[PATCH] D105269: [X86] AVX512FP16 instructions enabling 6/6

pengfei added inline comments. Comment at: llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp:3902 + case X86::VFCMADDCSHZr: + case X86::VFCMADDCSHZrb: + case X86::VFCMADDCSHZrbk: pengfei wrote: > LuoYuanke wrote: > > "b" means rounding. Right? > broadcasting Sorr

[PATCH] D105269: [X86] AVX512FP16 instructions enabling 6/6

LuoYuanke accepted this revision. LuoYuanke added a comment. This revision is now accepted and ready to land. LGTM, but may wait 1 or 2 days for the comments from others. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D105269/new/ https://reviews.llv

[PATCH] D105269: [X86] AVX512FP16 instructions enabling 6/6

pengfei added inline comments. Comment at: llvm/lib/Target/X86/X86ISelLowering.cpp:47419 + : X86ISD::VFCMADDC; + // FIXME: How we handle when FMF of FADD is different from CFMUL's? + CFmul = DAG.getNode(newOp, SDLoc(N), CVT,

[PATCH] D105269: [X86] AVX512FP16 instructions enabling 6/6

LuoYuanke added inline comments. Comment at: llvm/lib/Target/X86/X86ISelLowering.cpp:47419 + : X86ISD::VFCMADDC; + // FIXME: How we handle when FMF of FADD is different from CFMUL's? + CFmul = DAG.getNode(newOp, SDLoc(N), CV

[PATCH] D105269: [X86] AVX512FP16 instructions enabling 6/6

RKSimon added inline comments. Comment at: llvm/lib/Target/X86/X86ISelLowering.cpp:47419 + : X86ISD::VFCMADDC; + // FIXME: How we handle when FMF of FADD is different from CFMUL's? + CFmul = DAG.getNode(newOp, SDLoc(N), CVT,

[PATCH] D105269: [X86] AVX512FP16 instructions enabling 6/6

LuoYuanke added inline comments. Comment at: llvm/lib/Target/X86/X86ISelLowering.cpp:47419 + : X86ISD::VFCMADDC; + // FIXME: How we handle when FMF of FADD is different from CFMUL's? + CFmul = DAG.getNode(newOp, SDLoc(N), CV

[PATCH] D105269: [X86] AVX512FP16 instructions enabling 6/6

pengfei added a comment. Thanks for the review. Comment at: clang/test/CodeGen/X86/avx512fp16-builtins.c:4223 + +// CFC ADD PH + LuoYuanke wrote: > MADD? They are marks used when adding tests. We can remove them now. Repository: rG LLVM Github Monorepo CHA

[PATCH] D105269: [X86] AVX512FP16 instructions enabling 6/6

LuoYuanke added inline comments. Comment at: llvm/lib/Target/X86/X86InstrAVX512.td:13640 +(v4f32 (OpNode VR128X:$src1, VR128X:$src2)), +0, 0, 0, X86selects, "@earlyclobber $dst">, Sched<[sched.XMM]>; +defm rm : AVX512_maskable

[PATCH] D105269: [X86] AVX512FP16 instructions enabling 6/6

LuoYuanke added inline comments. Comment at: llvm/lib/Target/X86/X86InstrFoldTables.cpp:1852 + { X86::VFCMULCPHZrr, X86::VFCMULCPHZrm, 0 }, + { X86::VFCMULCSHZrr, X86::VFCMULCSHZrm, TB_NO_REVERSE }, { X86::VFMADDPD4Yrr,

[PATCH] D105269: [X86] AVX512FP16 instructions enabling 6/6

craig.topper added inline comments. Comment at: llvm/lib/Target/X86/X86InstrFoldTables.cpp:1852 + { X86::VFCMULCPHZrr, X86::VFCMULCPHZrm, 0 }, + { X86::VFCMULCSHZrr, X86::VFCMULCSHZrm, TB_NO_REVERSE }, { X86::VFMADDPD4Yrr,

[PATCH] D105269: [X86] AVX512FP16 instructions enabling 6/6

LuoYuanke added inline comments. Comment at: llvm/lib/Target/X86/X86InstrFoldTables.cpp:1852 + { X86::VFCMULCPHZrr, X86::VFCMULCPHZrm, 0 }, + { X86::VFCMULCSHZrr, X86::VFCMULCSHZrm, TB_NO_REVERSE }, { X86::VFMADDPD4Yrr,

[PATCH] D105269: [X86] AVX512FP16 instructions enabling 6/6

pengfei added inline comments. Comment at: llvm/lib/Target/X86/X86InstrFoldTables.cpp:1852 + { X86::VFCMULCPHZrr, X86::VFCMULCPHZrm, 0 }, + { X86::VFCMULCSHZrr, X86::VFCMULCSHZrm, TB_NO_REVERSE }, { X86::VFMADDPD4Yrr,

[PATCH] D105269: [X86] AVX512FP16 instructions enabling 6/6

pengfei added inline comments. Comment at: llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp:3902 + case X86::VFCMADDCSHZr: + case X86::VFCMADDCSHZrb: + case X86::VFCMADDCSHZrbk: LuoYuanke wrote: > "b" means rounding. Right? broadcasting Commen

[PATCH] D105269: [X86] AVX512FP16 instructions enabling 6/6

LuoYuanke added inline comments. Comment at: clang/test/CodeGen/X86/avx512fp16-builtins.c:4223 + +// CFC ADD PH + MADD? Comment at: clang/test/CodeGen/X86/avx512fp16-builtins.c:4315 + +// CF ADD PH + MADD? Co

[PATCH] D105269: [X86] AVX512FP16 instructions enabling 6/6

RKSimon added inline comments. Comment at: clang/lib/Headers/avx512fp16intrin.h:2900 + (__v4sf)(__m128h)(C), (__v4sf)(__m128h)(A), (__v4sf)(__m128h)(B), \ + (__mmask8)-1, (int)(R)) + Outer brackets Repository: rG LLVM Github Monorepo CHANGE

[PATCH] D105269: [X86] AVX512FP16 instructions enabling 6/6

LuoYuanke added inline comments. Comment at: llvm/test/CodeGen/X86/avx512cfma-intrinsics.ll:3 +; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=knl -mattr=+avx512bw -mattr=+avx512fp16 -mattr=+avx512vl | FileCheck %s + +declare <4 x float> @llvm.x86.avx512fp16.mask.vfmaddc.ph.1

[PATCH] D105269: [X86] AVX512FP16 instructions enabling 6/6

lebedev.ri added inline comments. Comment at: llvm/lib/Target/X86/X86ScheduleZnver3.td:64 - let CompleteModel = 1; + let CompleteModel = 0; } RKSimon wrote: > You could avoid this change if you add a scheduler class to whatever > instruction is complaining?

[PATCH] D105269: [X86] AVX512FP16 instructions enabling 6/6

RKSimon added inline comments. Comment at: llvm/lib/Target/X86/X86ScheduleZnver3.td:64 - let CompleteModel = 1; + let CompleteModel = 0; } You could avoid this change if you add a scheduler class to whatever instruction is complaining? Repository: rG LL