Conanap updated this revision to Diff 356528.
Conanap added a comment.
Properly updated the diff with arc.
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D105236/new/
https://reviews.llvm.org/D105236
Files:
clang/include/clang/Basic/BuiltinsPPC.de
Conanap updated this revision to Diff 356527.
Conanap added a comment.
Moved the pattern definitions and removed unnecessary guard.
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D105236/new/
https://reviews.llvm.org/D105236
Files:
llvm/include/ll
nemanjai added inline comments.
Comment at: llvm/lib/Target/PowerPC/PPCInstr64Bit.td:1724
+
+let Predicates = [HasP8Altivec] in {
+ def : Pat<(int_ppc_stdcx xoaddr:$dst, g8rc:$A),
lkail wrote:
> IIRC, `l(w|d)arx`, `st(w|d)cx` are supported very early and don't n
amyk added inline comments.
Comment at: llvm/include/llvm/IR/IntrinsicsPowerPC.td:1534
+ Intrinsic<[llvm_i64_ty], [llvm_ptr_ty], [IntrNoMem]>;
}
Is there an unintended change at the end?
Comment at: llvm/lib/Target/PowerPC
lkail added a comment.
The wording might be inaccurate. It's better to rephrase to 'Load and Reserve
and Store Conditional'.
Comment at: llvm/lib/Target/PowerPC/PPCInstr64Bit.td:1724
+
+let Predicates = [HasP8Altivec] in {
+ def : Pat<(int_ppc_stdcx xoaddr:$dst, g8rc:$A),
---
Conanap created this revision.
Herald added subscribers: steven.zhang, shchenz, jfb, kbarton, hiraditya,
nemanjai.
Conanap requested review of this revision.
Herald added projects: clang, LLVM.
Herald added subscribers: llvm-commits, cfe-commits.
This patch implaments the atomic load and store
