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@@ -7,5 +7,8 @@ tablegen(LLVM AArch64TargetParserDef.inc -gen-arm-target-def -I
${PROJECT_SOURCE
set(LLVM_TARGET_DEFINITIONS ${PROJECT_SOURCE_DIR}/lib/Target/RISCV/RISCV.td)
tablegen(LLVM RISCVTargetParserDef.inc -gen-riscv-target-def -I
${PROJECT_SOURCE_DIR}/lib/Target/RISCV/
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@@ -190,6 +192,31 @@ insertWaveSizeFeature(StringRef GPU, const Triple &T,
StringMap &Features);
} // namespace AMDGPU
+
+struct BasicSubtargetFeatureKV {
+ const char *Key; ///< K-V key string
+ unsigned Value; ///< K-V integer value
+
https://github.com/diggerlin updated
https://github.com/llvm/llvm-project/pull/144594
>From 2d0f536bdc6fc24f09053569a8c84056ffc31e0d Mon Sep 17 00:00:00 2001
From: zhijian lin
Date: Thu, 12 Jun 2025 13:38:13 -0400
Subject: [PATCH 1/5] [PowerPC] frontend get target feature from backend with
cp
https://github.com/diggerlin updated
https://github.com/llvm/llvm-project/pull/144594
>From 2d0f536bdc6fc24f09053569a8c84056ffc31e0d Mon Sep 17 00:00:00 2001
From: zhijian lin
Date: Thu, 12 Jun 2025 13:38:13 -0400
Subject: [PATCH 1/4] [PowerPC] frontend get target feature from backend with
cp
https://github.com/diggerlin updated
https://github.com/llvm/llvm-project/pull/144594
>From 2d0f536bdc6fc24f09053569a8c84056ffc31e0d Mon Sep 17 00:00:00 2001
From: zhijian lin
Date: Thu, 12 Jun 2025 13:38:13 -0400
Subject: [PATCH 1/3] [PowerPC] frontend get target feature from backend with
cp
diggerlin wrote:
the EmitTargetFeature.cpp will generated following content, I used PPC target
as example:
```
// Autogenerated by TargetFeatureEmitter.cpp
#ifdef GET_SUBTARGETFEATURES_ENUM
#undef GET_SUBTARGETFEATURES_ENUM
namespace llvm {
namespace PPC {
enum {
AIXOS = 0,
DeprecatedDST
https://github.com/diggerlin updated
https://github.com/llvm/llvm-project/pull/144594
>From 2d0f536bdc6fc24f09053569a8c84056ffc31e0d Mon Sep 17 00:00:00 2001
From: zhijian lin
Date: Thu, 12 Jun 2025 13:38:13 -0400
Subject: [PATCH 1/2] [PowerPC] frontend get target feature from backend with
cp
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@@ -8,6 +8,12 @@ if (HAS_WERROR_GLOBAL_CTORS AND NOT
LLVM_HAS_NOGLOBAL_CTOR_MUTEX)
SET(CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} -Werror=global-constructors")
endif()
+set(LLVM_TARGET_DEFINITIONS ${LLVM_MAIN_SRC_DIR}/lib/Target/PowerPC/PPC.td)
+
+tablegen(LLVM PPCGenSubtargetInfo
https://github.com/diggerlin created
https://github.com/llvm/llvm-project/pull/144594
1. The PR proceeds with a backend target hook to allow front-ends to determine
what target features are available in a compilation based on the CPU name.
2. Fix a backend target feature bug that supports HTM
@@ -8,6 +8,12 @@ if (HAS_WERROR_GLOBAL_CTORS AND NOT
LLVM_HAS_NOGLOBAL_CTOR_MUTEX)
SET(CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} -Werror=global-constructors")
endif()
+set(LLVM_TARGET_DEFINITIONS ${LLVM_MAIN_SRC_DIR}/lib/Target/PowerPC/PPC.td)
+
+tablegen(LLVM PPCGenSubtargetInfo
https://github.com/diggerlin updated
https://github.com/llvm/llvm-project/pull/137670
>From 97f10e6a0fb4c158359e79e24650f8fdf4d23ef2 Mon Sep 17 00:00:00 2001
From: zhijian
Date: Fri, 25 Apr 2025 13:09:47 +
Subject: [PATCH 01/11] implement getting target features from backend for
clang fron
https://github.com/diggerlin updated
https://github.com/llvm/llvm-project/pull/137670
>From 97f10e6a0fb4c158359e79e24650f8fdf4d23ef2 Mon Sep 17 00:00:00 2001
From: zhijian
Date: Fri, 25 Apr 2025 13:09:47 +
Subject: [PATCH 01/11] implement getting target features from backend for
clang fron
https://github.com/diggerlin updated
https://github.com/llvm/llvm-project/pull/137670
>From 97f10e6a0fb4c158359e79e24650f8fdf4d23ef2 Mon Sep 17 00:00:00 2001
From: zhijian
Date: Fri, 25 Apr 2025 13:09:47 +
Subject: [PATCH 01/10] implement getting target features from backend for
clang fron
diggerlin wrote:
@MaskRay, Just checking in to see if you have any further comments on the
patch. If not, I’d like to go ahead and proceed with landing it. Thanks!
https://github.com/llvm/llvm-project/pull/137670
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@@ -16,6 +16,7 @@
#include "llvm/ADT/StringMap.h"
#include "llvm/ADT/StringRef.h"
+#include "llvm/MC/MCSubtargetInfo.h"
diggerlin wrote:
I addressed your comment , would you help to take a look again? @MaskRay
https://github.com/llvm/llvm-project/pull/13767
https://github.com/diggerlin updated
https://github.com/llvm/llvm-project/pull/137670
>From 97f10e6a0fb4c158359e79e24650f8fdf4d23ef2 Mon Sep 17 00:00:00 2001
From: zhijian
Date: Fri, 25 Apr 2025 13:09:47 +
Subject: [PATCH 1/9] implement getting target features from backend for clang
fronte
https://github.com/diggerlin updated
https://github.com/llvm/llvm-project/pull/137670
>From 97f10e6a0fb4c158359e79e24650f8fdf4d23ef2 Mon Sep 17 00:00:00 2001
From: zhijian
Date: Fri, 25 Apr 2025 13:09:47 +
Subject: [PATCH 1/8] implement getting target features from backend for clang
fronte
https://github.com/diggerlin updated
https://github.com/llvm/llvm-project/pull/137670
>From 97f10e6a0fb4c158359e79e24650f8fdf4d23ef2 Mon Sep 17 00:00:00 2001
From: zhijian
Date: Fri, 25 Apr 2025 13:09:47 +
Subject: [PATCH 1/7] implement getting target features from backend for clang
fronte
https://github.com/diggerlin updated
https://github.com/llvm/llvm-project/pull/137670
Rate limit · GitHub
body {
background-color: #f6f8fa;
color: #24292e;
font-family: -apple-system,BlinkMacSystemFont,Segoe
UI,Helvetica,Arial,sans
diggerlin wrote:
Just a gentle follow-up — I’d truly appreciate any feedback when you have a
moment.
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https://github.com/diggerlin updated
https://github.com/llvm/llvm-project/pull/137670
>From 97f10e6a0fb4c158359e79e24650f8fdf4d23ef2 Mon Sep 17 00:00:00 2001
From: zhijian
Date: Fri, 25 Apr 2025 13:09:47 +
Subject: [PATCH 1/3] implement getting target features from backend for clang
fronte
https://github.com/diggerlin updated
https://github.com/llvm/llvm-project/pull/137670
>From 97f10e6a0fb4c158359e79e24650f8fdf4d23ef2 Mon Sep 17 00:00:00 2001
From: zhijian
Date: Fri, 25 Apr 2025 13:09:47 +
Subject: [PATCH 1/2] implement getting target features from backend for clang
fronte
https://github.com/diggerlin created
https://github.com/llvm/llvm-project/pull/137670
1. The PR proceeds with a backend target hook to allow front-ends to determine
what features are available in a compilation based on the CPU name.
2. Fix a backend target feature bug that supports HTM for Powe
@@ -609,13 +609,15 @@ bool PPCTargetInfo::initFeatureMap(
// Privileged instructions are off by default.
Features["privileged"] = false;
- // The code generated by the -maix-small-local-[exec|dynamic]-tls option is
- // turned off by default.
- Features["aix-small-local
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https://github.com/diggerlin created
https://github.com/llvm/llvm-project/pull/130994
There are some variables in the PPC.h which are defined and assigned a value to
them,
but never be used, remove the code related to the variables.
>From 45a51fd46aeedd73fbfe5d9ae493eeb9084bc98c Mon Sep 17 00:
https://github.com/diggerlin approved this pull request.
https://github.com/llvm/llvm-project/pull/90619
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@@ -6141,24 +6141,23 @@ void PPCDAGToDAGISel::Select(SDNode *N) {
assert((isPPC64 || (isAIXABI && !isPPC64)) && "We are dealing with 64-bit"
" ELF/AIX or 32-bit AIX in the following.");
-// Transforms the ISD::TOC_ENTRY node for 32-bit AIX large code model m
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@@ -479,14 +479,6 @@ static void addTocDataOptions(const llvm::opt::ArgList
&Args,
return false;
}();
- // Currently only supported for small code model.
- if (TOCDataGloballyinEffect &&
- (Args.getLastArgValue(options::OPT_mcmodel_EQ).equals("large") ||
-
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diggerlin wrote:
> @diggerlin ,
>
> > > can we implement -fcomplex-ppc-gnu-abi as "-msoft-float" ? what is your
> > > opinion ?
> > > that was not the intent here and we need to consultant ABI reference
> > > regrading the same ,before we decide on implementation .
I think I do not express c
diggerlin wrote:
I do not further comment on the PR,
but I have worry about that , the PR have different mechanism with
"-msoft-float" , the -msoft-float pass "use-soft-float"="true" in the IR, the
llc will l put float parameter in the GPR, but the PR implement
`-fcomplex-ppc-gnu-abi` in the
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diggerlin wrote:
please do not merge the commit if possible, merging the commit make the review
difficult, We want to compare what change between the two commit when we
review. otherwise we have review the patch from scratch.
https://github.com/llvm/llvm-project/pull/77732
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@@ -0,0 +1,15 @@
+// RUN: not %clang %s --target=x86_64 -fcomplex-ppc-gnu-abi 2>&1 \
+// RUN: | FileCheck %s -check-prefix=X86_64
+// X86_64: error: unsupported option '-fcomplex-ppc-gnu-abi' for target
'x86_64'
+
+// RUN: not %clang %s --target=ppc64 -fcomplex-ppc-gnu-abi 2>
@@ -0,0 +1,286 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
UTC_ARGS: --version 2
+
+// RUN: %clang_cc1 -triple powerpc-unknown-linux-gnu -fcomplex-ppc-gnu-abi \
+// RUN: -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK-GNU-DEF
+// RUN
@@ -0,0 +1,286 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
UTC_ARGS: --version 2
+
+// RUN: %clang_cc1 -triple powerpc-unknown-linux-gnu -fcomplex-ppc-gnu-abi \
+// RUN: -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK-GNU-DEF
+// RUN
@@ -0,0 +1,286 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
UTC_ARGS: --version 2
+
+// RUN: %clang_cc1 -triple powerpc-unknown-linux-gnu -fcomplex-ppc-gnu-abi \
+// RUN: -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK-GNU-DEF
+// RUN
@@ -330,8 +330,12 @@ namespace {
class PPC32_SVR4_ABIInfo : public DefaultABIInfo {
bool IsSoftFloatABI;
bool IsRetSmallStructInRegABI;
+ // Size of GPR in bits.
+ static const unsigned RegLen = 32;
diggerlin wrote:
suggest change RegLen to GPRBits as
https://github.com/diggerlin closed
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https://github.com/llvm/llvm-project/pull/82809
>From 557e7163d744890aadfa703a81a0c4f2cd112517 Mon Sep 17 00:00:00 2001
From: zhijian
Date: Fri, 23 Feb 2024 13:23:18 -0500
Subject: [PATCH 1/8] Implement a subset of builtin_cpu_supports() features
---
clang
https://github.com/diggerlin updated
https://github.com/llvm/llvm-project/pull/82809
>From 557e7163d744890aadfa703a81a0c4f2cd112517 Mon Sep 17 00:00:00 2001
From: zhijian
Date: Fri, 23 Feb 2024 13:23:18 -0500
Subject: [PATCH 1/7] Implement a subset of builtin_cpu_supports() features
---
clang
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@@ -0,0 +1,350 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
UTC_ARGS: --version 2
+
+// RUN: %clang_cc1 -triple powerpc-unknown-linux-gnu -fcomplex-ppc-gnu-abi \
+// RUN: -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK-GNU-DEF
+// RUN
@@ -5585,6 +5585,15 @@ void Clang::ConstructJob(Compilation &C, const JobAction
&JA,
}
}
+ if (Arg *A = Args.getLastArg(options::OPT_fcomplex_ppc_gnu_abi)) {
+if (!TC.getTriple().isPPC32() || !TC.getTriple().isOSBinFormatELF()) {
+ D.Diag(diag::err_drv_unsuppo
@@ -396,12 +405,80 @@ CharUnits
PPC32_SVR4_ABIInfo::getParamTypeAlignment(QualType Ty) const {
return CharUnits::fromQuantity(4);
}
+ABIArgInfo PPC32_SVR4_ABIInfo::handleComplex(uint64_t &TypeSize) const {
+ llvm::Type *ElemTy;
+ unsigned RegsNeeded; // Registers Needed f
@@ -0,0 +1,350 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
UTC_ARGS: --version 2
+
+// RUN: %clang_cc1 -triple powerpc-unknown-linux-gnu -fcomplex-ppc-gnu-abi \
+// RUN: -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK-GNU-DEF
+// RUN
@@ -396,12 +405,80 @@ CharUnits
PPC32_SVR4_ABIInfo::getParamTypeAlignment(QualType Ty) const {
return CharUnits::fromQuantity(4);
}
+ABIArgInfo PPC32_SVR4_ABIInfo::handleComplex(uint64_t &TypeSize) const {
+ llvm::Type *ElemTy;
+ unsigned RegsNeeded; // Registers Needed f
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@@ -396,12 +405,85 @@ CharUnits
PPC32_SVR4_ABIInfo::getParamTypeAlignment(QualType Ty) const {
return CharUnits::fromQuantity(4);
}
+ABIArgInfo PPC32_SVR4_ABIInfo::handleComplex(uint64_t &TypeSize) const {
+ llvm::Type *ElemTy;
+ unsigned RegsNeeded; // Registers Needed f
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@@ -396,12 +405,85 @@ CharUnits
PPC32_SVR4_ABIInfo::getParamTypeAlignment(QualType Ty) const {
return CharUnits::fromQuantity(4);
}
+ABIArgInfo PPC32_SVR4_ABIInfo::handleComplex(uint64_t &TypeSize) const {
+ llvm::Type *ElemTy;
+ unsigned RegsNeeded; // Registers Needed f
@@ -421,6 +503,11 @@ ABIArgInfo PPC32_SVR4_ABIInfo::classifyReturnType(QualType
RetTy) const {
}
}
+ bool IsComplexInRegABI =
+ getCodeGenOpts().getComplexInRegABI() == CodeGenOptions::CMPLX_InGPR;
+ if (IsComplexInRegABI && RetTy->isAnyComplexType())
---
@@ -0,0 +1,306 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
UTC_ARGS: --version 2
+
+// RUN: %clang_cc1 -triple powerpc-unknown-linux-gnu \
+// RUN: -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK-DEF
+// RUN: %clang_cc1 -triple power
@@ -337,12 +347,58 @@ CharUnits
PPC32_SVR4_ABIInfo::getParamTypeAlignment(QualType Ty) const {
return CharUnits::fromQuantity(4);
}
+ABIArgInfo PPC32_SVR4_ABIInfo::handleComplex(uint64_t &TypeSize) const {
+ llvm::Type *ElemTy;
+ unsigned RegsNeeded; // Registers Needed f
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@@ -337,12 +347,58 @@ CharUnits
PPC32_SVR4_ABIInfo::getParamTypeAlignment(QualType Ty) const {
return CharUnits::fromQuantity(4);
}
+ABIArgInfo PPC32_SVR4_ABIInfo::handleComplex(uint64_t &TypeSize) const {
+ llvm::Type *ElemTy;
+ unsigned RegsNeeded; // Registers Needed f
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@@ -396,12 +407,77 @@ CharUnits
PPC32_SVR4_ABIInfo::getParamTypeAlignment(QualType Ty) const {
return CharUnits::fromQuantity(4);
}
+ABIArgInfo PPC32_SVR4_ABIInfo::handleComplex(uint64_t &TypeSize) const {
+ llvm::Type *ElemTy;
+ unsigned RegsNeeded; // Registers Needed f
@@ -337,12 +347,58 @@ CharUnits
PPC32_SVR4_ABIInfo::getParamTypeAlignment(QualType Ty) const {
return CharUnits::fromQuantity(4);
}
+ABIArgInfo PPC32_SVR4_ABIInfo::handleComplex(uint64_t &TypeSize) const {
+ llvm::Type *ElemTy;
+ unsigned RegsNeeded; // Registers Needed f
@@ -330,22 +330,33 @@ namespace {
class PPC32_SVR4_ABIInfo : public DefaultABIInfo {
bool IsSoftFloatABI;
bool IsRetSmallStructInRegABI;
+ bool IsComplexInRegABI;
diggerlin wrote:
do we need a new data member `IsComplexInRegABI` here ? (there are several
@@ -420,6 +496,10 @@ ABIArgInfo PPC32_SVR4_ABIInfo::classifyReturnType(QualType
RetTy) const {
return ABIArgInfo::getDirect(CoerceTy);
}
}
+ if (IsComplexInRegABI && RetTy->isAnyComplexType()) {
+assert(RetTy->isAnyComplexType() && "RetTy must be Complex type.
@@ -337,12 +347,58 @@ CharUnits
PPC32_SVR4_ABIInfo::getParamTypeAlignment(QualType Ty) const {
return CharUnits::fromQuantity(4);
}
+ABIArgInfo PPC32_SVR4_ABIInfo::handleComplex(uint64_t &TypeSize) const {
+ llvm::Type *ElemTy;
+ unsigned RegsNeeded; // Registers Needed f
https://github.com/diggerlin updated
https://github.com/llvm/llvm-project/pull/82809
>From 557e7163d744890aadfa703a81a0c4f2cd112517 Mon Sep 17 00:00:00 2001
From: zhijian
Date: Fri, 23 Feb 2024 13:23:18 -0500
Subject: [PATCH 1/6] Implement a subset of builtin_cpu_supports() features
---
clang
https://github.com/diggerlin updated
https://github.com/llvm/llvm-project/pull/82809
>From 557e7163d744890aadfa703a81a0c4f2cd112517 Mon Sep 17 00:00:00 2001
From: zhijian
Date: Fri, 23 Feb 2024 13:23:18 -0500
Subject: [PATCH 1/5] Implement a subset of builtin_cpu_supports() features
---
clang
https://github.com/diggerlin edited
https://github.com/llvm/llvm-project/pull/77732
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https://github.com/diggerlin edited
https://github.com/llvm/llvm-project/pull/77732
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@@ -337,12 +347,58 @@ CharUnits
PPC32_SVR4_ABIInfo::getParamTypeAlignment(QualType Ty) const {
return CharUnits::fromQuantity(4);
}
+ABIArgInfo PPC32_SVR4_ABIInfo::handleComplex(uint64_t &TypeSize) const {
+ llvm::Type *ElemTy;
+ unsigned RegsNeeded; // Registers Needed f
https://github.com/diggerlin edited
https://github.com/llvm/llvm-project/pull/77732
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@@ -0,0 +1,177 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
UTC_ARGS: --version 2
+
+// RUN: %clang_cc1 -triple powerpc-unknown-linux-gnu \
+// RUN: -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK-DEF
+// RUN: %clang_cc1 -triple power
https://github.com/diggerlin edited
https://github.com/llvm/llvm-project/pull/77732
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@@ -337,12 +347,58 @@ CharUnits
PPC32_SVR4_ABIInfo::getParamTypeAlignment(QualType Ty) const {
return CharUnits::fromQuantity(4);
}
+ABIArgInfo PPC32_SVR4_ABIInfo::handleComplex(uint64_t &TypeSize) const {
+ llvm::Type *ElemTy;
+ unsigned RegsNeeded; // Registers Needed f
https://github.com/diggerlin edited
https://github.com/llvm/llvm-project/pull/77732
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https://github.com/diggerlin edited
https://github.com/llvm/llvm-project/pull/77732
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