[PATCH] D122556: [RISCV] Add definitions for Xiangshan processors.

SForeKeeper added inline comments. Comment at: llvm/include/llvm/Support/RISCVTargetParser.def:35 +PROC(XIANGSHAN_YANQIHU,{"xiangshan-yanqihu"},FK_64BIT,{"rv64gc"}) +PROC(XIANGSHAN_NANHU,{"xiangshan-nanhu"},FK_64BIT,{"rv64imafdc_zba_zbb_zbc_zbs_zbkb_zbkc_zbkx_zknd_zkne_zknh_zksed

[PATCH] D122556: [RISCV] Add definitions for Xiangshan processors.

SForeKeeper created this revision. Herald added subscribers: s, VincentWu, luke957, vkmr, frasercrmck, evandro, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, jrtc27, kito-cheng, niosHD, sabuasa