https://github.com/lizhengxing approved this pull request.
https://github.com/llvm/llvm-project/pull/128894
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lizhengxing wrote:
It's a name mangling issue on Windows (or maybe other OS).
For example, the check `// CHECK-LABEL:
define{{.*}}**_ZN1C4testEi**(ptr{{[^,]*}} %this, i32{{.*}} %p)` in
fake-use-this.cpp expects the string contains `_ZN1C4testEi`.
However, the compiler on Windows outputs `d
https://github.com/lizhengxing closed
https://github.com/llvm/llvm-project/pull/121521
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https://github.com/llvm/llvm-project/pull/121521
>From 21114c408baaa9309e3370d46a4ee196cc4f714a Mon Sep 17 00:00:00 2001
From: Zhengxing Li
Date: Thu, 2 Jan 2025 12:30:18 -0800
Subject: [PATCH 1/2] [HLSL][SPIR-V] implement SV_GroupID semantic lowering
The
@@ -0,0 +1,82 @@
+; RUN: llc -O0 -verify-machineinstrs -mtriple=spirv-vulkan-unknown %s -o - |
FileCheck %s
+; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-vulkan-unknown %s -o -
-filetype=obj | spirv-val %}
+
+; This file generated from the following command:
+; clang -cc1 -t
@@ -0,0 +1,82 @@
+; RUN: llc -O0 -verify-machineinstrs -mtriple=spirv-vulkan-unknown %s -o - |
FileCheck %s
+; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-vulkan-unknown %s -o -
-filetype=obj | spirv-val %}
+
+; This file generated from the following command:
+; clang -cc1 -t
https://github.com/lizhengxing created
https://github.com/llvm/llvm-project/pull/121521
The HLSL SV_GroupID semantic attribute is lowered into @llvm.spv.group.id
intrinsic in LLVM IR for SPIR-V target.
In the SPIR-V backend, this is now translated to a `WorkgroupId` builtin
variable.
Fixes #
https://github.com/lizhengxing updated
https://github.com/llvm/llvm-project/pull/117781
>From e66f451e1db4c321acbfac578fa57f286af2fe27 Mon Sep 17 00:00:00 2001
From: Zhengxing Li
Date: Wed, 13 Nov 2024 10:54:16 -0800
Subject: [PATCH 1/4] [HLSL] Implement SV_GroupThreadId semantic
Support SV_Gr
lizhengxing wrote:
@sudonatalie
Hello Natalie,
Could you help review this PR when you're available since it will modify your
changes (https://github.com/llvm/llvm-project/pull/82536), Thanks.
https://github.com/llvm/llvm-project/pull/117781
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@@ -2851,7 +2851,21 @@ bool SPIRVInstructionSelector::selectIntrinsic(Register
ResVReg,
.constrainAllUses(TII, TRI, RBI);
break;
case Intrinsic::spv_thread_id:
-return selectSpvThreadId(ResVReg, ResType, I);
+// The HLSL SV_DispatchThreadID semantic is
@@ -3606,6 +3613,32 @@ bool
SPIRVInstructionSelector::selectSpvThreadId(Register ResVReg,
return Result && MIB.constrainAllUses(TII, TRI, RBI);
}
+bool SPIRVInstructionSelector::selectSpvThreadId(Register ResVReg,
+ const SPIR
@@ -3606,6 +3613,32 @@ bool
SPIRVInstructionSelector::selectSpvThreadId(Register ResVReg,
return Result && MIB.constrainAllUses(TII, TRI, RBI);
}
+bool SPIRVInstructionSelector::selectSpvThreadId(Register ResVReg,
+ const SPIR
https://github.com/lizhengxing updated
https://github.com/llvm/llvm-project/pull/117781
>From 2941d87dbaf091aa443ad57ce55e98e7bab83d2b Mon Sep 17 00:00:00 2001
From: Zhengxing Li
Date: Wed, 13 Nov 2024 10:54:16 -0800
Subject: [PATCH 1/4] [HLSL] Implement SV_GroupThreadId semantic
Support SV_Gr
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https://github.com/llvm/llvm-project/pull/117781
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@@ -3606,6 +3613,32 @@ bool
SPIRVInstructionSelector::selectSpvThreadId(Register ResVReg,
return Result && MIB.constrainAllUses(TII, TRI, RBI);
}
+bool SPIRVInstructionSelector::selectSpvThreadId(Register ResVReg,
+ const SPIR
https://github.com/lizhengxing edited
https://github.com/llvm/llvm-project/pull/117781
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@@ -389,6 +389,11 @@ llvm::Value *CGHLSLRuntime::emitInputSemantic(IRBuilder<>
&B,
CGM.getIntrinsic(getThreadIdIntrinsic());
return buildVectorInput(B, ThreadIDIntrinsic, Ty);
}
+ if (D.hasAttr()) {
+llvm::Function *GroupThreadIDIntrinsic =
+CGM.getI
@@ -2,15 +2,18 @@
// RUN: %clang_cc1 -triple dxil-pc-shadermodel6.0-mesh -hlsl-entry CSMain -x
hlsl -finclude-default-header -verify -o - %s
[numthreads(8,8,1)]
-// expected-error@+3 {{attribute 'SV_GroupIndex' is unsupported in 'mesh'
shaders, requires compute}}
-// expect
https://github.com/lizhengxing updated
https://github.com/llvm/llvm-project/pull/117781
>From 2941d87dbaf091aa443ad57ce55e98e7bab83d2b Mon Sep 17 00:00:00 2001
From: Zhengxing Li
Date: Wed, 13 Nov 2024 10:54:16 -0800
Subject: [PATCH 1/3] [HLSL] Implement SV_GroupThreadId semantic
Support SV_Gr
@@ -2,15 +2,18 @@
// RUN: %clang_cc1 -triple dxil-pc-shadermodel6.0-mesh -hlsl-entry CSMain -x
hlsl -finclude-default-header -verify -o - %s
[numthreads(8,8,1)]
-// expected-error@+3 {{attribute 'SV_GroupIndex' is unsupported in 'mesh'
shaders, requires compute}}
-// expect
@@ -2,15 +2,18 @@
// RUN: %clang_cc1 -triple dxil-pc-shadermodel6.0-mesh -hlsl-entry CSMain -x
hlsl -finclude-default-header -verify -o - %s
[numthreads(8,8,1)]
-// expected-error@+3 {{attribute 'SV_GroupIndex' is unsupported in 'mesh'
shaders, requires compute}}
-// expect
lizhengxing wrote:
> Do we need to consider how spirv handles this? Otherwise, LGTM
This PR is similar to the one for SV_GroupID. We don't consider the spirv part
for both PRs.
https://github.com/llvm/llvm-project/pull/117781
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@@ -49,3 +49,28 @@ void CSMain3_GID(uint3 : SV_GroupID) {
// CHECK-NEXT: ParmVarDecl 0x{{[0-9a-fA-F]+}} <{{.*}}> col:24 'uint3'
// CHECK-NEXT: HLSLSV_GroupIDAttr
}
+
+[numthreads(8,8,1)]
+void CSMain_GThreadID(uint ID : SV_GroupThreadID) {
+// CHECK: FunctionDecl 0x{{[0-9a-fA-F
https://github.com/lizhengxing ready_for_review
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https://github.com/lizhengxing created
https://github.com/llvm/llvm-project/pull/117781
Support SV_GroupThreadId attribute.
Translate it into dx.thread.id.in.group in clang codeGen.
Fixes: #70122
>From 9d5ffe00f2a1093ca2c28cce184cad0324f53de2 Mon Sep 17 00:00:00 2001
From: Zhengxing Li
Date:
@@ -784,6 +785,17 @@ void SemaHLSL::handleSV_DispatchThreadIDAttr(Decl *D,
const ParsedAttr &AL) {
HLSLSV_DispatchThreadIDAttr(getASTContext(), AL));
}
+void SemaHLSL::handleSV_GroupIDAttr(Decl *D, const ParsedAttr &AL) {
+ auto *VD = cast(D);
+ if (!isLega
https://github.com/lizhengxing updated
https://github.com/llvm/llvm-project/pull/115911
>From 6418461717614d5879688d32a0ab9bf9d9137328 Mon Sep 17 00:00:00 2001
From: Zhengxing Li
Date: Tue, 1 Oct 2024 15:13:34 -0700
Subject: [PATCH 1/4] [HLSL] Implement SV_GroupID semantic
Support SV_GroupID a
https://github.com/lizhengxing updated
https://github.com/llvm/llvm-project/pull/115911
>From 6418461717614d5879688d32a0ab9bf9d9137328 Mon Sep 17 00:00:00 2001
From: Zhengxing Li
Date: Tue, 1 Oct 2024 15:13:34 -0700
Subject: [PATCH 1/3] [HLSL] Implement SV_GroupID semantic
Support SV_GroupID a
@@ -27,3 +27,25 @@ struct ST2 {
static uint X : SV_DispatchThreadID;
uint s : SV_DispatchThreadID;
};
+
+[numthreads(8,8,1)]
+// expected-error@+1 {{attribute 'SV_GroupID' only applies to a field or
parameter of type 'uint/uint2/uint3'}}
+void CSMain_GID(float ID : SV_
https://github.com/lizhengxing edited
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@@ -0,0 +1,21 @@
+// RUN: %clang_cc1 -triple dxil-pc-shadermodel6.3-library -x hlsl -emit-llvm
-finclude-default-header -disable-llvm-passes -o - %s | FileCheck %s
+
+// Make sure SV_GroupID translated into dx.group.id.
+
+// CHECK: define void @foo()
+// CHECK: %[[#ID:]] = cal
https://github.com/lizhengxing updated
https://github.com/llvm/llvm-project/pull/115911
>From 6418461717614d5879688d32a0ab9bf9d9137328 Mon Sep 17 00:00:00 2001
From: Zhengxing Li
Date: Tue, 1 Oct 2024 15:13:34 -0700
Subject: [PATCH 1/2] [HLSL] Implement SV_GroupID semantic
Support SV_GroupID a
https://github.com/lizhengxing edited
https://github.com/llvm/llvm-project/pull/115911
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@@ -0,0 +1,21 @@
+// RUN: %clang_cc1 -triple dxil-pc-shadermodel6.3-library -x hlsl -emit-llvm
-finclude-default-header -disable-llvm-passes -o - %s | FileCheck %s
+
+// Make sure SV_GroupID translated into dx.group.id.
+
+// CHECK: define void @foo()
+// CHECK: %[[#ID:]] = cal
https://github.com/lizhengxing updated
https://github.com/llvm/llvm-project/pull/115911
>From 6418461717614d5879688d32a0ab9bf9d9137328 Mon Sep 17 00:00:00 2001
From: Zhengxing Li
Date: Tue, 1 Oct 2024 15:13:34 -0700
Subject: [PATCH] [HLSL] Implement SV_GroupID semantic
Support SV_GroupID attri
https://github.com/lizhengxing created
https://github.com/llvm/llvm-project/pull/115911
Support SV_GroupID attribute.
Translate it into dx.group.id in clang codeGen.
Fixes: #70120
>From 2e231d66b405ffec843651f5d4260db91a0ed6a5 Mon Sep 17 00:00:00 2001
From: Zhengxing Li
Date: Tue, 1 Oct 2024
lizhengxing wrote:
@farzonl Could you help to merge this PR? The 2 failing checks are in libc++
since yesterday. It might be caused by
[#107638](https://github.com/llvm/llvm-project/pull/107638).
@hekota pinged the authors of
[#107638](https://github.com/llvm/llvm-project/pull/107638) to see
https://github.com/lizhengxing updated
https://github.com/llvm/llvm-project/pull/108849
>From 96a8f95b6e6cc9b59c856afc3297454ede241487 Mon Sep 17 00:00:00 2001
From: Zhengxing Li
Date: Fri, 13 Sep 2024 13:19:31 -0700
Subject: [PATCH] [HLSL] Implementation of the elementwise fmod builtin
This c
https://github.com/lizhengxing updated
https://github.com/llvm/llvm-project/pull/108849
>From a48abd93d9261a9026531bfd69aff52b0374d8d8 Mon Sep 17 00:00:00 2001
From: Zhengxing Li
Date: Fri, 13 Sep 2024 13:19:31 -0700
Subject: [PATCH] [HLSL] Implementation of the elementwise fmod builtin
This c
https://github.com/lizhengxing updated
https://github.com/llvm/llvm-project/pull/108849
>From a48abd93d9261a9026531bfd69aff52b0374d8d8 Mon Sep 17 00:00:00 2001
From: Zhengxing Li
Date: Fri, 13 Sep 2024 13:19:31 -0700
Subject: [PATCH] [HLSL] Implementation of the elementwise fmod builtin
This c
@@ -1645,6 +1645,18 @@ bool SemaHLSL::CheckBuiltinFunctionCall(unsigned
BuiltinID, CallExpr *TheCall) {
return true;
break;
}
+ case Builtin::BI__builtin_elementwise_fmod: {
lizhengxing wrote:
Done.
https://github.com/llvm/llvm-project/pull/1088
@@ -0,0 +1,37 @@
+
+// RUN: %clang_cc1 -finclude-default-header -triple
dxil-pc-shadermodel6.6-library %s -fnative-half-type -emit-llvm-only
-disable-llvm-passes -verify -verify-ignore-unexpected
+
+float test_too_few_arg() {
+ return __builtin_elementwise_fmod();
+ // expecte
https://github.com/lizhengxing updated
https://github.com/llvm/llvm-project/pull/108849
>From 9ed71b8fb37dbc72bd5378c3b6be534b7bb51f60 Mon Sep 17 00:00:00 2001
From: Zhengxing Li
Date: Fri, 13 Sep 2024 13:19:31 -0700
Subject: [PATCH] [HLSL] Implementation of the elementwise fmod builtin
This c
https://github.com/lizhengxing updated
https://github.com/llvm/llvm-project/pull/108849
>From 516d0e5c84df23c91b2ec430bcfb48da0d5ea0be Mon Sep 17 00:00:00 2001
From: Zhengxing Li
Date: Fri, 13 Sep 2024 13:19:31 -0700
Subject: [PATCH] [HLSL] Implementation of the elementwise fmod builtin
This c
lizhengxing wrote:
> change the title of this PR to remove the word intrinsic. That word has a
> specific meaning in LLVM and folks might get confused. Something like:
> `[HLSL] Implementation of the fmod API`.
>
> If you really want to use the word intrinsic then just reuse the HLSL keyword
lizhengxing wrote:
Done.
https://github.com/llvm/llvm-project/pull/108849
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lizhengxing wrote:
> This LGTM. There is one last thing we might want to do. But I'm not requiring
> it for sign off. We ussually add elementwise math builtins here:
>
> * `clang/test/CodeGen/builtins-elementwise-math.c`
> * `clang/test/CodeGen/strictfp-elementwise-bulitins.cpp`
> * `clang/test
https://github.com/lizhengxing updated
https://github.com/llvm/llvm-project/pull/108849
>From 516d0e5c84df23c91b2ec430bcfb48da0d5ea0be Mon Sep 17 00:00:00 2001
From: Zhengxing Li
Date: Fri, 13 Sep 2024 13:19:31 -0700
Subject: [PATCH] [HLSL] Implementation of the elementwise fmod builtin
This c
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https://github.com/llvm/llvm-project/pull/108849
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@@ -0,0 +1,38 @@
+
+// RUN: %clang_cc1 -finclude-default-header -triple
dxil-pc-shadermodel6.6-library %s -fnative-half-type -emit-llvm-only
-disable-llvm-passes -verify -verify-ignore-unexpected
+
+float test_too_few_arg() {
lizhengxing wrote:
Done. Add 2 doub
lizhengxing wrote:
> We should announce `__builtin_elementwise_fmod` here:
> `clang/docs/ReleaseNotes.rst` See @spall PR where we just did this:
> https://github.com/llvm/llvm-project/pull/108121/files
Done.
https://github.com/llvm/llvm-project/pull/108849
@@ -0,0 +1,79 @@
+// DirectX target:
+//
+// -- Native Half support test ---
+//
+// RUN: %clang_cc1 -finclude-default-header -x hlsl -triple \
+// RUN: dxil-pc-shadermodel6.3-library %s -fnative-half-type \
+// RUN: -emit-llvm -disable-llvm-passes -o - | FileC
@@ -0,0 +1,38 @@
+
+// RUN: %clang_cc1 -finclude-default-header -triple
dxil-pc-shadermodel6.6-library %s -fnative-half-type -emit-llvm-only
-disable-llvm-passes -verify -verify-ignore-unexpected
+
+float test_too_few_arg() {
+ return __builtin_elementwise_fmod();
+ // expecte
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https://github.com/llvm/llvm-project/pull/108849
>From 42015171d9756e3566021530a1e9479aad8de2c4 Mon Sep 17 00:00:00 2001
From: Zhengxing Li
Date: Fri, 13 Sep 2024 13:19:31 -0700
Subject: [PATCH] [HLSL] Implementation of the fmod intrinsic
This change impl
lizhengxing wrote:
> The SPIRV frem testing doesn't appear to be complete in
> `llvm/test/CodeGen/SPIRV/instructions/scalar-floating-point-arithmetic.ll`
> `llvm/test/CodeGen/SPIRV/instructions/vector-floating-point-arithmetic.ll`
>
> for all our cases we defined in `hlsl_intrinsics.h`. Should
@@ -0,0 +1,38 @@
+
+// RUN: %clang_cc1 -finclude-default-header -triple
dxil-pc-shadermodel6.6-library %s -fnative-half-type -emit-llvm-only
-disable-llvm-passes -verify -verify-ignore-unexpected
+
+float test_too_few_arg() {
+ return __builtin_elementwise_fmod();
+ // expecte
@@ -4782,6 +4782,12 @@ def HLSLStep: LangBuiltin<"HLSL_LANG"> {
let Prototype = "void(...)";
}
+def HLSLFmod : LangBuiltin<"HLSL_LANG"> {
+ let Spellings = ["__builtin_hlsl_elementwise_fmod"];
lizhengxing wrote:
Done.
https://github.com/llvm/llvm-project/
@@ -18709,6 +18709,25 @@ Value *CodeGenFunction::EmitHLSLBuiltinExpr(unsigned
BuiltinID,
CGM.getHLSLRuntime().getNormalizeIntrinsic(), ArrayRef{X},
nullptr, "hlsl.normalize");
}
+ case Builtin::BI__builtin_hlsl_elementwise_fmod: {
lizhengxin
@@ -90,4 +90,5 @@ def int_dx_rsqrt : DefaultAttrsIntrinsic<[llvm_anyfloat_ty],
[LLVMMatchType<0>]
def int_dx_wave_is_first_lane : DefaultAttrsIntrinsic<[llvm_i1_ty], [],
[IntrConvergent]>;
def int_dx_sign : DefaultAttrsIntrinsic<[LLVMScalarOrSameVectorWidth<0,
llvm_i32_ty>],
@@ -0,0 +1,38 @@
+
+// RUN: %clang_cc1 -finclude-default-header -triple
dxil-pc-shadermodel6.6-library %s -fnative-half-type -emit-llvm-only
-disable-llvm-passes -verify -verify-ignore-unexpected
+
+float test_too_few_arg() {
+ return __builtin_hlsl_elementwise_fmod();
+ // ex
https://github.com/lizhengxing updated
https://github.com/llvm/llvm-project/pull/108849
>From a12d65fabcc87a50e6c0d83e9f69862bb859b894 Mon Sep 17 00:00:00 2001
From: Zhengxing Li
Date: Fri, 13 Sep 2024 13:19:31 -0700
Subject: [PATCH] [HLSL] Implementation of the fmod intrinsic
This change impl
@@ -0,0 +1,79 @@
+// DirectX target:
+//
+// -- Native Half support test ---
+//
+// RUN: %clang_cc1 -finclude-default-header -x hlsl -triple \
+// RUN: dxil-pc-shadermodel6.3-library %s -fnative-half-type \
+// RUN: -emit-llvm -disable-llvm-passes -o - | FileC
https://github.com/lizhengxing edited
https://github.com/llvm/llvm-project/pull/108849
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https://github.com/llvm/llvm-project/pull/108849
>From 9942e3129cdb37969adceb40c42ea17042c61b2b Mon Sep 17 00:00:00 2001
From: Zhengxing Li
Date: Fri, 13 Sep 2024 13:19:31 -0700
Subject: [PATCH] [HLSL] Implementation of the fmod intrinsic
This change impl
@@ -90,4 +90,5 @@ def int_dx_rsqrt : DefaultAttrsIntrinsic<[llvm_anyfloat_ty],
[LLVMMatchType<0>]
def int_dx_wave_is_first_lane : DefaultAttrsIntrinsic<[llvm_i1_ty], [],
[IntrConvergent]>;
def int_dx_sign : DefaultAttrsIntrinsic<[LLVMScalarOrSameVectorWidth<0,
llvm_i32_ty>],
https://github.com/lizhengxing created
https://github.com/llvm/llvm-project/pull/108849
This change implements the frontend for #99118
Builtins.td - add the fmod builtin
CGBuiltin.cpp - add the builtin to DirectX intrinsic mapping
hlsl_intrinsics.h - add the fmod api
SemaH
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