https://github.com/miloserdow edited
https://github.com/llvm/llvm-project/pull/166022
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https://github.com/miloserdow updated
https://github.com/llvm/llvm-project/pull/166022
>From 1653040f9f259adec342ced3a5bdbd43824cffe9 Mon Sep 17 00:00:00 2001
From: Vladimir Miloserdov
Date: Sat, 1 Nov 2025 21:35:52 +
Subject: [PATCH] [AArch64] Implement "rZ" inline asm constraint
Add supp
https://github.com/miloserdow updated
https://github.com/llvm/llvm-project/pull/166022
>From 9482083bb6cb4c9790f325674cf53fad9d38d580 Mon Sep 17 00:00:00 2001
From: Vladimir Miloserdov
Date: Sat, 1 Nov 2025 21:35:52 +
Subject: [PATCH] [AArch64] Implement "rZ" inline asm constraint
Add supp
https://github.com/miloserdow created
https://github.com/llvm/llvm-project/pull/166022
Add support for the "rZ" inline assembly constraint. The constraint accepts
literal zero values and emits the arch zero register (xzr/wzr) instead of
materializing zero in a gpr.
In AArch64.cpp:
- validat
