https://github.com/Naghasan approved this pull request.
LGTM, thanks for all the changes :)
https://github.com/llvm/llvm-project/pull/148567
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@@ -1,17 +1,109 @@
; RUN: llc -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s
--check-prefix=CHECK-SPIRV
; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv32-unknown-unknown %s -o -
-filetype=obj | spirv-val %}
-; CHECK-SPIRV-DAG: OpDecorate %[[#Id:]] BuiltIn Globa
https://github.com/Naghasan commented:
> I've changed names in
> https://github.com/llvm/llvm-project/blob/main/clang/lib/Headers/__clang_spirv_builtins.h#L54
> in commit
> https://github.com/llvm/llvm-project/commit/a55fd379cac2d5b007d722eefe92b85f9c0bcb12
Make sense, thanks for updating the
https://github.com/Naghasan edited
https://github.com/llvm/llvm-project/pull/148567
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https://github.com/Naghasan closed
https://github.com/llvm/llvm-project/pull/143909
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https://github.com/Naghasan updated
https://github.com/llvm/llvm-project/pull/143909
>From 5603f904e4e644a4b86ab3beb8b6b48cf0fee317 Mon Sep 17 00:00:00 2001
From: Victor Lomuller
Date: Thu, 5 Jun 2025 16:17:10 +0100
Subject: [PATCH] [SPIRV] Add more id and range builtIns
The patch adds intrins
https://github.com/Naghasan updated
https://github.com/llvm/llvm-project/pull/143909
>From b2e45fdf15b28187463b5afda89bbe26c5083d80 Mon Sep 17 00:00:00 2001
From: Victor Lomuller
Date: Thu, 5 Jun 2025 16:17:10 +0100
Subject: [PATCH] [SPIRV] Add more id and range builtIns
The patch adds intrins
@@ -93,16 +73,6 @@
__SPIRV_BUILTIN_ALIAS(__builtin_spirv_generic_cast_to_ptr_explicit)
__private const void *
__spirv_GenericCastToPtrExplicit_ToPrivate(__generic const void *,
int) __SPIRV_NOEXCEPT;
-extern __SPIRV_overloadable
-__SP
@@ -115,16 +85,6 @@ __spirv_GenericCastToPtr_ToGlobal(__generic const void *p,
int) __SPIRV_NOEXCEPT {
return (__global const void *)p;
}
-static __SPIRV_overloadable __SPIRV_inline __global volatile void *
Naghasan wrote:
y
Naghasan wrote:
> makes it easier to support non clang based frontends. Say we wanted to do
> something MLIR based.
Yes, that reminds me of the D compiler struggling to use the translator a few
yers back.
@Keenuts so are you fine moving ahead as it is ? as @farzonl mentioned, it also
has val
@@ -93,16 +73,6 @@
__SPIRV_BUILTIN_ALIAS(__builtin_spirv_generic_cast_to_ptr_explicit)
__private const void *
__spirv_GenericCastToPtrExplicit_ToPrivate(__generic const void *,
int) __SPIRV_NOEXCEPT;
-extern __SPIRV_overloadable
-__SP
@@ -115,16 +85,6 @@ __spirv_GenericCastToPtr_ToGlobal(__generic const void *p,
int) __SPIRV_NOEXCEPT {
return (__global const void *)p;
}
-static __SPIRV_overloadable __SPIRV_inline __global volatile void *
Naghasan wrote:
W
Naghasan wrote:
> all built-ins are represented using global variables in a specific AS with
> the associated metadata to generate the decoration.
For the HLSL FE, there are already a few ids represented using intrinsics
(unfortunately they use the DXIL naming rather than the SPIR-V but that's
Naghasan wrote:
Thanks for the background, that helps.
> That said, I'm not completely against having 2 ways to do the same thing in
> the backend if that's really a requirement on your end. Some FE could use
> intrinsics, other the global approach.
Well all could switch to intrinics or none
https://github.com/Naghasan ready_for_review
https://github.com/llvm/llvm-project/pull/143909
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https://github.com/Naghasan updated
https://github.com/llvm/llvm-project/pull/143909
>From 049087b07503add00192211b8ee96bdfebcfeed3 Mon Sep 17 00:00:00 2001
From: Victor Lomuller
Date: Thu, 5 Jun 2025 16:17:10 +0100
Subject: [PATCH] [SPIRV] Add more id and range builtIns
The patch adds intrins
https://github.com/Naghasan converted_to_draft
https://github.com/llvm/llvm-project/pull/143909
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Naghasan wrote:
The advantage of intrinsics is they can be understood better by passes, it also
creates an easier way for passes to introduce them (and less error prone). It's
kinda pedantic TBH and I don't have strong opinions about them (it just feels
cleaner to me). For the frontend side, t
https://github.com/Naghasan created
https://github.com/llvm/llvm-project/pull/143909
The patch adds intrinsics and lowering logic for GlobalSize, GlobalOffset,
SubgroupMaxSize, NumWorkgroups, WorkgroupSize, WorkgroupId, LocalInvocationId,
GlobalInvocationId, SubgroupSize, NumSubgroups, Subgrou
Naghasan wrote:
@farzonl @VyacheslavLevytskyy
https://github.com/llvm/llvm-project/pull/141954
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https://github.com/Naghasan edited
https://github.com/llvm/llvm-project/pull/141954
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https://github.com/Naghasan edited
https://github.com/llvm/llvm-project/pull/141954
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Naghasan wrote:
Just opened a PR for this https://github.com/llvm/llvm-project/pull/141954
https://github.com/llvm/llvm-project/pull/137805
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https://github.com/Naghasan created
https://github.com/llvm/llvm-project/pull/141954
Remove unneeded default label which triggers a warning with
-Wcovered-switch-default
>From 5b5bbe5792043881e03db19e9e888bd797052b8e Mon Sep 17 00:00:00 2001
From: Victor Lomuller
Date: Thu, 29 May 2025 15:10:
@@ -33,8 +46,114 @@ static bool CheckAllArgsHaveSameType(Sema *S, CallExpr
*TheCall) {
return false;
}
-bool SemaSPIRV::CheckSPIRVBuiltinFunctionCall(unsigned BuiltinID,
+static std::optional
+processConstant32BitIntArgument(Sema &SemaRef, CallExpr *Call, int Argument) {
+
@@ -97,10 +97,10 @@ static Value *EmitTargetArchBuiltinExpr(CodeGenFunction
*CGF,
case llvm::Triple::riscv64:
return CGF->EmitRISCVBuiltinExpr(BuiltinID, E, ReturnValue);
case llvm::Triple::spirv:
Naghasan wrote:
nope, I fixed it
https://github.com/l
https://github.com/Naghasan updated
https://github.com/llvm/llvm-project/pull/137805
>From 020a804188b13ef881dcf1cbd81a5e11e4803d62 Mon Sep 17 00:00:00 2001
From: Victor Lomuller
Date: Mon, 28 Apr 2025 16:20:09 +0100
Subject: [PATCH 1/2] [clang][SPIRV] Add builtin for OpGenericCastToPtrExplicit
@@ -35,8 +35,10 @@ static constexpr Builtin::Info BuiltinInfos[] = {
static_assert(std::size(BuiltinInfos) == NumBuiltins);
llvm::SmallVector
-SPIRVTargetInfo::getTargetBuiltins() const {
- return {{&BuiltinStrings, BuiltinInfos}};
+BaseSPIRTargetInfo::getTargetBuiltins() con
https://github.com/Naghasan edited
https://github.com/llvm/llvm-project/pull/137805
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https://github.com/Naghasan updated
https://github.com/llvm/llvm-project/pull/137805
>From 020a804188b13ef881dcf1cbd81a5e11e4803d62 Mon Sep 17 00:00:00 2001
From: Victor Lomuller
Date: Mon, 28 Apr 2025 16:20:09 +0100
Subject: [PATCH 1/2] [clang][SPIRV] Add builtin for OpGenericCastToPtrExplicit
@@ -35,8 +35,10 @@ static constexpr Builtin::Info BuiltinInfos[] = {
static_assert(std::size(BuiltinInfos) == NumBuiltins);
llvm::SmallVector
-SPIRVTargetInfo::getTargetBuiltins() const {
- return {{&BuiltinStrings, BuiltinInfos}};
+BaseSPIRTargetInfo::getTargetBuiltins() con
@@ -5837,12 +5838,13 @@ static void handleBuiltinAliasAttr(Sema &S, Decl *D,
const ParsedAttr &AL) {
bool IsAArch64 = S.Context.getTargetInfo().getTriple().isAArch64();
bool IsARM = S.Context.getTargetInfo().getTriple().isARM();
bool IsRISCV = S.Context.getTargetInfo().g
@@ -35,8 +35,10 @@ static constexpr Builtin::Info BuiltinInfos[] = {
static_assert(std::size(BuiltinInfos) == NumBuiltins);
llvm::SmallVector
-SPIRVTargetInfo::getTargetBuiltins() const {
- return {{&BuiltinStrings, BuiltinInfos}};
+BaseSPIRTargetInfo::getTargetBuiltins() con
@@ -35,8 +35,10 @@ static constexpr Builtin::Info BuiltinInfos[] = {
static_assert(std::size(BuiltinInfos) == NumBuiltins);
llvm::SmallVector
-SPIRVTargetInfo::getTargetBuiltins() const {
- return {{&BuiltinStrings, BuiltinInfos}};
+BaseSPIRTargetInfo::getTargetBuiltins() con
https://github.com/Naghasan updated
https://github.com/llvm/llvm-project/pull/137805
>From 020a804188b13ef881dcf1cbd81a5e11e4803d62 Mon Sep 17 00:00:00 2001
From: Victor Lomuller
Date: Mon, 28 Apr 2025 16:20:09 +0100
Subject: [PATCH] [clang][SPIRV] Add builtin for OpGenericCastToPtrExplicit and
https://github.com/Naghasan updated
https://github.com/llvm/llvm-project/pull/137805
>From 90725e8f74295bfd9169e03e73af54c2cf4616ea Mon Sep 17 00:00:00 2001
From: Victor Lomuller
Date: Mon, 28 Apr 2025 16:20:09 +0100
Subject: [PATCH] [clang][SPIRV] Add builtin for OpGenericCastToPtrExplicit and
Naghasan wrote:
Sorry I can't assign reviewers, @JonChesterfield @jhuber6 as you are involved
in gpuintrin.h, I'd welcome feedbacks here (feel free to ping other relevant
persons)
For the SPIR-V side of thing @VyacheslavLevytskyy @farzonl I appreciate your
feedbacks as well :)
FYI @tahoner
https://github.com/Naghasan created
https://github.com/llvm/llvm-project/pull/137805
The patch introduce __builtin_spirv_generic_cast_to_ptr_explicit which is
lowered to the llvm.spv.generic.cast.to.ptr.explicit intrinsic.
The patch also introduces a new header defining its SPIR-V friendly equ
@@ -0,0 +1,131 @@
+//===--- SYCL.h -*- C++
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Ap
@@ -0,0 +1,131 @@
+//===--- SYCL.h -*- C++
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Ap
@@ -91,6 +97,88 @@ SPIRVTargetMachine::SPIRVTargetMachine(const Target &T,
const Triple &TT,
setRequiresStructuredCFG(false);
}
+enum AddressSpace {
+ Function = storageClassToAddressSpace(SPIRV::StorageClass::Function),
+ CrossWorkgroup =
+ storageClassToAddressSpac
@@ -91,6 +97,88 @@ SPIRVTargetMachine::SPIRVTargetMachine(const Target &T,
const Triple &TT,
setRequiresStructuredCFG(false);
}
+enum AddressSpace {
+ Function = storageClassToAddressSpace(SPIRV::StorageClass::Function),
+ CrossWorkgroup =
+ storageClassToAddressSpac
@@ -91,6 +97,88 @@ SPIRVTargetMachine::SPIRVTargetMachine(const Target &T,
const Triple &TT,
setRequiresStructuredCFG(false);
}
+enum AddressSpace {
+ Function = storageClassToAddressSpace(SPIRV::StorageClass::Function),
+ CrossWorkgroup =
+ storageClassToAddressSpac
@@ -91,6 +97,88 @@ SPIRVTargetMachine::SPIRVTargetMachine(const Target &T,
const Triple &TT,
setRequiresStructuredCFG(false);
}
+enum AddressSpace {
+ Function = storageClassToAddressSpace(SPIRV::StorageClass::Function),
+ CrossWorkgroup =
+ storageClassToAddressSpac
@@ -92,6 +98,63 @@ SPIRVTargetMachine::SPIRVTargetMachine(const Target &T,
const Triple &TT,
setRequiresStructuredCFG(false);
}
+enum AddressSpace {
+ Function = storageClassToAddressSpace(SPIRV::StorageClass::Function),
+ CrossWorkgroup =
+ storageClassToAddressSpac
@@ -92,6 +98,63 @@ SPIRVTargetMachine::SPIRVTargetMachine(const Target &T,
const Triple &TT,
setRequiresStructuredCFG(false);
}
+enum AddressSpace {
+ Function = storageClassToAddressSpace(SPIRV::StorageClass::Function),
+ CrossWorkgroup =
+ storageClassToAddressSpac
@@ -91,6 +97,88 @@ SPIRVTargetMachine::SPIRVTargetMachine(const Target &T,
const Triple &TT,
setRequiresStructuredCFG(false);
}
+enum AddressSpace {
+ Function = storageClassToAddressSpace(SPIRV::StorageClass::Function),
+ CrossWorkgroup =
+ storageClassToAddressSpac
Naghasan wrote:
ping
https://github.com/llvm/llvm-project/pull/94934
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Naghasan wrote:
Still I forgot to answer this point as well...
> Are there ever point releases that might mea +ptx78 should actually expand to
> 780 rather than 78?
not sure what you exactly mean with your question. I guess we can mirror the
cuda arch macro so, major * 100 + minor * 10, no op
https://github.com/Naghasan edited
https://github.com/llvm/llvm-project/pull/94934
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Naghasan wrote:
Thanks for setting the reviewer
> Can you please include rationale for why this this name e.g. why not
> __NVPTX_VERSION__?
`NVPTX` is the name of the LLVM backend, `PTX` is the name of assembly which
have a version hence `__PTX_VERSION__`. Happy to use a better name, but it i
Naghasan wrote:
@Artem-B could you have a look ? I think you are the most relevant for this,
thanks. (Sorry I can't manage assignment)
https://github.com/llvm/llvm-project/pull/94934
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https://github.com/Naghasan created
https://github.com/llvm/llvm-project/pull/94934
Define __PTX_VERSION__ macro to indicate the used PTX version.
Usually each new PTX version brings a new sm version and the associated
instructions. However, some of these instructions can also be made avialabl
@@ -418,8 +418,10 @@ class LLVM_LIBRARY_VISIBILITY AMDGPUTargetInfo final :
public TargetInfo {
// value ~0.
uint64_t getNullPointerValue(LangAS AS) const override {
// FIXME: Also should handle region.
-return (AS == LangAS::opencl_local || AS == LangAS::opencl_pr
@@ -285,6 +289,20 @@ void
NVPTXTargetCodeGenInfo::addNVVMMetadata(llvm::GlobalValue *GV,
bool NVPTXTargetCodeGenInfo::shouldEmitStaticExternCAliases() const {
return false;
}
+
+llvm::Constant *
+NVPTXTargetCodeGenInfo::getNullPointer(const CodeGen::CodeGenModule &CGM,
+
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