@@ -537,7 +537,11 @@ AMDGPUTargetCodeGenInfo::getLLVMSyncScopeID(const
LangOptions &LangOpts,
break;
}
- if (Ordering != llvm::AtomicOrdering::SequentiallyConsistent) {
+ // OpenCL assumes by default that atomic scopes are per-address space for
+ // non-sequentially
@@ -537,7 +537,11 @@ AMDGPUTargetCodeGenInfo::getLLVMSyncScopeID(const
LangOptions &LangOpts,
break;
}
- if (Ordering != llvm::AtomicOrdering::SequentiallyConsistent) {
+ // OpenCL assumes by default that atomic scopes are per-address space for
+ // non-sequentially
@@ -537,7 +537,11 @@ AMDGPUTargetCodeGenInfo::getLLVMSyncScopeID(const
LangOptions &LangOpts,
break;
}
- if (Ordering != llvm::AtomicOrdering::SequentiallyConsistent) {
+ // OpenCL assumes by default that atomic scopes are per-address space for
+ // non-sequentially
https://github.com/t-tye edited https://github.com/llvm/llvm-project/pull/120095
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@@ -537,7 +537,11 @@ AMDGPUTargetCodeGenInfo::getLLVMSyncScopeID(const
LangOptions &LangOpts,
break;
}
- if (Ordering != llvm::AtomicOrdering::SequentiallyConsistent) {
+ // OpenCL assumes by default that atomic scopes are per-address space for
+ // non-sequentially
@@ -537,7 +537,11 @@ AMDGPUTargetCodeGenInfo::getLLVMSyncScopeID(const
LangOptions &LangOpts,
break;
}
- if (Ordering != llvm::AtomicOrdering::SequentiallyConsistent) {
+ // OpenCL assumes by default that atomic scopes are per-address space for
+ // non-sequentially
https://github.com/t-tye edited https://github.com/llvm/llvm-project/pull/120095
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@@ -537,7 +537,11 @@ AMDGPUTargetCodeGenInfo::getLLVMSyncScopeID(const
LangOptions &LangOpts,
break;
}
- if (Ordering != llvm::AtomicOrdering::SequentiallyConsistent) {
+ // OpenCL assumes by default that atomic scopes are per-address space for
+ // non-sequentially
t-tye wrote:
I am not clear why new functions need to be added for this, as I think there
are existing functions that already do this.
https://github.com/llvm/llvm-project/pull/79236
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https://github.com/t-tye approved this pull request.
https://github.com/llvm/llvm-project/pull/76955
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https://github.com/t-tye commented:
Documentation LGTM. Thanks.
https://github.com/llvm/llvm-project/pull/76955
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@@ -1642,80 +1746,118 @@ The AMDGPU backend uses the following ELF header:
``EF_AMDGPU_FEATURE_SRAMECC_ON_V4`` 0xc00 SRAMECC enabled.
=
===
+ .. table:: AMDGPU ELF Header ``e_
@@ -4135,6 +4283,33 @@ Code object V5 metadata is the same as
== == =
+.. _amdgpu-amdhsa-code-object-metadata-v6:
+
+Code Object V6 Metadata
+
+.. warning::
+ Code object
@@ -520,6 +520,102 @@ Every processor supports every OS ABI (see
:ref:`amdgpu-os`) with the following
=== === = =
=== === ==
+Generic processors allow execution of a single
@@ -520,6 +520,102 @@ Every processor supports every OS ABI (see
:ref:`amdgpu-os`) with the following
=== === = =
=== === ==
+Generic processors allow execution of a single
@@ -605,12 +606,197 @@ class SIGfx12CacheControl : public SIGfx11CacheControl {
bool IsNonTemporal) const override;
};
+class SIPreciseMemorySupport {
+protected:
+ const GCNSubtarget &ST;
+ const SIInstrInfo *TII = nullptr;
+
+ IsaVers
@@ -605,12 +606,197 @@ class SIGfx12CacheControl : public SIGfx11CacheControl {
bool IsNonTemporal) const override;
};
+class SIPreciseMemorySupport {
t-tye wrote:
My initial thought had been that this would be part of th
@@ -641,6 +644,9 @@ class SIMemoryLegalizer final : public MachineFunctionPass {
bool expandAtomicCmpxchgOrRmw(const SIMemOpInfo &MOI,
MachineBasicBlock::iterator &MI);
+ bool GFX9InsertWaitcntForPreciseMem(MachineFunction &MF);
-
https://github.com/t-tye edited https://github.com/llvm/llvm-project/pull/79236
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https://github.com/t-tye requested changes to this pull request.
https://github.com/llvm/llvm-project/pull/79236
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@@ -520,6 +520,106 @@ Every processor supports every OS ABI (see
:ref:`amdgpu-os`) with the following
=== === = =
=== === ==
+Generic processors also exist. They group mult
@@ -520,6 +520,106 @@ Every processor supports every OS ABI (see
:ref:`amdgpu-os`) with the following
=== === = =
=== === ==
+Generic processors also exist. They group mult
https://github.com/t-tye requested changes to this pull request.
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@@ -520,6 +520,106 @@ Every processor supports every OS ABI (see
:ref:`amdgpu-os`) with the following
=== === = =
=== === ==
+Generic processors also exist. They group mult
@@ -520,6 +520,106 @@ Every processor supports every OS ABI (see
:ref:`amdgpu-os`) with the following
=== === = =
=== === ==
+Generic processors also exist. They group mult
@@ -4135,6 +4283,33 @@ Code object V5 metadata is the same as
== == =
+.. _amdgpu-amdhsa-code-object-metadata-v6:
+
+Code Object V6 Metadata
+
+.. warning::
+ Code object
@@ -520,6 +520,106 @@ Every processor supports every OS ABI (see
:ref:`amdgpu-os`) with the following
=== === = =
=== === ==
+Generic processors also exist. They group mult
@@ -1633,80 +1741,120 @@ The AMDGPU backend uses the following ELF header:
``EF_AMDGPU_FEATURE_SRAMECC_ON_V4`` 0xc00 SRAMECC enabled.
=
===
+ .. table:: AMDGPU ELF Header ``e_
@@ -1633,80 +1741,120 @@ The AMDGPU backend uses the following ELF header:
``EF_AMDGPU_FEATURE_SRAMECC_ON_V4`` 0xc00 SRAMECC enabled.
=
===
+ .. table:: AMDGPU ELF Header ``e_
@@ -520,6 +520,106 @@ Every processor supports every OS ABI (see
:ref:`amdgpu-os`) with the following
=== === = =
=== === ==
+Generic processors also exist. They group mult
https://github.com/t-tye edited https://github.com/llvm/llvm-project/pull/76955
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Author: t-tye
Date: Fri Mar 23 11:51:45 2018
New Revision: 328350
URL: http://llvm.org/viewvc/llvm-project?rev=328350&view=rev
Log:
[AMDGPU] Update OpenCL to use 48 bytes of implicit arguments for AMDGPU (CLANG)
Add two additional implicit arguments for OpenCL for the AMDGPU target using
the AMD
Author: t-tye
Date: Fri Mar 23 11:43:15 2018
New Revision: 328347
URL: http://llvm.org/viewvc/llvm-project?rev=328347&view=rev
Log:
[AMDGPU] Remove use of OpenCL triple environment and replace with function
attribute for AMDGPU (CLANG)
- Remove use of the opencl and amdopencl environment member
tony-tye added inline comments.
Comment at: lib/CodeGen/CodeGenTypes.cpp:743
+auto NullPtr = CGM.getNullPtr(LLPT, T);
+return isa(NullPtr);
+ }
Is this correct if the target does not represent a NULL pointer as the address
with value 0? Or should this b
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