[clang] [llvm] RFC: Implementing new mechanism for hard register operands to inline asm as a constraint. (PR #85846)

2025-12-12 Thread Tony Tao via cfe-commits
tltao wrote: Hmm looks like the testing reveals another problem. We have no way of invalidating a platform specific constraint that also uses `{}`. The AMDGCN tests expect `{exec}a` to fail to verify, but it does not fail in the generic `validateHardRegisterAsmConstraint` since we want to supp

[clang] [llvm] RFC: Implementing new mechanism for hard register operands to inline asm as a constraint. (PR #85846)

2025-12-12 Thread Tony Tao via cfe-commits
tltao wrote: I've made the changes as discussed to support multiple hard register constraints. https://github.com/llvm/llvm-project/pull/85846 ___ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe

[clang] [llvm] RFC: Implementing new mechanism for hard register operands to inline asm as a constraint. (PR #85846)

2025-12-10 Thread Tony Tao via cfe-commits
tltao wrote: > I'm not sure I follow what you mean here; does this mean that if you have a > register asm variable, it might not end up in that register? That seems like > a regression for existing code. Ah, good point. I was thinking more in line of mismatching register classes, but you're r

[clang] [llvm] RFC: Implementing new mechanism for hard register operands to inline asm as a constraint. (PR #85846)

2025-12-10 Thread Tony Tao via cfe-commits
tltao wrote: Thanks for all the comments. I think from @stefan-sf-ibm's response, it sounds like the GCC side is not fully decided on what to do with multiple constraints involving hard registers, so we can wait for the details to be hashed out further there. In the meantime, I plan on makin

[clang] [llvm] RFC: Implementing new mechanism for hard register operands to inline asm as a constraint. (PR #85846)

2025-12-08 Thread Tony Tao via cfe-commits
tltao wrote: > If you do want to reject, please make sure we reject gracefully at both the > clang level and the LLVM IR level. Is there a reason we also need to check it in the LLVM IR level if we are already checking for it in clang? This PR only affects the Clang output so I don't know for

[clang] [llvm] RFC: Implementing new mechanism for hard register operands to inline asm as a constraint. (PR #85846)

2025-12-05 Thread Tony Tao via cfe-commits
tltao wrote: Ping. Restarting this topic as GCC have implemented the same feature. https://gcc.gnu.org/onlinedocs/gcc/Hard-Register-Constraints.html https://github.com/llvm/llvm-project/pull/85846 ___ cfe-commits mailing list [email protected]

[clang] [llvm] RFC: Implementing new mechanism for hard register operands to inline asm as a constraint. (PR #85846)

2025-12-05 Thread Tony Tao via cfe-commits
https://github.com/tltao edited https://github.com/llvm/llvm-project/pull/85846 ___ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] RFC: Implementing new mechanism for hard register operands to inline asm as a constraint. (PR #85846)

2025-12-05 Thread Tony Tao via cfe-commits
https://github.com/tltao edited https://github.com/llvm/llvm-project/pull/85846 ___ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits