@@ -1,1145 +0,0 @@
-// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
UTC_ARGS: --function-signature --check-attributes --check-globals
--include-generated-funcs --global-value-regex ".*"
-// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -emit-llvm -
https://github.com/tmatheson-arm approved this pull request.
I can't check 100% we are not missing anything important, but if you are
confident then go for it.
https://github.com/llvm/llvm-project/pull/132273
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LGTM. Does this actually fix the build time regression from the previous patch?
https://github.com/llvm/llvm-project/pull/132495
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@@ -0,0 +1,790 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
UTC_ARGS: --function-signature --check-attributes --check-globals
--include-generated-funcs --global-value-regex ".*"
+
+// Test all of the AArch64 feature detection bitmasks in the
@@ -1,1145 +0,0 @@
-// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
UTC_ARGS: --function-signature --check-attributes --check-globals
--include-generated-funcs --global-value-regex ".*"
-// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -emit-llvm -
@@ -0,0 +1,790 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
UTC_ARGS: --function-signature --check-attributes --check-globals
--include-generated-funcs --global-value-regex ".*"
+
+// Test all of the AArch64 feature detection bitmasks in the
@@ -0,0 +1,790 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
UTC_ARGS: --function-signature --check-attributes --check-globals
--include-generated-funcs --global-value-regex ".*"
+
+// Test all of the AArch64 feature detection bitmasks in the
tmatheson-arm wrote:
> There are lots of bugs like this in this area, this is not the only feature
> like this. Should this be fixed in a more general way?
We've looked at this internally but didn't get around to finishing it.
`HasD128` etc map to `Extensions` in `AArch64Features.td`, I think
https://github.com/tmatheson-arm updated
https://github.com/llvm/llvm-project/pull/126945
>From e618aba47c0e7244105bf325ab8019a085e1ed99 Mon Sep 17 00:00:00 2001
From: Tomas Matheson
Date: Wed, 12 Feb 2025 14:31:47 +
Subject: [PATCH 1/4] Add missing Neon Types
The AAPCS64 adds a number of
https://github.com/tmatheson-arm updated
https://github.com/llvm/llvm-project/pull/126945
>From e618aba47c0e7244105bf325ab8019a085e1ed99 Mon Sep 17 00:00:00 2001
From: Tomas Matheson
Date: Wed, 12 Feb 2025 14:31:47 +
Subject: [PATCH 1/3] Add missing Neon Types
The AAPCS64 adds a number of
tmatheson-arm wrote:
I think so, but I would rather do it as a separate PR. There are a couple of
other things that could do with tidying up too.
https://github.com/llvm/llvm-project/pull/126945
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The AAPCS64 adds a number of vector types to the C unconditionally:
https://github.com/ARM-software/abi-aa/blob/main/aapcs64/aapcs64.rst#11appendix-support-for-advanced-simd-extensions
The equivalent SVE
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>From 87d539860c11d7e0f021410b5947b5c25c8870d7 Mon Sep 17 00:00:00 2001
From: Tomas Matheson
Date: Thu, 30 Jan 2025 15:37:08 +
Subject: [PATCH 1/2] [NFC] remove string literals from AArch64Types.def
-
https://github.com/tmatheson-arm updated
https://github.com/llvm/llvm-project/pull/125063
>From 87d539860c11d7e0f021410b5947b5c25c8870d7 Mon Sep 17 00:00:00 2001
From: Tomas Matheson
Date: Thu, 30 Jan 2025 15:37:08 +
Subject: [PATCH] [NFC] remove string literals from AArch64Types.def
---
tmatheson-arm wrote:
I've just noticed 2/3 of these are redundant now since the existing neon
functions have been removed. I'll remove them.
https://github.com/llvm/llvm-project/pull/125063
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https://github.com/llvm/llvm-project/pull/125063
- Rename AArch64SVEACLETypes.def to AArch64Types.def
- Remove string literals from the macro calls
- Rename macros so that the hierarchy makes sense
>From 63159e8e82b56850213fb0e2479bd708f008ea81 Mon Sep
https://github.com/tmatheson-arm approved this pull request.
LGTM, assuming no objections to CPU changes.
https://github.com/llvm/llvm-project/pull/123336
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tmatheson-arm wrote:
Actually this is being added as a mandatory dependency of 9.4, should it not be
added as one of the default features instead?
https://github.com/llvm/llvm-project/pull/120753
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https://github.com/tmatheson-arm approved this pull request.
Makes sense to me.
https://github.com/llvm/llvm-project/pull/120753
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I'm surprised how complicated this was to do, but LGTM.
https://github.com/llvm/llvm-project/pull/118581
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@@ -87,9 +86,8 @@ def : FMVExtension<"sve-bf16", "FEAT_SVE_BF16",
"+sve,+bf16,+fullfp16,+fp-armv8,
def : FMVExtension<"sve-ebf16", "FEAT_SVE_EBF16",
"+sve,+bf16,+fullfp16,+fp-armv8,+neon", 330>;
def : FMVExtension<"sve-i8mm", "FEAT_SVE_I8MM",
"+sve,+i8mm,+fullfp16,+fp-armv8,+
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@@ -59,7 +59,7 @@ enum CPUFeatures {
FEAT_SVE_F32MM,
FEAT_SVE_F64MM,
FEAT_SVE2,
- FEAT_SVE_AES,
+ RESERVED_FEAT_SVE_AES, // previously used and now ABI legacy
tmatheson-arm wrote:
It would be nice to have a more complete explanation of these reserved v
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@@ -1125,31 +1125,32 @@ int caller(void) { return
used_def_without_default_decl() + used_decl_without_de
// CHECK: attributes #[[ATTR10]] = { noinline nounwind optnone
"no-trapping-math"="true" "stack-protector-buffer-size"="8"
"target-features"="+fp-armv8,+ls64,+neon" }
// C
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https://github.com/llvm/llvm-project/pull/110297
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@@ -1059,7 +1059,7 @@ bool
AArch64TargetInfo::handleTargetFeatures(std::vector &Features,
HasFullFP16 = true;
HasFP16FML = true;
}
-if (Feature == "+mte")
+if (Feature == "+mte2")
tmatheson-arm wrote:
This breaks backwards compatibilit
@@ -1059,7 +1059,7 @@ bool
AArch64TargetInfo::handleTargetFeatures(std::vector &Features,
HasFullFP16 = true;
HasFP16FML = true;
}
-if (Feature == "+mte")
+if (Feature == "+mte2")
tmatheson-arm wrote:
Won't this break existing IR with
https://github.com/tmatheson-arm approved this pull request.
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@@ -73,8 +73,6 @@ enum CPUFeatures {
FEAT_SSBS,
FEAT_SSBS2,
FEAT_BTI,
- FEAT_LS64,
- FEAT_LS64_V,
tmatheson-arm wrote:
> If object A uses bit 36, object B uses bit 35 and the runtime uses bit 34,
> how is it ever going to work?
Using them for what?
@@ -73,8 +73,6 @@ enum CPUFeatures {
FEAT_SSBS,
FEAT_SSBS2,
FEAT_BTI,
- FEAT_LS64,
- FEAT_LS64_V,
tmatheson-arm wrote:
@Wilco1 could you explain the scenario you are worried about in more detail?
What you posted above appears to be a snippet of a gene
tmatheson-arm wrote:
Are you planning to follow through with this?
https://github.com/llvm/llvm-project/pull/106304
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@@ -3682,6 +3682,8 @@ static const struct Extension {
{"sve2-bitperm", {AArch64::FeatureSVE2BitPerm}},
{"sve2p1", {AArch64::FeatureSVE2p1}},
{"ls64", {AArch64::FeatureLS64}},
+{"ls64_v", {AArch64::FeatureLS64_V}},
+{"ls64_accdata", {AArch64::FeatureLS64_ACCD
@@ -305,9 +305,17 @@ def FeatureWFxT : ExtensionWithMArch<"wfxt", "WFxT",
"FEAT_WFxT",
def FeatureHCX : Extension<"hcx", "HCX", "FEAT_HCX",
"Enable Armv8.7-A HCRX_EL2 system register">;
-def FeatureLS64 : ExtensionWithMArch<"ls64", "LS64",
- "FEAT_LS64, FEAT_LS64_V, FEAT_L
@@ -305,9 +305,17 @@ def FeatureWFxT : ExtensionWithMArch<"wfxt", "WFxT",
"FEAT_WFxT",
def FeatureHCX : Extension<"hcx", "HCX", "FEAT_HCX",
"Enable Armv8.7-A HCRX_EL2 system register">;
-def FeatureLS64 : ExtensionWithMArch<"ls64", "LS64",
- "FEAT_LS64, FEAT_LS64_V, FEAT_L
tmatheson-arm wrote:
This looks like the right direction to go.
https://github.com/llvm/llvm-project/pull/106304
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@@ -895,7 +895,10 @@ def ProcessorFeatures {
FeatureLSE, FeaturePAuth, FeatureFPAC,
FeatureRAS, FeatureRCPC, FeatureRDM,
FeatureBF16, FeatureDotProd,
FeatureMatMulInt
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tmatheson-arm wrote:
/cherry-pick 362142c4bb5cc657151f592e507f552d5b9f7dde
https://github.com/llvm/llvm-project/pull/104435
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@@ -0,0 +1,90 @@
+// Use --implicit-check-not to ensure no additional CPUs are in this list
+
+// RUN: not %clang_cc1 -triple arm64--- -target-cpu not-a-cpu -fsyntax-only %s
2>&1 | FileCheck %s --implicit-check-not={{[a-zA-Z0-9]}}
+// RUN: not %clang_cc1 -triple arm64--- -tune-cp
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@@ -0,0 +1,90 @@
+// Use --implicit-check-not to ensure no additional CPUs are in this list
+
+// RUN: not %clang_cc1 -triple arm64--- -target-cpu not-a-cpu -fsyntax-only %s
2>&1 | FileCheck %s --implicit-check-not={{[a-zA-Z0-9]}}
+// RUN: not %clang_cc1 -triple arm64--- -tune-cp
https://github.com/tmatheson-arm updated
https://github.com/llvm/llvm-project/pull/104435
>From f79eb28441491f1625691886cc92bd05d3b3cb6a Mon Sep 17 00:00:00 2001
From: Tomas Matheson
Date: Thu, 15 Aug 2024 13:41:31 +0100
Subject: [PATCH 01/18] [AArch64] Add a check for invalid default features
tmatheson-arm wrote:
@jroelofs @ahmedbougacha Are you happy with the FEAT_CCIDX changes to Apple
processors?
https://github.com/llvm/llvm-project/pull/104435
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https://github.com/tmatheson-arm approved this pull request.
Thanks. This will make downstream maintenance much easier after the initial
merge.
https://github.com/llvm/llvm-project/pull/104601
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@@ -0,0 +1,382 @@
+// Use --implicit-check-not={{[a-zA-Z0-9]}} to ensure no additional CPUs are
in these lists
+
+// RUN: not %clang_cc1 -triple i386--- -target-cpu not-a-cpu -fsyntax-only %s
2>&1 | FileCheck %s --check-prefix X86 --implicit-check-not={{[a-zA-Z0-9]}}
+// X86: er
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>From f79eb28441491f1625691886cc92bd05d3b3cb6a Mon Sep 17 00:00:00 2001
From: Tomas Matheson
Date: Thu, 15 Aug 2024 13:41:31 +0100
Subject: [PATCH 01/17] [AArch64] Add a check for invalid default features
https://github.com/tmatheson-arm updated
https://github.com/llvm/llvm-project/pull/104435
>From f79eb28441491f1625691886cc92bd05d3b3cb6a Mon Sep 17 00:00:00 2001
From: Tomas Matheson
Date: Thu, 15 Aug 2024 13:41:31 +0100
Subject: [PATCH 01/16] [AArch64] Add a check for invalid default features
@@ -283,9 +311,7 @@ static void EmitARMTargetDef(RecordKeeper &RK, raw_ostream
&OS) {
auto Profile = Arch->getValueAsString("Profile");
auto ArchInfo = ArchInfoName(Major, Minor, Profile);
-// The apple-latest alias is backend only, do not expose it to -mcpu.
-
https://github.com/tmatheson-arm updated
https://github.com/llvm/llvm-project/pull/104435
>From f79eb28441491f1625691886cc92bd05d3b3cb6a Mon Sep 17 00:00:00 2001
From: Tomas Matheson
Date: Thu, 15 Aug 2024 13:41:31 +0100
Subject: [PATCH 01/12] [AArch64] Add a check for invalid default features
tmatheson-arm wrote:
Fixed SSBS and CCIDX.
> Does this also fix the "+nossbs" issue we saw earlier this week?
Yes, added a test
https://github.com/llvm/llvm-project/pull/104435/files#diff-e355e3951d191d3a32265d9bdeb101e4f49ddfa6049ef058cf9e1dfdf7c19ef3
https://github.com/llvm/llvm-project/pul
https://github.com/tmatheson-arm updated
https://github.com/llvm/llvm-project/pull/104435
>From f79eb28441491f1625691886cc92bd05d3b3cb6a Mon Sep 17 00:00:00 2001
From: Tomas Matheson
Date: Thu, 15 Aug 2024 13:41:31 +0100
Subject: [PATCH 01/11] [AArch64] Add a check for invalid default features
https://github.com/tmatheson-arm edited
https://github.com/llvm/llvm-project/pull/104435
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>From f79eb28441491f1625691886cc92bd05d3b3cb6a Mon Sep 17 00:00:00 2001
From: Tomas Matheson
Date: Thu, 15 Aug 2024 13:41:31 +0100
Subject: [PATCH 01/10] [AArch64] Add a check for invalid default features
https://github.com/tmatheson-arm updated
https://github.com/llvm/llvm-project/pull/104435
>From f79eb28441491f1625691886cc92bd05d3b3cb6a Mon Sep 17 00:00:00 2001
From: Tomas Matheson
Date: Thu, 15 Aug 2024 13:41:31 +0100
Subject: [PATCH 1/9] [AArch64] Add a check for invalid default features
T
tmatheson-arm wrote:
> > Cortex-A710 does not appear to have SSBS
> I believe this says it should be present:
You're right, I'll fix that.
I will also actually remove FeatureCCIDX from the 8.3 mandatory features.
https://github.com/llvm/llvm-project/pull/104435
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https://github.com/llvm/llvm-project/pull/104435
This adds a check that all ExtensionWithMArch which are marked as implied
features for an architecture are also present in the list of default features.
It doesn't make sense to have something mandatory b
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https://github.com/llvm/llvm-project/pull/101192
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@@ -161,14 +161,10 @@ struct CpuInfo {
StringRef Name; // Name, as written for -mcpu.
const ArchInfo &Arch;
AArch64::ExtensionBitset
- DefaultExtensions; // Default extensions for this CPU. These will be
- // ORd with the architecture defaults
tmatheson-arm wrote:
> Seems like there are still many more inconsistencies that could be improved
> too.
To be clear, I'm not suggesting you need to do them in this PR.
https://github.com/llvm/llvm-project/pull/98550
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@@ -472,22 +472,22 @@ def FeatureFP8 : ExtensionWithMArch<"fp8", "FP8",
"FEAT_FP8",
"Enable FP8 instructions", [FeatureFAMINMAX, FeatureLUT, FeatureBF16]>;
def FeatureFP8FMA : ExtensionWithMArch<"fp8fma", "FP8FMA", "FEAT_FP8FMA",
- "Enable fp8 multiply-add instructions",
@@ -106,24 +106,24 @@ def FeatureSpecRestrict : Extension<"specrestrict",
"SpecRestrict", "FEAT_CSV2_2
//===--===//
def FeatureLSE : ExtensionWithMArch<"lse", "LSE", "FEAT_LSE",
- "Enable ARMv8.1 Large Syst
@@ -89,14 +89,14 @@ def FeatureCrypto : ExtensionWithMArch<"crypto", "Crypto",
"FEAT_Crypto",
"Enable cryptographic instructions", [FeatureNEON, FeatureSHA2, FeatureAES]>;
def FeatureCRC : ExtensionWithMArch<"crc", "CRC", "FEAT_CRC32",
- "Enable ARMv8 CRC-32 checksum instr
@@ -210,29 +210,29 @@ def FeatureDotProd : ExtensionWithMArch<"dotprod",
"DotProd", "FEAT_DotProd",
"Enable dot product support", [FeatureNEON]>;
def FeatureMPAM : Extension<"mpam", "MPAM", "FEAT_MPAM",
- "Enable v8.4-A Memory system Partitioning and Monitoring extension">
@@ -65,7 +65,7 @@ class ExtensionWithMArch<
let ArchExtKindSpelling = "AEK_FP", UserVisibleName = "fp" in
def FeatureFPARMv8 : ExtensionWithMArch<"fp-armv8", "FPARMv8", "FEAT_FP",
- "Enable ARMv8">;
+ "Enable Armv8.0-A Floating Point Extensions">;
tmatheson-
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LGTM. Seems like there are still many more inconsistencies that could be
improved too.
https://github.com/llvm/llvm-project/pull/98550
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@@ -1626,7 +1628,7 @@ INSTANTIATE_TEST_SUITE_P(
AArch64::AEK_FP16FML, AArch64::AEK_SHA3,AArch64::AEK_BF16,
AArch64::AEK_I8MM,AArch64::AEK_JSCVT, AArch64::AEK_FCMA,
AArch64::AEK_PAUTH, AArch64::AEK_PERFMON, AArch64::AEK_HCX}),
-
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LGTM. I haven't checked all the CPU feature changes, but the tests give a lot
of confidence. I also haven't checked all the TRMs but the changes there make
sense given the MEC/RME architecture changes.
https://github.com/llvm/llvm-pr
@@ -161,14 +161,10 @@ struct CpuInfo {
StringRef Name; // Name, as written for -mcpu.
const ArchInfo &Arch;
AArch64::ExtensionBitset
- DefaultExtensions; // Default extensions for this CPU. These will be
- // ORd with the architecture defaults
https://github.com/tmatheson-arm edited
https://github.com/llvm/llvm-project/pull/98267
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@@ -1434,7 +1434,14 @@ class TargetInfo : public TransferrableTargetInfo,
}
public:
-BranchProtectionInfo() = default;
+BranchProtectionInfo() {
+ SignReturnAddr = LangOptions::SignReturnAddressScopeKind::None;
+ SignKey = LangOptions::SignReturnAddress
@@ -141,7 +141,7 @@ class ARMTargetCodeGenInfo : public TargetCodeGenInfo {
ParsedTargetAttr Attr =
CGM.getTarget().parseTargetAttr(TA->getFeaturesStr());
if (!Attr.BranchProtection.empty()) {
-TargetInfo::BranchProtectionInfo BPI;
+TargetI
tmatheson-arm wrote:
Whatever the solution is, it would be better off done now, as "in future" is
likely to get forgotten.
https://github.com/llvm/llvm-project/pull/98307
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tmatheson-arm wrote:
Can something be done to prevent this happening accidentally again?
https://github.com/llvm/llvm-project/pull/98307
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@@ -11,7 +11,7 @@ int __attribute__((target_version("fp+aes"))) fmv(void) {
return 6; }
int __attribute__((target_version("crc+ls64_v"))) fmv(void) { return 7; }
int __attribute__((target_version("bti"))) fmv(void) { return 8; }
int __attribute__((target_version("sme2"))) fmv(
@@ -59,15 +59,22 @@ int bar() {
return m.goo(1) + foo(1) + foo();
}
+// Example to demonstrate that at the point of use we haven't yet seen the
default.
+// At that point a declaration for the unmangled symbol is emitted, which is
later
+// replaced by the ifunc symbol (on
@@ -4224,10 +4204,8 @@ void CodeGenModule::emitMultiVersionFunctions() {
llvm::Function *Func = createFunction(CurFD);
Options.emplace_back(Func, TA->getArchitecture(), Feats);
} else if (const auto *TVA = CurFD->getAttr()) {
-bool
@@ -59,15 +59,22 @@ int bar() {
return m.goo(1) + foo(1) + foo();
}
+// Example to demonstrate that at the point of use we haven't yet seen the
default.
+// At that point a declaration for the unmangled symbol is emitted, which is
later
+// replaced by the ifunc symbol (on
https://github.com/tmatheson-arm edited
https://github.com/llvm/llvm-project/pull/97761
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@@ -4210,9 +4192,7 @@ void CodeGenModule::emitMultiVersionFunctions() {
return cast(Func);
};
-bool HasDefaultDecl = !FD->isTargetVersionMultiVersion();
-bool ShouldEmitResolver =
-!getContext().getTargetInfo().getTriple().isAArch64();
+bool Shoul
https://github.com/tmatheson-arm commented:
It's really hard to tell what is changing here because the existing tests are
so non-specific.
https://github.com/llvm/llvm-project/pull/97761
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@@ -261,9 +261,9 @@ __attribute__((target_version("jscvt"))) int
default_def_with_version_decls(void
// CHECK: attributes #[[ATTR3]] = { noinline nounwind optnone
"no-trapping-math"="true" "stack-protector-buffer-size"="8"
"target-features"="+lse,-v9.5a" }
// CHECK: attribute
@@ -0,0 +1,24 @@
+// REQUIRES: aarch64-registered-target
tmatheson-arm wrote:
I've kept them as-is so that they still correspond to the [generating
script](https://gist.github.com/tmatheson-arm/333dd14cc1c95ab4ac563ed615add95d).
https://github.com/llvm/llvm-pro
https://github.com/tmatheson-arm closed
https://github.com/llvm/llvm-project/pull/97829
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tmatheson-arm wrote:
> Mind sticking it in a gist at least so folks can use it for downstream
> subtargets?
[Here you
go](https://gist.github.com/tmatheson-arm/333dd14cc1c95ab4ac563ed615add95d)
https://github.com/llvm/llvm-project/pull/97829
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https://github.com/tmatheson-arm approved this pull request.
LGTM, just based on what I can see from implementation of the existing bits in
the version field.
https://github.com/llvm/llvm-project/pull/96159
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