https://github.com/rampitec approved this pull request.
LGTM modulo the crash fix.
https://github.com/llvm/llvm-project/pull/147425
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@@ -2,169 +2,69 @@
# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1250 -mattr=+real-true16 -disassemble
-show-encoding < %s | FileCheck -check-prefixes=GFX1250,GFX1250-REAL16 %s
# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1250 -mattr=-real-true16 -disassemble
-show-encoding < %s | FileChec
@@ -131,21 +197,3 @@
0x02,0xeb,0x02,0x7e
# GFX1250-REAL16: v_cvt_pk_f16_fp8 v1, v2.l ; encoding:
[0x02,0xeb,0x02,0x7e]
# GFX1250-FAKE16: v_cvt_pk_f16_fp8 v1, v2 ; encoding:
[0x02,0xeb,0x02,0x7e]
-
-0x03,0xda,0x02,0x7e
rampitec wr
https://github.com/rampitec closed
https://github.com/llvm/llvm-project/pull/145152
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@@ -9669,6 +9670,9 @@ int SIInstrInfo::pseudoToMCOpcode(int Opcode) const {
int MCOp = AMDGPU::getMCOpcode(Opcode, Gen);
+ if (MCOp == (uint16_t)-1 && ST.hasGFX1250Insts())
rampitec wrote:
This is also a common pattern in this function, we do it all the t
https://github.com/rampitec edited
https://github.com/llvm/llvm-project/pull/145152
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@@ -0,0 +1,34 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -march=amdgcn -mcpu=gfx1250 -show-mc-encoding -verify-machineinstrs
< %s | FileCheck -check-prefix=GFX1250 %s
rampitec wrote:
Done
https://github.com/llv
@@ -636,5 +636,11 @@ TARGET_BUILTIN(__builtin_amdgcn_bitop3_b16, "IUi",
"nc", "bitop3-insts")
TARGET_BUILTIN(__builtin_amdgcn_cvt_sr_bf16_f32, "V2yV2yfUiIb", "nc",
"f32-to-f16bf16-cvt-sr-insts")
TARGET_BUILTIN(__builtin_amdgcn_cvt_sr_f16_f32, "V2hV2hfUiIb", "nc",
"f32-to-
https://github.com/rampitec updated
https://github.com/llvm/llvm-project/pull/145152
>From d8bfe8fad4f1ca7436dd8697b24cdfdb91be7a48 Mon Sep 17 00:00:00 2001
From: Stanislav Mekhanoshin
Date: Fri, 20 Jun 2025 12:24:47 -0700
Subject: [PATCH] [AMDGPU] Add s_setprio_inc_wg gfx1250 instruction
---
https://github.com/rampitec closed
https://github.com/llvm/llvm-project/pull/144965
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rampitec wrote:
* **#144965** https://app.graphite.dev/github/pr/llvm/llvm-project/144965?utm_source=stack-comment-icon";
target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite"
width="10px" height="10px"/> 👈 https://app.graphite.dev/github/pr/llvm/llvm-project/144
https://github.com/rampitec created
https://github.com/llvm/llvm-project/pull/144965
This is just a stub for now.
>From a176e3547079ded67ce4b3ed91ca9de6751a920b Mon Sep 17 00:00:00 2001
From: Stanislav Mekhanoshin
Date: Thu, 19 Jun 2025 15:57:29 -0700
Subject: [PATCH] [AMDGPU] Initial support
https://github.com/rampitec closed
https://github.com/llvm/llvm-project/pull/138743
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https://github.com/llvm/llvm-project/pull/138753
None
>From 7aad45e6bb65f6378abb4f76052dab283a9b3f93 Mon Sep 17 00:00:00 2001
From: Stanislav Mekhanoshin
Date: Tue, 6 May 2025 13:10:15 -0700
Subject: [PATCH] [AMDGPU] Remove unused argument in builtins-amdgcn
https://github.com/rampitec ready_for_review
https://github.com/llvm/llvm-project/pull/138753
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rampitec wrote:
* **#138753** https://app.graphite.dev/github/pr/llvm/llvm-project/138753?utm_source=stack-comment-icon";
target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite"
width="10px" height="10px"/> 👈 https://app.graphite.dev/github/pr/llvm/llvm-project/138
https://github.com/rampitec closed
https://github.com/llvm/llvm-project/pull/138745
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rampitec wrote:
Closing in favor of downstream change.
https://github.com/llvm/llvm-project/pull/138745
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rampitec wrote:
> > > Why? This just adds more intermediate IR and makes the output bigger. If
> > > anything we should switch any tests unnecessarily using CL2.0 to use CL1.2
> >
> >
> > It is like that everywhere, and that eliminates huge delta to downstream
> > branch.
>
> Fix the downstr
rampitec wrote:
* **#138743** https://app.graphite.dev/github/pr/llvm/llvm-project/138743?utm_source=stack-comment-icon";
target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite"
width="10px" height="10px"/> 👈 https://app.graphite.dev/github/pr/llvm/llvm-project/138
https://github.com/rampitec ready_for_review
https://github.com/llvm/llvm-project/pull/138743
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>From 5320eff1d30772339622d5dfbde3ae29567e89eb Mon Sep 17 00:00:00 2001
From: Stanislav Mekhanoshin
Date: Tue, 6 May 2025 12:16:24 -0700
Subject: [PATCH] [AMDGPU] Fix gfx1201 check line in the amdgpu-feat
https://github.com/rampitec approved this pull request.
LGTM
https://github.com/llvm/llvm-project/pull/129101
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https://github.com/rampitec closed
https://github.com/llvm/llvm-project/pull/122169
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https://github.com/rampitec updated
https://github.com/llvm/llvm-project/pull/122169
>From cf1e4319bc0b9799d1e20b87a3aadd7cb038b736 Mon Sep 17 00:00:00 2001
From: Stanislav Mekhanoshin
Date: Wed, 8 Jan 2025 12:49:18 -0800
Subject: [PATCH] Drop emitQuaternaryBuiltin from clang
It was superceede
https://github.com/rampitec ready_for_review
https://github.com/llvm/llvm-project/pull/122169
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rampitec wrote:
* **#122169** https://app.graphite.dev/github/pr/llvm/llvm-project/122169?utm_source=stack-comment-icon";
target="_blank">https://static.graphite.dev/graphite-32x32-black.png"; alt="Graphite"
width="10px" height="10px"/> 👈 https://app.graphite.dev/github/pr/llvm/llvm-project/122
https://github.com/rampitec created
https://github.com/llvm/llvm-project/pull/122169
It was superceeded by the emitBuiltinWithOneOverloadedType() some
time ago.
>From 2b14fb00e32db739ab8f3962fe5ad77e1df3ffda Mon Sep 17 00:00:00 2001
From: Stanislav Mekhanoshin
Date: Wed, 8 Jan 2025 12:49:18 -0
@@ -1,6 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
UTC_ARGS: --version 5
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -o - %s | FileCheck
-check-prefixes=GFX9 %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx942 -o - %s | File
@@ -1,5 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
UTC_ARGS: --version 2
# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx942
-start-before=machine-scheduler -verify-misched -o - %s | FileCheck
-check-prefix=GCN %s
+# RUN: llc -mtriple
https://github.com/rampitec approved this pull request.
It's the same code already reviewed downstream. LGTM.
https://github.com/llvm/llvm-project/pull/114550
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@@ -1024,6 +1024,16 @@ GCNTTIImpl::instCombineIntrinsic(InstCombiner &IC,
IntrinsicInst &II) const {
}
break;
}
+ case Intrinsic::amdgcn_wavefrontsize: {
+// TODO: this is a workaround for the pseudo-generic target one gets with
no
+// specified mcpu, which
https://github.com/rampitec commented:
In general LTGM.
https://github.com/llvm/llvm-project/pull/114481
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@@ -1024,6 +1024,16 @@ GCNTTIImpl::instCombineIntrinsic(InstCombiner &IC,
IntrinsicInst &II) const {
}
break;
}
+ case Intrinsic::amdgcn_wavefrontsize: {
+// TODO: this is a workaround for the pseudo-generic target one gets with
no
+// specified mcpu, which
@@ -1024,6 +1024,15 @@ GCNTTIImpl::instCombineIntrinsic(InstCombiner &IC,
IntrinsicInst &II) const {
}
break;
}
+ case Intrinsic::amdgcn_wavefrontsize: {
+// TODO: this is a workaround for the pseudo-generic target one gets with
no
+// specified mcpu, which
https://github.com/rampitec edited
https://github.com/llvm/llvm-project/pull/114481
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@@ -1024,6 +1024,15 @@ GCNTTIImpl::instCombineIntrinsic(InstCombiner &IC,
IntrinsicInst &II) const {
}
break;
}
+ case Intrinsic::amdgcn_wavefrontsize: {
+// TODO: this is a workaround for the pseudo-generic target one gets with
no
+// specified mcpu, which
@@ -345,6 +345,15 @@ extern char &AMDGPUPrintfRuntimeBindingID;
void initializeAMDGPUResourceUsageAnalysisPass(PassRegistry &);
extern char &AMDGPUResourceUsageAnalysisID;
+struct AMDGPUExpandPseudoIntrinsicsPass
rampitec wrote:
The pass isn't needed now?
ht
rampitec wrote:
This is really just a constant folding rather than a new pass. If the concern
is that InstCombine works too late that is possible to add an earlier
invocation.
https://github.com/llvm/llvm-project/pull/114481
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https://github.com/rampitec closed
https://github.com/llvm/llvm-project/pull/113610
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https://github.com/rampitec updated
https://github.com/llvm/llvm-project/pull/113610
>From edda0e600abeabff4d44e8b0b897104efacc8f98 Mon Sep 17 00:00:00 2001
From: Stanislav Mekhanoshin
Date: Thu, 24 Oct 2024 11:31:52 -0700
Subject: [PATCH 1/2] [AMDGPU] Allow overload of __builtin_amdgcn_mov_dpp
rampitec wrote:
It does not really work w/o https://github.com/llvm/llvm-project/pull/113500
though.
https://github.com/llvm/llvm-project/pull/113610
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https://github.com/rampitec updated
https://github.com/llvm/llvm-project/pull/113610
>From edda0e600abeabff4d44e8b0b897104efacc8f98 Mon Sep 17 00:00:00 2001
From: Stanislav Mekhanoshin
Date: Thu, 24 Oct 2024 11:31:52 -0700
Subject: [PATCH 1/2] [AMDGPU] Allow overload of __builtin_amdgcn_mov_dpp
@@ -152,6 +115,44 @@ bool SemaAMDGPU::CheckAMDGCNBuiltinFunctionCall(unsigned
BuiltinID,
return false;
}
+bool SemaAMDGPU::CheckMovDPPFunctionCall(CallExpr *TheCall, unsigned NumArgs,
rampitec wrote:
Done
https://github.com/llvm/llvm-project/pull/113610
_
https://github.com/rampitec created
https://github.com/llvm/llvm-project/pull/113610
The same handling as for __builtin_amdgcn_mov_dpp.
>From edda0e600abeabff4d44e8b0b897104efacc8f98 Mon Sep 17 00:00:00 2001
From: Stanislav Mekhanoshin
Date: Thu, 24 Oct 2024 11:31:52 -0700
Subject: [PATCH] [AM
https://github.com/rampitec closed
https://github.com/llvm/llvm-project/pull/113341
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https://github.com/rampitec created
https://github.com/llvm/llvm-project/pull/113341
Recent change applied too strict check for old and src operands match. These
shall be compatible, but not necessarily exactly the same.
>From 01e8c4224a1a0b8e1067c087f3a5e1283566f80a Mon Sep 17 00:00:00 2001
F
https://github.com/rampitec closed
https://github.com/llvm/llvm-project/pull/112447
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https://github.com/rampitec updated
https://github.com/llvm/llvm-project/pull/112447
>From 761b3e21748dd3a7b53cd0ead745943213317eb4 Mon Sep 17 00:00:00 2001
From: Stanislav Mekhanoshin
Date: Tue, 15 Oct 2024 15:23:28 -0700
Subject: [PATCH 1/7] [AMDGPU] Allow overload of
__builtin_amdgcn_mov/up
https://github.com/rampitec updated
https://github.com/llvm/llvm-project/pull/112447
>From 761b3e21748dd3a7b53cd0ead745943213317eb4 Mon Sep 17 00:00:00 2001
From: Stanislav Mekhanoshin
Date: Tue, 15 Oct 2024 15:23:28 -0700
Subject: [PATCH 1/7] [AMDGPU] Allow overload of
__builtin_amdgcn_mov/up
https://github.com/rampitec updated
https://github.com/llvm/llvm-project/pull/112447
>From 761b3e21748dd3a7b53cd0ead745943213317eb4 Mon Sep 17 00:00:00 2001
From: Stanislav Mekhanoshin
Date: Tue, 15 Oct 2024 15:23:28 -0700
Subject: [PATCH 1/6] [AMDGPU] Allow overload of
__builtin_amdgcn_mov/up
rampitec wrote:
I actually wish a better way to have overloaded builtins in clang. I do not
believe any user of these builtins is expecting that a wide integer will be
silently truncated, and any fp will go through fptosi and backwards after, like
we do now. We have much more builtins like tha
https://github.com/rampitec updated
https://github.com/llvm/llvm-project/pull/112447
>From 761b3e21748dd3a7b53cd0ead745943213317eb4 Mon Sep 17 00:00:00 2001
From: Stanislav Mekhanoshin
Date: Tue, 15 Oct 2024 15:23:28 -0700
Subject: [PATCH 1/6] [AMDGPU] Allow overload of
__builtin_amdgcn_mov/up
https://github.com/rampitec updated
https://github.com/llvm/llvm-project/pull/112447
>From 761b3e21748dd3a7b53cd0ead745943213317eb4 Mon Sep 17 00:00:00 2001
From: Stanislav Mekhanoshin
Date: Tue, 15 Oct 2024 15:23:28 -0700
Subject: [PATCH 1/6] [AMDGPU] Allow overload of
__builtin_amdgcn_mov/up
@@ -7,3 +7,37 @@ void test_gfx9_fmed3h(global half *out, half a, half b, half c)
{
*out = __builtin_amdgcn_fmed3h(a, b, c); // expected-error
{{'__builtin_amdgcn_fmed3h' needs target feature gfx9-insts}}
}
+
+void test_mov_dpp(global int* out, int src, int i)
+{
+ *out = __
@@ -102,20 +102,66 @@ void test_s_dcache_wb()
__builtin_amdgcn_s_dcache_wb();
}
-// CHECK-LABEL: @test_mov_dpp
+// CHECK-LABEL: @test_mov_dpp_int
// CHECK: {{.*}}call{{.*}} i32 @llvm.amdgcn.update.dpp.i32(i32 poison, i32
%src, i32 0, i32 0, i32 0, i1 false)
-void test_mov_
https://github.com/rampitec updated
https://github.com/llvm/llvm-project/pull/112447
>From 761b3e21748dd3a7b53cd0ead745943213317eb4 Mon Sep 17 00:00:00 2001
From: Stanislav Mekhanoshin
Date: Tue, 15 Oct 2024 15:23:28 -0700
Subject: [PATCH 1/5] [AMDGPU] Allow overload of
__builtin_amdgcn_mov/up
@@ -102,20 +102,66 @@ void test_s_dcache_wb()
__builtin_amdgcn_s_dcache_wb();
}
-// CHECK-LABEL: @test_mov_dpp
+// CHECK-LABEL: @test_mov_dpp_int
// CHECK: {{.*}}call{{.*}} i32 @llvm.amdgcn.update.dpp.i32(i32 poison, i32
%src, i32 0, i32 0, i32 0, i1 false)
-void test_mov_
@@ -102,20 +102,66 @@ void test_s_dcache_wb()
__builtin_amdgcn_s_dcache_wb();
}
-// CHECK-LABEL: @test_mov_dpp
+// CHECK-LABEL: @test_mov_dpp_int
// CHECK: {{.*}}call{{.*}} i32 @llvm.amdgcn.update.dpp.i32(i32 poison, i32
%src, i32 0, i32 0, i32 0, i1 false)
-void test_mov_
rampitec wrote:
> This needs some sema type restrictions to make sure it's something sensible
Added.
https://github.com/llvm/llvm-project/pull/112447
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https://github.com/rampitec updated
https://github.com/llvm/llvm-project/pull/112447
>From 761b3e21748dd3a7b53cd0ead745943213317eb4 Mon Sep 17 00:00:00 2001
From: Stanislav Mekhanoshin
Date: Tue, 15 Oct 2024 15:23:28 -0700
Subject: [PATCH 1/4] [AMDGPU] Allow overload of
__builtin_amdgcn_mov/up
@@ -224,8 +224,8 @@ TARGET_BUILTIN(__builtin_amdgcn_frexp_exph, "sh", "nc",
"16-bit-insts")
TARGET_BUILTIN(__builtin_amdgcn_fracth, "hh", "nc", "16-bit-insts")
TARGET_BUILTIN(__builtin_amdgcn_classh, "bhi", "nc", "16-bit-insts")
TARGET_BUILTIN(__builtin_amdgcn_s_memrealtime, "
rampitec wrote:
Note, there is also dpp8 with the similar problem. But dpp8 is not properly
handled even if intrinsic is used with a 64-bit type (i.e. not split into 2
separate 32-bit dpp ops). This would be a nice to have, but not absolutely
necessary like here, because there are no 64-bit re
https://github.com/rampitec updated
https://github.com/llvm/llvm-project/pull/112447
>From 761b3e21748dd3a7b53cd0ead745943213317eb4 Mon Sep 17 00:00:00 2001
From: Stanislav Mekhanoshin
Date: Tue, 15 Oct 2024 15:23:28 -0700
Subject: [PATCH 1/3] [AMDGPU] Allow overload of
__builtin_amdgcn_mov/up
https://github.com/rampitec updated
https://github.com/llvm/llvm-project/pull/112447
>From 761b3e21748dd3a7b53cd0ead745943213317eb4 Mon Sep 17 00:00:00 2001
From: Stanislav Mekhanoshin
Date: Tue, 15 Oct 2024 15:23:28 -0700
Subject: [PATCH 1/2] [AMDGPU] Allow overload of
__builtin_amdgcn_mov/up
https://github.com/rampitec created
https://github.com/llvm/llvm-project/pull/112447
We need to support 64-bit data types (intrinsics do support it). We are also
silently converting FP to integer argument now, also fixed.
>From 761b3e21748dd3a7b53cd0ead745943213317eb4 Mon Sep 17 00:00:00 2001
https://github.com/rampitec closed
https://github.com/llvm/llvm-project/pull/107293
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rampitec wrote:
> I think the parent needs some revision for global/flat/infer handling
Do you like this more? https://github.com/llvm/llvm-project/pull/107624
https://github.com/llvm/llvm-project/pull/107293
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@@ -0,0 +1,36 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
UTC_ARGS: --version 5
+; RUN: llc -global-isel=0 -march=amdgcn -mcpu=gfx1200 < %s | FileCheck
--check-prefix=GCN %s
+; RUN: llc -global-isel=1 -march=amdgcn -mcpu=gfx1200 < %s | FileC
https://github.com/rampitec updated
https://github.com/llvm/llvm-project/pull/107293
>From 8361742ca5fe20a3168b3274166909412e225184 Mon Sep 17 00:00:00 2001
From: Stanislav Mekhanoshin
Date: Wed, 4 Sep 2024 12:00:27 -0700
Subject: [PATCH 1/2] [AMDGPU] Add target intrinsic for s_buffer_prefetch_
@@ -9934,6 +9934,12 @@ SDValue SITargetLowering::LowerINTRINSIC_VOID(SDValue Op,
auto NewMI = DAG.getMachineNode(Opc, DL, Op->getVTList(), Ops);
return SDValue(NewMI, 0);
}
+ case Intrinsic::amdgcn_s_prefetch_data: {
+// For non-global address space preserve the
@@ -9934,6 +9934,12 @@ SDValue SITargetLowering::LowerINTRINSIC_VOID(SDValue Op,
auto NewMI = DAG.getMachineNode(Opc, DL, Op->getVTList(), Ops);
return SDValue(NewMI, 0);
}
+ case Intrinsic::amdgcn_s_prefetch_data: {
+// For non-global address space preserve the
@@ -9934,6 +9934,12 @@ SDValue SITargetLowering::LowerINTRINSIC_VOID(SDValue Op,
auto NewMI = DAG.getMachineNode(Opc, DL, Op->getVTList(), Ops);
return SDValue(NewMI, 0);
}
+ case Intrinsic::amdgcn_s_prefetch_data: {
+// For non-global address space preserve the
https://github.com/rampitec closed
https://github.com/llvm/llvm-project/pull/107133
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https://github.com/llvm/llvm-project/pull/107293
None
>From 8361742ca5fe20a3168b3274166909412e225184 Mon Sep 17 00:00:00 2001
From: Stanislav Mekhanoshin
Date: Wed, 4 Sep 2024 12:00:27 -0700
Subject: [PATCH] [AMDGPU] Add target intrinsic for s_buffer_prefetc
@@ -2689,6 +2689,12 @@ def int_amdgcn_global_load_tr_b128 :
AMDGPULoadIntrinsic;
def int_amdgcn_wave_id :
DefaultAttrsIntrinsic<[llvm_i32_ty], [], [NoUndef, IntrNoMem,
IntrSpeculatable]>;
+def int_amdgcn_s_prefetch_data :
+ Intrinsic<[], [llvm_anyptr_ty, llvm_i32_ty],
---
https://github.com/rampitec updated
https://github.com/llvm/llvm-project/pull/107133
>From 000e16cbd27783be68afdd9952c65e58f4cd7040 Mon Sep 17 00:00:00 2001
From: Stanislav Mekhanoshin
Date: Tue, 3 Sep 2024 10:14:35 -0700
Subject: [PATCH 1/4] [AMDGPU] Add target intrinsic for s_prefetch_data
-
@@ -0,0 +1,136 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
UTC_ARGS: --version 5
+; RUN: llc -global-isel=0 -march=amdgcn -mcpu=gfx1200 < %s | FileCheck
--check-prefixes=GCN,SDAG %s
+; RUN: llc -global-isel=1 -march=amdgcn -mcpu=gfx1200 < %s
@@ -19489,6 +19489,12 @@ Value *CodeGenFunction::EmitAMDGPUBuiltinExpr(unsigned
BuiltinID,
F, {EmitScalarExpr(E->getArg(0)), EmitScalarExpr(E->getArg(1)),
EmitScalarExpr(E->getArg(2)), EmitScalarExpr(E->getArg(3))});
}
+ case AMDGPU::BI__builtin_amdgcn_s
https://github.com/rampitec updated
https://github.com/llvm/llvm-project/pull/107133
>From 000e16cbd27783be68afdd9952c65e58f4cd7040 Mon Sep 17 00:00:00 2001
From: Stanislav Mekhanoshin
Date: Tue, 3 Sep 2024 10:14:35 -0700
Subject: [PATCH 1/3] [AMDGPU] Add target intrinsic for s_prefetch_data
-
https://github.com/rampitec updated
https://github.com/llvm/llvm-project/pull/107133
>From 000e16cbd27783be68afdd9952c65e58f4cd7040 Mon Sep 17 00:00:00 2001
From: Stanislav Mekhanoshin
Date: Tue, 3 Sep 2024 10:14:35 -0700
Subject: [PATCH 1/2] [AMDGPU] Add target intrinsic for s_prefetch_data
-
@@ -19489,6 +19489,12 @@ Value *CodeGenFunction::EmitAMDGPUBuiltinExpr(unsigned
BuiltinID,
F, {EmitScalarExpr(E->getArg(0)), EmitScalarExpr(E->getArg(1)),
EmitScalarExpr(E->getArg(2)), EmitScalarExpr(E->getArg(3))});
}
+ case AMDGPU::BI__builtin_amdgcn_s
https://github.com/rampitec created
https://github.com/llvm/llvm-project/pull/107133
None
>From 000e16cbd27783be68afdd9952c65e58f4cd7040 Mon Sep 17 00:00:00 2001
From: Stanislav Mekhanoshin
Date: Tue, 3 Sep 2024 10:14:35 -0700
Subject: [PATCH] [AMDGPU] Add target intrinsic for s_prefetch_data
https://github.com/rampitec approved this pull request.
https://github.com/llvm/llvm-project/pull/99551
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https://github.com/rampitec approved this pull request.
LGTM
https://github.com/llvm/llvm-project/pull/99540
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rampitec wrote:
> /build/buildbot/premerge-monolithic-linux/llvm-project/flang/lib/Frontend/CompilerInstance.cpp:226:44:
> error: too many arguments to function call, expected 3, have 4
Fixed.
https://github.com/llvm/llvm-project/pull/97633
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rampitec wrote:
[AMD Official Use Only - AMD Internal Distribution Only]
Fixed https://github.com/llvm/llvm-project/pull/98231
Sorry.
Stas
From: LLVM Continuous Integration ***@***.***>
Date: Tuesday, July 9, 2024 at 14:37
To: llvm/llvm-project ***@***.***>
Cc: Mekhanoshin, Stanislav ***@***.*
https://github.com/rampitec closed
https://github.com/llvm/llvm-project/pull/97633
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https://github.com/rampitec updated
https://github.com/llvm/llvm-project/pull/97633
>From dc9d1e2039981bb412e68975570d9911511bb880 Mon Sep 17 00:00:00 2001
From: Stanislav Mekhanoshin
Date: Wed, 3 Jul 2024 13:12:21 -0700
Subject: [PATCH 1/3] [AMDGPU] Report error in clang if wave32 is requested
@@ -188,8 +188,12 @@ bool AMDGPUTargetInfo::initFeatureMap(
// TODO: Should move this logic into TargetParser
std::string ErrorMsg;
- if (!insertWaveSizeFeature(CPU, getTriple(), Features, ErrorMsg)) {
-Diags.Report(diag::err_invalid_feature_combination) << ErrorMsg;
https://github.com/rampitec updated
https://github.com/llvm/llvm-project/pull/97633
>From dc9d1e2039981bb412e68975570d9911511bb880 Mon Sep 17 00:00:00 2001
From: Stanislav Mekhanoshin
Date: Wed, 3 Jul 2024 13:12:21 -0700
Subject: [PATCH 1/2] [AMDGPU] Report error in clang if wave32 is requested
@@ -188,8 +188,12 @@ bool AMDGPUTargetInfo::initFeatureMap(
// TODO: Should move this logic into TargetParser
std::string ErrorMsg;
- if (!insertWaveSizeFeature(CPU, getTriple(), Features, ErrorMsg)) {
-Diags.Report(diag::err_invalid_feature_combination) << ErrorMsg;
https://github.com/rampitec edited
https://github.com/llvm/llvm-project/pull/97633
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https://github.com/rampitec edited
https://github.com/llvm/llvm-project/pull/97633
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@@ -188,8 +188,12 @@ bool AMDGPUTargetInfo::initFeatureMap(
// TODO: Should move this logic into TargetParser
std::string ErrorMsg;
- if (!insertWaveSizeFeature(CPU, getTriple(), Features, ErrorMsg)) {
-Diags.Report(diag::err_invalid_feature_combination) << ErrorMsg;
https://github.com/rampitec created
https://github.com/llvm/llvm-project/pull/97633
None
>From dc9d1e2039981bb412e68975570d9911511bb880 Mon Sep 17 00:00:00 2001
From: Stanislav Mekhanoshin
Date: Wed, 3 Jul 2024 13:12:21 -0700
Subject: [PATCH] [AMDGPU] Report error in clang if wave32 is request
@@ -1534,6 +1534,12 @@ def FeatureISAVersion11_5_1 : FeatureSet<
FeatureVGPRSingleUseHintInsts,
Feature1_5xVGPRs])>;
+def FeatureISAVersion11_5_2 : FeatureSet<
rampitec wrote:
Then I defer review to Jay.
https://github.com/llvm/llvm-project/pull/94
@@ -1534,6 +1534,12 @@ def FeatureISAVersion11_5_1 : FeatureSet<
FeatureVGPRSingleUseHintInsts,
Feature1_5xVGPRs])>;
+def FeatureISAVersion11_5_2 : FeatureSet<
rampitec wrote:
I don't know, but if they are I have a question why a new target needed?
@@ -1534,6 +1534,12 @@ def FeatureISAVersion11_5_1 : FeatureSet<
FeatureVGPRSingleUseHintInsts,
Feature1_5xVGPRs])>;
+def FeatureISAVersion11_5_2 : FeatureSet<
rampitec wrote:
Looks the same as 1150?
https://github.com/llvm/llvm-project/pull/94534
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