[clang] [X86] Allow XOP rotate intrinsics to be used in constexpr (PR #157643)

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[clang] [Headers][X86] Allow SSE2/AVX2/AVX512F/AVX512BW/AVX512DQ integer arithmetic intrinsics to be used in constexpr (PR #157582)

https://github.com/RKSimon requested changes to this pull request. The next (tedious) step is to add test coverage - see #156369 for examples https://github.com/llvm/llvm-project/pull/157582 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https

[clang] [X86] Allow AVX512 funnel shift intrinsics to be used in constexpr (PR #157668)

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[clang] [Headers][X86] Enable constexpr handling for MMX/SSE/AVX/AVX512 avg intrinsics (PR #157464)

@@ -496,9 +496,8 @@ _mm256_andnot_si256(__m256i __a, __m256i __b) /// \param __b ///A 256-bit integer vector. /// \returns A 256-bit integer vector containing the result. -static __inline__ __m256i __DEFAULT_FN_ATTRS256 -_mm256_avg_epu8(__m256i __a, __m256i __b) -{ +static

[clang] [Headers][X86] Enable constexpr handling for MMX/SSE/AVX/AVX512 avg intrinsics (PR #157464)

@@ -24,6 +24,7 @@ typedef float __m128_u __attribute__((__vector_size__(16), __aligned__(1))); /* Unsigned types */ typedef unsigned int __v4su __attribute__((__vector_size__(16))); typedef unsigned short __v8hu __attribute__((__vector_size__(16))); +typedef unsigned char __v1

[clang] [Headers][X86] Enable constexpr handling for MMX/SSE/AVX/AVX512 avg intrinsics (PR #157464)

@@ -24,6 +24,7 @@ typedef float __m128_u __attribute__((__vector_size__(16), __aligned__(1))); /* Unsigned types */ typedef unsigned int __v4su __attribute__((__vector_size__(16))); typedef unsigned short __v8hu __attribute__((__vector_size__(16))); +typedef unsigned char __v1

[clang] [X86] Allow AVX512 rotate intrinsics to be used in constexpr (PR #157652)

https://github.com/RKSimon closed https://github.com/llvm/llvm-project/pull/157652 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [Mips] Convert -mnan=legacy to nan2008 when architecture support nan2008 (PR #153777)

@@ -620,6 +620,10 @@ def warn_target_unsupported_nan2008 : Warning< def warn_target_unsupported_nanlegacy : Warning< "ignoring '-mnan=legacy' option because the '%0' architecture does not support it">, InGroup; +def warn_target_unsupported_convertnanlegacytonan2008 : Warni

[clang] [X86] Allow AVX512 rotate intrinsics to be used in constexpr (PR #157652)

https://github.com/RKSimon created https://github.com/llvm/llvm-project/pull/157652 Now that they wrap the __builtin_elementwise_fshl/fshr builtin intrinsics this is pretty trivial. Another step towards #153152 - just VBMI2 double shifts remaining >From 3da4ab30326a7624e317046118d617c3031aaf6

[clang] [X86] Allow XOP rotate intrinsics to be used in constexpr (PR #157643)

https://github.com/RKSimon created https://github.com/llvm/llvm-project/pull/157643 Now that they wrap the __builtin_elementwise_fshl/fshr builtin intrinsics this is pretty trivial. Another step towards #153152 - I'll handle the AVX512 rotates next >From 9c75345b574a1d85a5a62efaf11d00ae61a1d1

[clang] [Headers][X86] Enable constexpr handling for MMX/SSE/AVX/AVX512 avg intrinsics (PR #157464)

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[clang] [X86] make the set/r/4 intrinsics macros into functions (PR #156819)

https://github.com/RKSimon updated https://github.com/llvm/llvm-project/pull/156819 >From 1e8482846c5d623192bb5ce8e21dbc4eeb3fd591 Mon Sep 17 00:00:00 2001 From: SadiinsoSnowfall Date: Thu, 4 Sep 2025 09:28:09 +0200 Subject: [PATCH] made the AVX512 _set macros into functions --- clang/lib/Hea

[clang] [Headers][X86] Group related AVX512VL FMA intrinsics together (NFC) (PR #156794)

https://github.com/RKSimon closed https://github.com/llvm/llvm-project/pull/156794 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] X86: make the set/r/4 intrinsics macros into functions (PR #156819)

https://github.com/RKSimon approved this pull request. LGTM - cheers https://github.com/llvm/llvm-project/pull/156819 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [clang] VectorExprEvaluator::VisitCallExpr - use APSInt callback instead of repeated switch statement (PR #157137)

https://github.com/RKSimon closed https://github.com/llvm/llvm-project/pull/157137 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [clang] VectorExprEvaluator::VisitCallExpr - use APSInt callback instead of repeated switch statement (PR #157137)

https://github.com/RKSimon created https://github.com/llvm/llvm-project/pull/157137 Create a EvaluateBinOpExpr helper that each related group of elementwise binop builtins can use with their own custom callback, to help reduce the amount of duplication and avoid too much code bloat as more bui

[clang] [X86][bytecode] Allow SSE/AVX PBLENDVB intrinsics to be used in constexpr (PR #157100)

https://github.com/RKSimon updated https://github.com/llvm/llvm-project/pull/157100 >From 497b8799fafe72dbbf3d9aab6f0b930f4ee91b09 Mon Sep 17 00:00:00 2001 From: Simon Pilgrim Date: Fri, 5 Sep 2025 14:07:26 +0100 Subject: [PATCH 1/2] [X86][bytecode] Allow SSE/AVX PBLENDVB intrinsics to be used

[clang] [Headers][X86] Allow AVX512 integer min/max mask/maskz variants intrinsics to be used in constexpr (PR #156901)

https://github.com/RKSimon auto_merge_enabled https://github.com/llvm/llvm-project/pull/156901 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [X86][bytecode] Allow SSE/AVX PBLENDVB intrinsics to be used in constexpr (PR #157100)

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[clang] [Clang][bytecode] Add interp__builtin_elementwise_triop_fp to handle general 3-operand floating point intrinsics (PR #157106)

@@ -2736,12 +2736,14 @@ static bool interp__builtin_ia32_pmul(InterpState &S, CodePtr OpPC, return true; } -static bool interp__builtin_elementwise_fma(InterpState &S, CodePtr OpPC, -const CallExpr *Call) { +static bool interp__bu

[clang] [clang] VectorExprEvaluator::VisitCallExpr - use APSInt callback instead of repeated switch statement (PR #157137)

https://github.com/RKSimon updated https://github.com/llvm/llvm-project/pull/157137 >From 32f6bdf7e206a09515ce6ee7c06a85ecee5fdaa3 Mon Sep 17 00:00:00 2001 From: Simon Pilgrim Date: Fri, 5 Sep 2025 17:28:21 +0100 Subject: [PATCH] [clang] VectorExprEvaluator::VisitCallExpr - use APSInt callback

[clang] [Headers][X86] Add constexpr support for some AVX[512] intrinsics. (PR #157260)

https://github.com/RKSimon updated https://github.com/llvm/llvm-project/pull/157260 >From 6a3ea1634162fa90e3b2deacb1b0ff7a1a907359 Mon Sep 17 00:00:00 2001 From: moorabbit Date: Thu, 4 Sep 2025 16:03:54 -0400 Subject: [PATCH 01/30] _mm_cvtepi64_pd --- clang/lib/Headers/avx512vldqintrin.h

[clang] [Headers][X86] Add constexpr support for some AVX[512] intrinsics. (PR #157260)

https://github.com/RKSimon closed https://github.com/llvm/llvm-project/pull/157260 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [Headers][X86] Add constexpr support for some AVX[512] intrinsics. (PR #157260)

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[clang] [Headers][X86] Add constexpr support for some AVX[512] intrinsics. (PR #157260)

https://github.com/RKSimon approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/157260 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [Clang][bytecode] interp__builtin_elementwise_binop - remove unused BuiltinID argument. NFC (PR #157109)

https://github.com/RKSimon closed https://github.com/llvm/llvm-project/pull/157109 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [Headers][X86] Allow AVX512 integer min/max mask/maskz variants intrinsics to be used in constexpr (PR #156901)

https://github.com/RKSimon approved this pull request. LGTM - cheers https://github.com/llvm/llvm-project/pull/156901 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [Clang][bytecode] Add interp__builtin_elementwise_triop_fp to handle general 3-operand floating point intrinsics (PR #157106)

https://github.com/RKSimon updated https://github.com/llvm/llvm-project/pull/157106 >From 4d6078f92740efa3f109b85492f43b8fadd39b03 Mon Sep 17 00:00:00 2001 From: Simon Pilgrim Date: Fri, 5 Sep 2025 14:32:07 +0100 Subject: [PATCH 1/2] [Clang][bytecode] Add interp__builtin_elementwise_triop_fp t

[clang] [Headers][X86] Allow AVX512 integer min/max mask/maskz variants intrinsics to be used in constexpr (PR #156901)

https://github.com/RKSimon closed https://github.com/llvm/llvm-project/pull/156901 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [clang] VectorExprEvaluator::VisitCallExpr - use APSInt callback instead of repeated switch statement (PR #157137)

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[clang] [Headers][X86] Allow AVX2/AVX512 integer min/max intrinsics to be used in constexpr (PR #156833)

https://github.com/RKSimon updated https://github.com/llvm/llvm-project/pull/156833 >From 2a180106369bb805ba95c6aef65442583b450ed9 Mon Sep 17 00:00:00 2001 From: Bhasawut Singhaphan Date: Wed, 3 Sep 2025 20:50:15 +0700 Subject: [PATCH] [Headers][X86] Allow AVX2/AVX512 integer min/max intrinsics

[clang] [Headers][X86] Allow AVX512 integer min/max mask/maskz variants intrinsics to be used in constexpr (PR #156901)

https://github.com/RKSimon commented: we still need to handle the mask/maskz variants in avx512vlintrin.h + avx512vlbwintrin.h https://github.com/llvm/llvm-project/pull/156901 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.

[clang] [X86][bytecode] Allow SSE/AVX PBLENDVB intrinsics to be used in constexpr (PR #157100)

https://github.com/RKSimon created https://github.com/llvm/llvm-project/pull/157100 BLENDV intrinsics use the signbit of the condition mask to select between the LHS (false) and RHS (true) operands First part of #157066 - the BLENDVPS/D requires floatbits hacking which I need to do some prep

[clang] [X86][bytecode] Allow SSE/AVX BLENDVPD/PD intrinsics to be used in constexpr (PR #157126)

https://github.com/RKSimon closed https://github.com/llvm/llvm-project/pull/157126 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [Clang] Rename elementwise builtins to `clzg` and `ctzg` (PR #157128)

RKSimon wrote: No objections, but only because we haven't had these builtins for very long. https://github.com/llvm/llvm-project/pull/157128 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-com

[clang] [X86][bytecode] Allow SSE/AVX BLENDVPD/PD intrinsics to be used in constexpr (PR #157126)

https://github.com/RKSimon updated https://github.com/llvm/llvm-project/pull/157126 >From f7db91d029dc81f99225deef3144b498e7195fbe Mon Sep 17 00:00:00 2001 From: Simon Pilgrim Date: Fri, 5 Sep 2025 16:35:45 +0100 Subject: [PATCH 1/2] [X86][bytecode] Allow SSE/AVX BLENDVPD/PD intrinsics to be u

[clang] [X86][bytecode] Allow SSE/AVX BLENDVPD/PD intrinsics to be used in constexpr (PR #157126)

https://github.com/RKSimon auto_merge_enabled https://github.com/llvm/llvm-project/pull/157126 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [X86][bytecode] Allow SSE/AVX BLENDVPD/PD intrinsics to be used in constexpr (PR #157126)

https://github.com/RKSimon updated https://github.com/llvm/llvm-project/pull/157126 >From f7db91d029dc81f99225deef3144b498e7195fbe Mon Sep 17 00:00:00 2001 From: Simon Pilgrim Date: Fri, 5 Sep 2025 16:35:45 +0100 Subject: [PATCH 1/2] [X86][bytecode] Allow SSE/AVX BLENDVPD/PD intrinsics to be u

[clang] [X86][bytecode] Allow SSE/AVX BLENDVPD/PD intrinsics to be used in constexpr (PR #157126)

@@ -3421,6 +3421,17 @@ bool InterpretBuiltin(InterpState &S, CodePtr OpPC, const CallExpr *Call, return F; }); + case clang::X86::BI__builtin_ia32_blendvpd: + case clang::X86::BI__builtin_ia32_blendvpd256: + case clang::X86::BI__builtin_ia32_blendvps: +

[clang] [Clang][bytecode] Add interp__builtin_elementwise_triop_fp to handle general 3-operand floating point intrinsics (PR #157106)

https://github.com/RKSimon closed https://github.com/llvm/llvm-project/pull/157106 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [Clang][bytecode] Add interp__builtin_elementwise_triop_fp to handle general 3-operand floating point intrinsics (PR #157106)

https://github.com/RKSimon created https://github.com/llvm/llvm-project/pull/157106 Refactor interp__builtin_elementwise_fma into something similar to interp__builtin_elementwise_triop with a callback function argument to allow reuse with other intrinsics This will allow reuse with some upcom

[clang] [X86][bytecode] Allow SSE/AVX BLENDVPD/PD intrinsics to be used in constexpr (PR #157126)

https://github.com/RKSimon created https://github.com/llvm/llvm-project/pull/157126 BLENDV intrinsics use the signbit of the condition mask to select between the LHS (false) and RHS (true) operands Fixes #157066 >From f7db91d029dc81f99225deef3144b498e7195fbe Mon Sep 17 00:00:00 2001 From: Sim

[clang] [X86][bytecode] Allow SSE/AVX PBLENDVB intrinsics to be used in constexpr (PR #157100)

https://github.com/RKSimon closed https://github.com/llvm/llvm-project/pull/157100 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [Clang][bytecode] Add interp__builtin_elementwise_triop_fp to handle general 3-operand floating point intrinsics (PR #157106)

https://github.com/RKSimon auto_merge_enabled https://github.com/llvm/llvm-project/pull/157106 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [Clang][bytecode] Add interp__builtin_elementwise_triop_fp to handle general 3-operand floating point intrinsics (PR #157106)

https://github.com/RKSimon updated https://github.com/llvm/llvm-project/pull/157106 >From 4d6078f92740efa3f109b85492f43b8fadd39b03 Mon Sep 17 00:00:00 2001 From: Simon Pilgrim Date: Fri, 5 Sep 2025 14:32:07 +0100 Subject: [PATCH 1/2] [Clang][bytecode] Add interp__builtin_elementwise_triop_fp t

[clang] [X86][bytecode] Allow SSE/AVX PBLENDVB intrinsics to be used in constexpr (PR #157100)

https://github.com/RKSimon updated https://github.com/llvm/llvm-project/pull/157100 >From 497b8799fafe72dbbf3d9aab6f0b930f4ee91b09 Mon Sep 17 00:00:00 2001 From: Simon Pilgrim Date: Fri, 5 Sep 2025 14:07:26 +0100 Subject: [PATCH 1/2] [X86][bytecode] Allow SSE/AVX PBLENDVB intrinsics to be used

[clang] [Clang][bytecode] Add interp__builtin_elementwise_triop to handle general 3-operand integer intrinsics (PR #156944)

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[clang] [llvm] [X86][AVX10] Remove EVEX512 and AVX10-256 implementations (PR #157034)

https://github.com/RKSimon approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/157034 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [X86][AVX10] Remove EVEX512 and AVX10-256 implementations (PR #157034)

https://github.com/RKSimon commented: Do we have any test coverage of the error messages if people use the old args and does it explain how they can fix it? Not sure how important it is given its still early days for avx10 but I imagine someone has already started using it.. https://githu

[clang] [Clang][bytecode] Add interp__builtin_elementwise_triop to handle general 3-operand integer intrinsics (PR #156944)

https://github.com/RKSimon closed https://github.com/llvm/llvm-project/pull/156944 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [Clang][bytecode] Add interp__builtin_elementwise_triop to handle general 3-operand integer intrinsics (PR #156944)

https://github.com/RKSimon updated https://github.com/llvm/llvm-project/pull/156944 >From 4fa0ff01c7114ab69d44de3da4b4ca9132d8bf5e Mon Sep 17 00:00:00 2001 From: Simon Pilgrim Date: Thu, 4 Sep 2025 19:22:44 +0100 Subject: [PATCH 1/2] [Clang][bytecode] Add interp__builtin_elementwise_triop to h

[clang] [Clang] Enable constexpr handling for builtin elementwise fshl/fshr (PR #153572)

https://github.com/RKSimon closed https://github.com/llvm/llvm-project/pull/153572 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [Clang][bytecode] Add interp__builtin_elementwise_triop to handle general 3-operand integer intrinsics (PR #156944)

https://github.com/RKSimon created https://github.com/llvm/llvm-project/pull/156944 Refactor interp__builtin_elementwise_fsh into something similar to interp__builtin_elementwise_int_binop with a callback function argument to allow reuse with other intrinsics This will allow reuse with some u

[clang] add MMX/SSE/AVX PHADD/SUB & HADDPS/D intrinsics to be used in constexpr (PR #156822)

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[clang] [Clang] Enable constexpr handling for builtin elementwise fshl/fshr (PR #153572)

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[clang] [X86] make the set/r/4 intrinsics macros into functions (PR #156819)

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[clang] [X86] Add MMX/SSE/AVX PHADD/SUB & HADDPS/D intrinsics to be used in constexpr (PR #156822)

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[clang] [Headers][X86] Allow AVX2/AVX512 integer min/max intrinsics to be used in constexpr (PR #156833)

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[clang] [Headers][X86] Allow AVX2/AVX512 integer min/max intrinsics to be used in constexpr (PR #156833)

https://github.com/RKSimon approved this pull request. LGTM - cheers https://github.com/llvm/llvm-project/pull/156833 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [Headers][X86] Group related AVX512VL FMA intrinsics together (NFC) (PR #156794)

https://github.com/RKSimon approved this pull request. LGTM - cheers https://github.com/llvm/llvm-project/pull/156794 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [X86] make the set/r/4 intrinsics macros into functions (PR #156819)

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[clang] [Headers][X86] Add constexpr support for some AVX[512] intrinsics. (PR #156567)

https://github.com/RKSimon closed https://github.com/llvm/llvm-project/pull/156567 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [Headers][X86] Add constexpr support for some AVX[512] intrinsics. (PR #156567)

RKSimon wrote: > @RKSimon `git clang-format` doesn't report any formatting errors locally. Do > you want me to manually apply the formatting patch suggested by the > github-actions bot? No I don't think those are necessary changes tbh. https://github.com/llvm/llvm-project/pull/156567

[clang] X86: make the setr_ph intrinsics functions (PR #156819)

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[clang] add MMX/SSE/AVX PHADD/SUB & HADDPS/D intrinsics to be used in constexpr #155395 (PR #156822)

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[clang] [Headers][X86] Allow MMX/SSE integer min/max intrinsics to be used in constexpr (PR #156678)

https://github.com/RKSimon closed https://github.com/llvm/llvm-project/pull/156678 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [Headers][X86] Allow MMX/SSE integer min/max intrinsics to be used in constexpr (PR #156678)

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[clang] [Headers][X86] Allow MMX/SSE integer min/max intrinsics to be used in constexpr (PR #156678)

https://github.com/RKSimon updated https://github.com/llvm/llvm-project/pull/156678 >From 5bdb914dc978150575a82f48e087f732f0e833ec Mon Sep 17 00:00:00 2001 From: Bhasawut Singhaphan Date: Wed, 3 Sep 2025 20:44:26 +0700 Subject: [PATCH] [Headers][X86] Allow MMX/SSE integer min/max intrinsics to

[clang] [Headers][X86] Allow MMX/SSE integer min/max intrinsics to be used in constexpr (PR #156678)

https://github.com/RKSimon approved this pull request. LGTM - cheers https://github.com/llvm/llvm-project/pull/156678 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [Headers][X86] Allow FMA intrinsics to be used in constexpr (PR #156385)

https://github.com/RKSimon closed https://github.com/llvm/llvm-project/pull/156385 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [Headers][X86] Allow FMA intrinsics to be used in constexpr (PR #156385)

https://github.com/RKSimon approved this pull request. LGTM - the mask3 intrinsics seem to be mixed up randomly and could do with sorting out at some point to be consistently with their siblings, but that's not relevant for this patch. https://github.com/llvm/llvm-project/pull/156385 _

[clang] [Headers][X86] Allow FMA intrinsics to be used in constexpr (PR #156385)

@@ -2501,125 +2501,104 @@ _mm512_maskz_div_ps(__mmask16 __U, __m512 __A, __m512 __B) { -(__v8df)(__m512d)(C), \ (__mmask8)(U), (int)(R))) +static __inline__ __m512d __DEFAULT_FN_ATTRS512

[clang] [Clang] Enable constexpr handling for builtin elementwise fshl/fshr (PR #153572)

RKSimon wrote: @ckoparkar reverse-ping - what's still needed on this patch? https://github.com/llvm/llvm-project/pull/153572 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [Headers][X86] Allow AVX512 masked blend intrinsics to be used in constexpr (PR #156234)

https://github.com/RKSimon requested changes to this pull request. https://github.com/llvm/llvm-project/pull/156234 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [Headers][X86] Allow AVX512 masked blend intrinsics to be used in constexpr (PR #156234)

@@ -915,7 +948,14 @@ __m128i test_mm_mask_abs_epi8(__m128i __W, __mmask16 __U, __m128i __A) { // CHECK: select <16 x i1> %{{.*}}, <16 x i8> [[ABS]], <16 x i8> %{{.*}} return _mm_mask_abs_epi8(__W,__U,__A); } -TEST_CONSTEXPR(match_v16qi(_mm_mask_abs_epi8((__m128i)(__v16qi)

[clang] [X86] Update BMI, BMI2 and TBM constexpr tests (PR #156260)

@@ -237,85 +238,85 @@ unsigned long long test_blsr_u64(unsigned long long __X) { // Test constexpr handling. #if defined(__cplusplus) && (__cplusplus >= 201103L) -char andnu32[__andn_u32(0x01234567, 0xFECDBA98) == (~0x01234567 & 0xFECDBA98) ? 1 : -1]; -char andn2u32[_andn_u32

[clang] [Headers][X86] Add constexpr support for some AVX[512] intrinsics. (PR #156187)

https://github.com/RKSimon approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/156187 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [X86] Allow AVX512 512-bit variants of AVX2 per-element i32 shift intrinsics to be used in constexpr (PR #156480)

https://github.com/RKSimon closed https://github.com/llvm/llvm-project/pull/156480 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [X86] Update BMI, BMI2 and TBM constexpr tests (PR #156260)

https://github.com/RKSimon requested changes to this pull request. https://github.com/llvm/llvm-project/pull/156260 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [X86] Clear EVEX512 feature for 128-bit and 256-bit FMA intrinsics (PR #156472)

https://github.com/RKSimon approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/156472 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [X86] Add -fexperimental-new-constant-interpreter test coverage to the x86 scalar rotate constexpr test files (PR #156337)

https://github.com/RKSimon created https://github.com/llvm/llvm-project/pull/156337 Update tests to use builtin_test_helpers.h and the TEST_CONSTEXPR helper macro Partial fix for #155814 >From 5b994ec0a36c1a4a3d6b9781cde9ecea2babc664 Mon Sep 17 00:00:00 2001 From: Simon Pilgrim Date: Mon, 1 S

[clang] [X86] Allow AVX512 512-bit variants of AVX2 per-element i32 shift intrinsics to be used in constexpr (PR #156480)

https://github.com/RKSimon created https://github.com/llvm/llvm-project/pull/156480 Followup to #154780 >From 2bed7f329c50218cb2173c555a9f3ffae31e4241 Mon Sep 17 00:00:00 2001 From: Simon Pilgrim Date: Tue, 2 Sep 2025 16:51:42 +0100 Subject: [PATCH] [X86] Allow AVX512 512-bit variants of AVX2

[clang] [X86] Allow AVX512 512-bit variants of AVX2 per-element i32 shift intrinsics to be used in constexpr (PR #156480)

https://github.com/RKSimon updated https://github.com/llvm/llvm-project/pull/156480 >From 2bed7f329c50218cb2173c555a9f3ffae31e4241 Mon Sep 17 00:00:00 2001 From: Simon Pilgrim Date: Tue, 2 Sep 2025 16:51:42 +0100 Subject: [PATCH 1/2] [X86] Allow AVX512 512-bit variants of AVX2 per-element shif

[clang] [Headers][X86] Allow FMA intrinsics to be used in constexpr (PR #156385)

@@ -2501,125 +2501,124 @@ _mm512_maskz_div_ps(__mmask16 __U, __m512 __A, __m512 __B) { -(__v8df)(__m512d)(C), \ (__mmask8)(U), (int)(R))) +static __inline__ __m512d __DEFAULT_FN_ATTRS512

[clang] [Headers][X86] Allow FMA intrinsics to be used in constexpr (PR #156385)

https://github.com/RKSimon requested changes to this pull request. https://github.com/llvm/llvm-project/pull/156385 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [Headers][X86] Allow FMA intrinsics to be used in constexpr (PR #156385)

@@ -2501,125 +2501,124 @@ _mm512_maskz_div_ps(__mmask16 __U, __m512 __A, __m512 __B) { -(__v8df)(__m512d)(C), \ (__mmask8)(U), (int)(R))) +static __inline__ __m512d __DEFAULT_FN_ATTRS512

[clang] Allow vector zero padding intrinsics to be used in constexpr (PR #156441)

RKSimon wrote: > @RKSimon I've changed my account settings to make my email address public, > though I'm not sure whether that will retroactively fix the problem? Yes that seems to have worked - auto-merge now reports your proton address. Thanks. https://github.com/llvm/llvm-project/pull/1564

[clang] [Headers][X86] Allow FMA intrinsics to be used in constexpr (PR #156385)

@@ -2501,125 +2501,124 @@ _mm512_maskz_div_ps(__mmask16 __U, __m512 __A, __m512 __B) { -(__v8df)(__m512d)(C), \ (__mmask8)(U), (int)(R))) +static __inline__ __m512d __DEFAULT_FN_ATTRS512

[clang] Allow vector zero padding intrinsics to be used in constexpr (PR #156441)

https://github.com/RKSimon closed https://github.com/llvm/llvm-project/pull/156441 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] Allow vector zero padding intrinsics to be used in constexpr (PR #156441)

https://github.com/RKSimon auto_merge_enabled https://github.com/llvm/llvm-project/pull/156441 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] Allow vector zero padding intrinsics to be used in constexpr (PR #156441)

https://github.com/RKSimon approved this pull request. LGTM - cheers https://github.com/llvm/llvm-project/pull/156441 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] Allow vector zero padding intrinsics to be used in constexpr (PR #156441)

https://github.com/RKSimon updated https://github.com/llvm/llvm-project/pull/156441 >From b42f6d8cb05049269689adabb21b66637d491f00 Mon Sep 17 00:00:00 2001 From: Ellis Kesterton <31514698+ea...@users.noreply.github.com> Date: Tue, 2 Sep 2025 11:56:17 +0100 Subject: [PATCH] Allow vector zero padd

[clang] Allow vector zero padding intrinsics to be used in constexpr (PR #156441)

RKSimon wrote: @eayus are you able to fix your public github address please? https://github.com/llvm/llvm-project/pull/156441 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [Headers][X86] Allow SSE2/AVX2/AVX512F/AVX512BW/AVX512DQ integer multiply intrinsics to be used in constexpr (PR #156369)

https://github.com/RKSimon closed https://github.com/llvm/llvm-project/pull/156369 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [Headers][X86] Allow SSE2/AVX2/AVX512F/AVX512BW/AVX512DQ integer multiply intrinsics to be used in constexpr (PR #156369)

https://github.com/RKSimon approved this pull request. LGTM - cheers https://github.com/llvm/llvm-project/pull/156369 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [clang] Make vector cast intrinsics constexpr (PR #156381)

https://github.com/RKSimon requested changes to this pull request. Thanks - the next step is to add suitable test coverage to the relevant builtins file like we have in the other x86 constexpr patches e.g. https://github.com/llvm/llvm-project/pull/152435 https://github.com/llvm/llvm-project/pu

[clang] [Headers][X86] Allow FMA intrinsics to be used in constexpr (PR #156385)

@@ -2501,125 +2501,124 @@ _mm512_maskz_div_ps(__mmask16 __U, __m512 __A, __m512 __B) { -(__v8df)(__m512d)(C), \ (__mmask8)(U), (int)(R))) +static __inline__ __m512d __DEFAULT_FN_ATTRS512

[clang] [Headers][X86] Allow SSE2/AVX2/AVX512F/AVX512BW/AVX512DQ integer multiply intrinsics to be used in constexpr (PR #156369)

https://github.com/RKSimon commented: Thanks - the next step is to add suitable test coverage to the relevant builtins file like we have in the other x86 constexpr patches e.g. #152435 https://github.com/llvm/llvm-project/pull/156369 ___ cfe-commits m

[clang] [clang] Make vector cast intrinsics constexpr (PR #156381)

https://github.com/RKSimon edited https://github.com/llvm/llvm-project/pull/156381 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [X86] Add -fexperimental-new-constant-interpreter test coverage to the u32/f32 u64/f64 cast constexpr test files (PR #156327)

https://github.com/RKSimon closed https://github.com/llvm/llvm-project/pull/156327 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

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