https://github.com/paulwalker-arm updated
https://github.com/llvm/llvm-project/pull/130973
>From 32a2805a41dc3ff02bff9df26f4665923445b488 Mon Sep 17 00:00:00 2001
From: Paul Walker
Date: Thu, 20 Mar 2025 14:58:51 +
Subject: [PATCH 1/2] Add SROA tests for casts between fixed and scalable
ty
@@ -2034,6 +2071,18 @@ static Value *convertValue(const DataLayout &DL,
IRBuilderTy &IRB, Value *V,
}
}
+ if (isa(NewTy) && isa(OldTy)) {
+auto *Ty = VectorType::getWithSizeAndScalar(cast(NewTy),
OldTy);
+V = IRB.CreateInsertVector(Ty, PoisonValue::get(Ty), V,
@@ -473,6 +473,14 @@ std::optional Attribute::getVScaleRangeMax()
const {
return unpackVScaleRangeArgs(pImpl->getValueAsInt()).second;
}
+unsigned Attribute::getVScaleValue() const {
+ std::optional VScale = getVScaleRangeMax();
+ if (VScale && *VScale == getVScaleRangeMi
https://github.com/paulwalker-arm edited
https://github.com/llvm/llvm-project/pull/130973
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https://github.com/llvm/llvm-project/pull/130625
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@@ -26,11 +26,15 @@ typedef vbool64_t fixed_bool64_t
__attribute__((riscv_rvv_vector_bits(__riscv_v_
//
// CHECK-128-LABEL: @call_bool32_ff(
// CHECK-128-NEXT: entry:
+// CHECK-128-NEXT:[[SAVED_VALUE:%.*]] = alloca <1 x i8>, align 1
paulwalker-arm wrote:
paulwalker-arm wrote:
Sorry for the delay and thanks for the investigation @rj-jesus. This is so
not intentional behaviour. VLS based auto vectorisation was implemented before
the VLS ACLE extensions and by that time it's likely fixed length calls to
`llvm.vscale()` were constant folded a
paulwalker-arm wrote:
@pawosm-arm - I've removed the reviewers because it is not quite ready yet. I
need to investigate the potential regressions shown by the RISCV tests.
https://github.com/llvm/llvm-project/pull/130973
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https://github.com/paulwalker-arm created
https://github.com/llvm/llvm-project/pull/130973
For function whose vscale_range is limited to a single value we can size
scalable vectors. This aids SROA by allowing scalable vector load and store
operations to be considered for replacement whereby bi
https://github.com/paulwalker-arm updated
https://github.com/llvm/llvm-project/pull/130973
>From 487a823a9ec35df1a93109ef03630738bdc39ab1 Mon Sep 17 00:00:00 2001
From: Paul Walker
Date: Fri, 7 Mar 2025 11:54:20 +
Subject: [PATCH] [LLVM][SROA] Teach SROA how to "bitcast" between fixed and
@@ -405,6 +405,17 @@ class AArch64Subtarget final : public
AArch64GenSubtargetInfo {
return MinSVEVectorSizeInBits;
}
+ // Return the known bit length of SVE data registers. A value of 0 means the
+ // length is unkown beyond what's implied by the architecture.
+ uns
@@ -7380,17 +7380,31 @@ bool
AArch64DAGToDAGISel::SelectAddrModeIndexedSVE(SDNode *Root, SDValue N,
return false;
SDValue VScale = N.getOperand(1);
- if (VScale.getOpcode() != ISD::VSCALE)
+ std::optional MulImm;
+ if (VScale.getOpcode() == ISD::VSCALE) {
+MulImm
https://github.com/paulwalker-arm approved this pull request.
Other than a potentially erroneous assert this looks good to me.
https://github.com/llvm/llvm-project/pull/129732
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@@ -7380,12 +7380,26 @@ bool
AArch64DAGToDAGISel::SelectAddrModeIndexedSVE(SDNode *Root, SDValue N,
return false;
SDValue VScale = N.getOperand(1);
- if (VScale.getOpcode() != ISD::VSCALE)
+ int64_t MulImm = std::numeric_limits::max();
+ if (VScale.getOpcode() == ISD
@@ -405,6 +405,17 @@ class AArch64Subtarget final : public
AArch64GenSubtargetInfo {
return MinSVEVectorSizeInBits;
}
+ // Return the known bit length of SVE data registers. A value of 0 means the
+ // length is unkown beyond what's implied by the architecture.
+ uns
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@@ -7380,17 +7380,31 @@ bool
AArch64DAGToDAGISel::SelectAddrModeIndexedSVE(SDNode *Root, SDValue N,
return false;
SDValue VScale = N.getOperand(1);
- if (VScale.getOpcode() != ISD::VSCALE)
+ std::optional MulImm;
+ if (VScale.getOpcode() == ISD::VSCALE) {
+MulImm
@@ -0,0 +1,362 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
UTC_ARGS: --version 5
+; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s | FileCheck %s
+; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve
-aarch64-sve-vector-bits-min=128 -aarc
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@@ -2993,6 +2993,22 @@ let Predicates = [HasSVE_or_SME] in {
defm : unpred_loadstore_bitcast;
defm : unpred_loadstore_bitcast;
+ // Allow using LDR/STR to avoid the predicate dependence.
+ let Predicates = [IsLE, AllowMisalignedMemAccesses] in
paulwalker
https://github.com/paulwalker-arm approved this pull request.
Based on the previous conversation I'm happy enough. I don't think the
existing bug needs to hold up this PR and I can take a look at fixing it once
this lands.
Please keep an ear out for any performance regression reports just in
https://github.com/paulwalker-arm edited
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@@ -2993,6 +2993,22 @@ let Predicates = [HasSVE_or_SME] in {
defm : unpred_loadstore_bitcast;
defm : unpred_loadstore_bitcast;
+ // Allow using LDR/STR to avoid the predicate dependence.
+ let Predicates = [IsLE, AllowMisalignedMemAccesses] in
+foreach Ty = [ nxv16i8
@@ -2993,6 +2993,22 @@ let Predicates = [HasSVE_or_SME] in {
defm : unpred_loadstore_bitcast;
defm : unpred_loadstore_bitcast;
+ // Allow using LDR/STR to avoid the predicate dependence.
+ let Predicates = [IsLE, AllowMisalignedMemAccesses] in
+foreach Ty = [ nxv16i8
paulwalker-arm wrote:
I see what you mean. I was concerned because the SVE variant makes special
mention of it but when looking as the pseudo code for the NEON variants I agree
they look consistent. Sorry for the confusion.
https://github.com/llvm/llvm-project/pull/127837
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@@ -1738,6 +1738,12 @@ SDValue SelectionDAGBuilder::getValueImpl(const Value
*V) {
if (const auto *NC = dyn_cast(C))
return getValue(NC->getGlobalValue());
+if (VT == MVT::aarch64svcount) {
+ assert(C->isNullValue() && "Can only zero this target type!");
+
https://github.com/paulwalker-arm approved this pull request.
https://github.com/llvm/llvm-project/pull/120753
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https://github.com/paulwalker-arm updated
https://github.com/llvm/llvm-project/pull/120443
>From 35989b3a5b78f1eacc13104d9fdb806eb92ac7ae Mon Sep 17 00:00:00 2001
From: Paul Walker
Date: Wed, 18 Dec 2024 13:17:13 +
Subject: [PATCH 1/3] Add test to show missing CSE.
---
.../post-vectorisat
@@ -1306,6 +1306,10 @@ void PassBuilder::addVectorPasses(OptimizationLevel
Level,
}
// Cleanup after the loop optimization passes.
FPM.addPass(InstCombinePass());
+ // InstCombine can create CSE opportunities when it cleans the result of loop
+ // vectorization. They o
https://github.com/paulwalker-arm created
https://github.com/llvm/llvm-project/pull/120443
I revisited 58690 and was puzzled why the obvious combines do not fire. I
believe the reason is combines that end with replaceOperand, because they can
introduce duplicate expression trees (albeit tiny o
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@@ -0,0 +1,23 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
UTC_ARGS: --version 2
+// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64-none-linux-gnu
-target-feature +sve -emit-llvm -o - %s | FileCheck %s
+
+#include
+
+using vec_t =
@@ -0,0 +1,23 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
UTC_ARGS: --version 2
+// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64-none-linux-gnu
-target-feature +sve -emit-llvm -o - %s | FileCheck %s
+
+#include
+
+using vec_t =
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https://github.com/paulwalker-arm approved this pull request.
Looks good but please remember to update the commit message to reflect the PR
as it stands today.
https://github.com/llvm/llvm-project/pull/114804
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paulwalker-arm wrote:
Thanks @CarolineConcatto this is structurally more what I had in mind. The
non-fp8 neon types make use of general vector support within clang but the fp8
based types are completely target specific and so I'd rather keep their spread
within common code to a minimum. Neon
@@ -490,6 +490,16 @@ void tools::AddLinkerInputs(const ToolChain &TC, const
InputInfoList &Inputs,
else
A.renderAsInput(Args, CmdArgs);
}
+ if (const Arg *A = Args.getLastArg(options::OPT_fveclib)) {
+if (A->getNumValues() == 1) {
+ StringRef V = A->getVa
paulwalker-arm wrote:
The flags are only intended to control the C++ representation of constant
splats and do not affect the parsing[1] or printing.
After this PR the expected behaviour is to unify the textual representation of
constant splats. I did not anticipate there being a need to contr
@@ -490,6 +490,16 @@ void tools::AddLinkerInputs(const ToolChain &TC, const
InputInfoList &Inputs,
else
A.renderAsInput(Args, CmdArgs);
}
+ if (const Arg *A = Args.getLastArg(options::OPT_fveclib)) {
+if (A->getNumValues() == 1) {
+ StringRef V = A->getVa
paulwalker-arm wrote:
What's the advantage of moving away from the current implementation? From what
I can see we're now having to add knowledge about what's essentially a target
specific type across common code, which the current implementation avoids.
https://github.com/llvm/llvm-project/pu
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paulwalker-arm wrote:
I've pushed
https://github.com/llvm/llvm-project/commit/246b57cb2086b22ad8b41051c77e86ef478053a1
to fix the failing PowerPC tests. For what it's worth I think the tests are
overly restricted to only run on PowerPC machines, hence the reason they only
failed after the PR
paulwalker-arm wrote:
> Yet we see a value in the change proposed here too hence a good reason for
> merging it.
I've clearly misunderstood the context of the rebase. What is the value in
merging this change if the original issue has already been resolved? I guess
this fix is simpler and
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https://github.com/paulwalker-arm approved this pull request.
The change looks reasonable to me and consistent within an existing solution to
a similar problem. Worse case, the new code should be removed when we're at a
point that instruction fast math flags are sufficiently preserved/propagat
@@ -1690,6 +1690,23 @@ static void WriteConstantInternal(raw_ostream &Out,
const Constant *CV,
if (isa(CV) || isa(CV)) {
auto *CVVTy = cast(CV->getType());
Type *ETy = CVVTy->getElementType();
+
+// Use the same shorthand for splat vector (i.e. "splat(Ty val)") a
@@ -1690,6 +1690,23 @@ static void WriteConstantInternal(raw_ostream &Out,
const Constant *CV,
if (isa(CV) || isa(CV)) {
auto *CVVTy = cast(CV->getType());
Type *ETy = CVVTy->getElementType();
+
+// Use the same shorthand for splat vector (i.e. "splat(Ty val)") a
@@ -0,0 +1,91 @@
+// RUN: %clang_cc1 -std=c++11 -triple aarch64-arm-none-eabi -target-feature
-fp8 -ast-dump %s | \
+// RUN: FileCheck %s --strict-whitespace
+
+// REQUIRES: aarch64-registered-target || arm-registered-target
+
+/* Various contexts where type __mfp8 can appear.
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@@ -2590,6 +2590,7 @@ void NeonEmitter::runVectorTypes(raw_ostream &OS) {
OS << "#if defined(__aarch64__) || defined(__arm64ec__)\n";
OS << "typedef __MFloat8x8_t mfloat8x8_t;\n";
OS << "typedef __MFloat8x16_t mfloat8x16_t;\n";
+ OS << "typedef __MFloat8_t __mfp8;\n";
--
@@ -107,6 +107,15 @@
AARCH64_VECTOR_TYPE(Name, MangledName, Id, SingletonId)
#endif
+#ifndef AARCH64_SCALAR_TYPE
+#define AARCH64_SCALAR_TYPE(Name, MangledName, Id, SingletonId) \
+ SVE_TYPE(Name, Id, SingletonId)
+#endif
+
+#ifndef AARCH64_SCALAR_TYPE_MFLOAT
+#define AARCH
@@ -4302,6 +4308,7 @@ ASTContext::getBuiltinVectorTypeInfo(const BuiltinType
*Ty) const {
case BuiltinType::Id:
\
return {BoolTy, llvm::ElementCount::getScalable(NumEls), NF};
#define SVE_OPAQUE_TYPE(Name, MangledNa
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paulwalker-arm wrote:
FYI: I've separated the code changes into a separate (first) commit to aid
review.
https://github.com/llvm/llvm-project/pull/112548
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@@ -1687,6 +1692,46 @@ static void WriteConstantInternal(raw_ostream &Out,
const Constant *CV,
return;
}
+ // When in the mode where Constant{Int,FP} do not support vector types the
+ // "splat(Ty val)" syntax is interpreted as a ConstantDataVector. Maintaining
+ //
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@@ -2580,6 +2580,8 @@ void NeonEmitter::runVectorTypes(raw_ostream &OS) {
OS << "typedef __fp16 float16_t;\n";
OS << "#if defined(__aarch64__) || defined(__arm64ec__)\n";
+ OS << "typedef __MFloat8x8_t mfloat8x8_t;\n";
+ OS << "typedef __MFloat8x16_t mfloat8x16_t;\n";
--
@@ -2580,6 +2580,8 @@ void NeonEmitter::runVectorTypes(raw_ostream &OS) {
OS << "typedef __fp16 float16_t;\n";
OS << "#if defined(__aarch64__) || defined(__arm64ec__)\n";
+ OS << "typedef __MFloat8x8_t mfloat8x8_t;\n";
+ OS << "typedef __MFloat8x16_t mfloat8x16_t;\n";
--
@@ -2580,6 +2580,8 @@ void NeonEmitter::runVectorTypes(raw_ostream &OS) {
OS << "typedef __fp16 float16_t;\n";
OS << "#if defined(__aarch64__) || defined(__arm64ec__)\n";
+ OS << "typedef __MFloat8x8_t mfloat8x8_t;\n";
+ OS << "typedef __MFloat8x16_t mfloat8x16_t;\n";
--
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@@ -2960,6 +2969,12 @@ static void RenderFloatingPointOptions(const ToolChain
&TC, const Driver &D,
}
for (const Arg *A : Args) {
+auto CheckMathErrnoForVecLib =
+llvm::make_scope_exit([&, MathErrnoBeforeArg = MathErrno] {
+ if (NoMathErrnoWasImpliedB
@@ -2960,6 +2969,12 @@ static void RenderFloatingPointOptions(const ToolChain
&TC, const Driver &D,
}
for (const Arg *A : Args) {
+auto CheckMathErrnoForVecLib =
+llvm::make_scope_exit([&, MathErrnoBeforeArg = MathErrno] {
+ if (NoMathErrnoWasImpliedB
@@ -3125,6 +3140,13 @@ static void RenderFloatingPointOptions(const ToolChain
&TC, const Driver &D,
TrappingMathPresent = true;
FPExceptionBehavior = "strict";
break;
+case options::OPT_fveclib:
+ VecLibArg = A;
+ if (llvm::is_contained(VecLibIm
@@ -502,6 +502,10 @@ def err_sls_hardening_arm_not_supported : Error<
def warn_drv_large_data_threshold_invalid_code_model: Warning<
"'%0' only applies to medium and large code models">,
InGroup;
+def warn_drv_math_errno_reenabled_after_veclib: Warning<
+ "math errno re-en
@@ -36,16 +36,23 @@
/* Verify that the correct vector library is passed to LTO flags. */
// RUN: %clang -### --target=x86_64-unknown-linux-gnu -fveclib=LIBMVEC -flto
%s 2>&1 | FileCheck --check-prefix=CHECK-LTO-LIBMVEC %s
+// CHECK-LTO-LIBMVEC: "-fmath-errno"
// CHECK-LTO-LI
@@ -2580,6 +2580,8 @@ void NeonEmitter::runVectorTypes(raw_ostream &OS) {
OS << "typedef __fp16 float16_t;\n";
OS << "#if defined(__aarch64__) || defined(__arm64ec__)\n";
+ OS << "typedef __MFloat8x8_t mfloat8x8_t;\n";
+ OS << "typedef __MFloat8x16_t mfloat8x16_t;\n";
--
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https://github.com/paulwalker-arm commented:
I can be persuaded if there are good reasons for the `TypeSpec` side to wait,
but the the current placement of the typedefs looks wrong.
https://github.com/llvm/llvm-project/pull/99865
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@@ -36,16 +36,23 @@
/* Verify that the correct vector library is passed to LTO flags. */
// RUN: %clang -### --target=x86_64-unknown-linux-gnu -fveclib=LIBMVEC -flto
%s 2>&1 | FileCheck --check-prefix=CHECK-LTO-LIBMVEC %s
+// CHECK-LTO-LIBMVEC: "-fmath-errno"
// CHECK-LTO-LI
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@@ -3125,6 +3129,10 @@ static void RenderFloatingPointOptions(const ToolChain
&TC, const Driver &D,
TrappingMathPresent = true;
FPExceptionBehavior = "strict";
break;
+case options::OPT_fveclib:
+ if (llvm::is_contained(VecLibImpliesNoMathErrno, A->g
@@ -36,16 +36,23 @@
/* Verify that the correct vector library is passed to LTO flags. */
// RUN: %clang -### --target=x86_64-unknown-linux-gnu -fveclib=LIBMVEC -flto
%s 2>&1 | FileCheck --check-prefix=CHECK-LTO-LIBMVEC %s
+// CHECK-LTO-LIBMVEC: "-fmath-errno"
// CHECK-LTO-LI
@@ -97,6 +97,17 @@
SVE_TYPE(Name, Id, SingletonId)
#endif
+#ifndef AARCH64_VECTOR_TYPE
paulwalker-arm wrote:
I agree. Carol and I discussed this previously and I asked her to ignore the
obvious structural/naming issues and focus on adding the new types in
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@@ -4419,6 +4419,13 @@ QualType ASTContext::getScalableVectorType(QualType
EltTy, unsigned NumElts,
EltTySize == ElBits && NumElts == (NumEls * NF) && NumFields == 1) {
\
return SingletonId;
\
}
+#define
@@ -69,7 +69,7 @@
#ifndef SVE_VECTOR_TYPE_BFLOAT
#define SVE_VECTOR_TYPE_BFLOAT(Name, MangledName, Id, SingletonId, NumEls,
ElBits, NF) \
- SVE_VECTOR_TYPE_DETAILS(Name, MangledName, Id, SingletonId, NumEls, ElBits,
NF, false, false, true)
+ SVE_VECTOR_TYPE_DETAILS(Name, M
@@ -700,6 +701,9 @@ class TargetInfo : public TransferrableTargetInfo,
return HasBFloat16 || HasFullBFloat16;
}
+ /// Determine whether the _mfp8 type is supported on this target.
+ virtual bool hasArmMFloat8Type() const { return HasMFloat8; }
paulwalk
@@ -3437,8 +3445,8 @@ StringRef BuiltinType::getName(const PrintingPolicy
&Policy) const {
case Id: \
return #ExtType;
#include "clang/Basic/OpenCLExtensionTypes.def"
-#define SVE_TYPE(Name, Id, SingletonId) \
- case Id: \
+#define SVE_TYPE(Name, Id, SingletonId)
@@ -5828,6 +5832,7 @@ bool Parser::isKnownToBeTypeSpecifier(const Token &Tok)
const {
case tok::kw__ExtInt:
case tok::kw__BitInt:
case tok::kw___bf16:
+ case tok::kw___mfp8:
paulwalker-arm wrote:
Do you know why this and the similar changes are needed?
@@ -526,6 +526,11 @@ llvm::Type *CodeGenTypes::ConvertType(QualType T) {
}
case BuiltinType::SveCount:
return llvm::TargetExtType::get(getLLVMContext(), "aarch64.svcount");
+case BuiltinType::ArmMFloat8:
+ ResultType =
+ llvm::VectorType::get(l
@@ -1391,7 +1391,8 @@ void ASTContext::InitBuiltinTypes(const TargetInfo
&Target,
}
if (Target.hasAArch64SVETypes() ||
- (AuxTarget && AuxTarget->hasAArch64SVETypes())) {
+ (AuxTarget && AuxTarget->hasAArch64SVETypes()) ||
+ Target.hasArmMFloat8Type()) {
--
@@ -2218,6 +2219,11 @@ TypeInfo ASTContext::getTypeInfoImpl(const Type *T)
const {
Width = 0;
\
Align = 16;
\
break;
+#define AARCH64_SC
@@ -4302,6 +4308,7 @@ ASTContext::getBuiltinVectorTypeInfo(const BuiltinType
*Ty) const {
case BuiltinType::Id:
\
return {BoolTy, llvm::ElementCount::getScalable(NumEls), NF};
#define SVE_OPAQUE_TYPE(Name, MangledNa
@@ -476,7 +476,6 @@ llvm::Type *CodeGenTypes::ConvertType(QualType T) {
Context.getFloatTypeSemantics(T),
/* UseNativeHalf = */ false);
break;
-
paulwalker-arm wrote:
Unnecessary whi
@@ -87,6 +87,10 @@ class SVEType {
bool isDefault() const { return DefaultType; }
bool isFloat() const { return Float && !BFloat; }
bool isBFloat() const { return BFloat && !Float; }
paulwalker-arm wrote:
To be consistent I think these need updating to i
@@ -4354,12 +4353,16 @@ ASTContext::getBuiltinVectorTypeInfo(const BuiltinType
*Ty) const {
ElBits, NF)
\
case BuiltinType::Id:
\
return {BFloat16T
@@ -454,6 +458,8 @@ std::string SVEType::builtin_str() const {
else if (isBFloat()) {
assert(ElementBitwidth == 16 && "Not a valid BFloat.");
S += "y";
+ } else if (isMFloat()) {
+S += "m";
paulwalker-arm wrote:
Perhaps worth adding `assert(Elem
@@ -87,6 +87,10 @@ class SVEType {
bool isDefault() const { return DefaultType; }
bool isFloat() const { return Float && !BFloat; }
bool isBFloat() const { return BFloat && !Float; }
+ bool isMFloat() const {
+return MFloat && !BFloat && !Float;
+;
--
@@ -4339,7 +4339,6 @@ ASTContext::getBuiltinVectorTypeInfo(const BuiltinType
*Ty) const {
switch (Ty->getKind()) {
default:
llvm_unreachable("Unsupported builtin vector type");
-
paulwalker-arm wrote:
Please can we keep these blank lines. With all th
https://github.com/paulwalker-arm commented:
Not sure if there's enough support to update all of them but, but many of the
following should be extended to cover the new types:
clang/test/CodeGenCXX/aarch64-sve-vector-init.cpp
clang/test/CodeGenCXX/aarch64-mangle-sve-fixed-vectors.cpp
clang/test
@@ -69,6 +69,11 @@
#ifndef SVE_VECTOR_TYPE_BFLOAT
#define SVE_VECTOR_TYPE_BFLOAT(Name, MangledName, Id, SingletonId, NumEls,
ElBits, NF) \
+ SVE_VECTOR_TYPE_DETAILS(Name, MangledName, Id, SingletonId, NumEls, ElBits,
NF, true, false, true)
+#endif
+
+#ifndef SVE_VECTOR_TYPE
https://github.com/paulwalker-arm edited
https://github.com/llvm/llvm-project/pull/101644
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