bzEq wrote:
I am not going to pursue this PR, close it.
https://github.com/llvm/llvm-project/pull/86905
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bzEq wrote:
Address comment.
https://github.com/llvm/llvm-project/pull/117415
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>From f4e8c55a4dbe9092bcf5f61cca67359a779861bc Mon Sep 17 00:00:00 2001
From: Kai Luo
Date: Sat, 23 Nov 2024 13:14:27 +0800
Subject: [PATCH 1/2] [Driver] Pass `--no-cuda-version-check` to test
My local build, on De
https://github.com/bzEq edited https://github.com/llvm/llvm-project/pull/117415
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https://github.com/bzEq created https://github.com/llvm/llvm-project/pull/117415
My local build, on Debian GNU/Linux 12 (bookworm), complains
```
clang: error: GPU arch sm_20 is supported by CUDA versions between 7.0 and 8.0
(inclusive), but installation at /usr/lib/cuda is 11.8; use '--cuda-pat
@@ -80,6 +80,7 @@ class LLVM_LIBRARY_VISIBILITY PPCTargetInfo : public
TargetInfo {
bool IsISA3_0 = false;
bool IsISA3_1 = false;
bool HasQuadwordAtomics = false;
+ bool HasAIXShLibTLSModelHeuristic = false;
bzEq wrote:
Code in `PPCTargetLowering::Lowe
@@ -80,6 +80,7 @@ class LLVM_LIBRARY_VISIBILITY PPCTargetInfo : public
TargetInfo {
bool IsISA3_0 = false;
bool IsISA3_1 = false;
bool HasQuadwordAtomics = false;
+ bool HasAIXShLibTLSModelHeuristic = false;
bzEq wrote:
The variable defined here is onl
bzEq wrote:
> due to backward compatibility, it needs to be expanded into series of rlwimi
> in 32-bit environment
Why must be 'series of rlwimi'?
Why don't we just expand it following what ISA describes and let legalizer
generates code sequence under 32-bit mode?
```
n ← sh5 || sh0:4
r ← ROT
https://github.com/bzEq created https://github.com/llvm/llvm-project/pull/86905
This is to address https://github.com/llvm/llvm-project/issues/84703. However
this might not be a long-term solution in my view.
>From 99e76dbe0016332ed1d21edbf5297cd5189afe3d Mon Sep 17 00:00:00 2001
From: Kai Luo
@@ -329,6 +329,12 @@ def FeatureAIXLocalExecTLS :
"Produce a TOC-free local-exec TLS sequence for this
function "
"for 64-bit AIX">;
+def FeatureAIXSharedLibraryTLSModelHeuristic :
+ SubtargetFeature<"aix-shared-library-tls-model-heurist
@@ -3369,6 +3369,48 @@ SDValue
PPCTargetLowering::LowerGlobalTLSAddressAIX(SDValue Op,
bool Is64Bit = Subtarget.isPPC64();
bool HasAIXSmallLocalExecTLS = Subtarget.hasAIXSmallLocalExecTLS();
TLSModel::Model Model = getTargetMachine().getTLSModel(GV);
+ // Initialize heu
@@ -3369,6 +3369,48 @@ SDValue
PPCTargetLowering::LowerGlobalTLSAddressAIX(SDValue Op,
bool Is64Bit = Subtarget.isPPC64();
bool HasAIXSmallLocalExecTLS = Subtarget.hasAIXSmallLocalExecTLS();
TLSModel::Model Model = getTargetMachine().getTLSModel(GV);
+ // Initialize heu
@@ -80,6 +80,7 @@ class LLVM_LIBRARY_VISIBILITY PPCTargetInfo : public
TargetInfo {
bool IsISA3_0 = false;
bool IsISA3_1 = false;
bool HasQuadwordAtomics = false;
+ bool HasAIXShLibTLSModelHeuristic = false;
bzEq wrote:
This looks redundant. Frontend d
@@ -14428,15 +14431,52 @@ SDValue PPCTargetLowering::combineSetCC(SDNode *N,
// x != 0-y --> x+y != 0
if (RHS.getOpcode() == ISD::SUB && isNullConstant(RHS.getOperand(0)) &&
RHS.hasOneUse()) {
- SDLoc DL(N);
- SelectionDAG &DAG = DCI.DAG;
- EVT VT
@@ -14428,15 +14431,52 @@ SDValue PPCTargetLowering::combineSetCC(SDNode *N,
// x != 0-y --> x+y != 0
if (RHS.getOpcode() == ISD::SUB && isNullConstant(RHS.getOperand(0)) &&
RHS.hasOneUse()) {
- SDLoc DL(N);
- SelectionDAG &DAG = DCI.DAG;
- EVT VT
@@ -14428,15 +14431,52 @@ SDValue PPCTargetLowering::combineSetCC(SDNode *N,
// x != 0-y --> x+y != 0
if (RHS.getOpcode() == ISD::SUB && isNullConstant(RHS.getOperand(0)) &&
RHS.hasOneUse()) {
- SDLoc DL(N);
- SelectionDAG &DAG = DCI.DAG;
- EVT VT
bzEq wrote:
Please provide more description in PR summary.
https://github.com/llvm/llvm-project/pull/66978
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bzEq wrote:
Though I do see some codegen improvement, I don't think we should check uses
inside `getValueBits`, since `getValueBits` is for analysis and is gathering as
much information as it can. Can you post your motivation code?
https://github.com/llvm/llvm-project/pull/66040
__
@@ -288,9 +288,9 @@ def SPEFSCR: SPR<512, "spefscr">, DwarfRegNum<[612, 112]>;
def XER: SPR<1, "xer">, DwarfRegNum<[76]>;
-// Carry bit. In the architecture this is really bit 0 of the XER register
-// (which really is SPR register 1); this is the only bit interesting to a
@@ -782,6 +782,8 @@ ArrayRef PPCTargetInfo::getGCCRegNames()
const {
const TargetInfo::GCCRegAlias PPCTargetInfo::GCCRegAliases[] = {
// While some of these aliases do map to different registers
// they still share the same register name.
+// Strictly speaking, "ca
@@ -288,9 +288,9 @@ def SPEFSCR: SPR<512, "spefscr">, DwarfRegNum<[612, 112]>;
def XER: SPR<1, "xer">, DwarfRegNum<[76]>;
-// Carry bit. In the architecture this is really bit 0 of the XER register
-// (which really is SPR register 1); this is the only bit interesting to a
https://github.com/bzEq updated https://github.com/llvm/llvm-project/pull/77557
>From e1caee46dc81e59b8eab0379e200ca2a709801c3 Mon Sep 17 00:00:00 2001
From: Kai Luo
Date: Wed, 10 Jan 2024 05:29:22 +
Subject: [PATCH 1/5] Alias
---
clang/lib/Basic/Targets/PPC.cpp | 2 +-
1 file changed, 1 i
@@ -0,0 +1,14 @@
+// REQUIRES: powerpc-registered-target
+// RUN: %clang -target powerpc64le -c %s -mllvm -stop-after=finalize-isel -o -
| \
+// RUN: FileCheck %s
+// RUN: %clang -target powerpc64 -c %s -mllvm -stop-after=finalize-isel -o - |
\
+// RUN: FileCheck %s
bzEq wrote:
Add test for backend and adjust comment of `CARRY`.
https://github.com/llvm/llvm-project/pull/77557
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>From e1caee46dc81e59b8eab0379e200ca2a709801c3 Mon Sep 17 00:00:00 2001
From: Kai Luo
Date: Wed, 10 Jan 2024 05:29:22 +
Subject: [PATCH 1/4] Alias
---
clang/lib/Basic/Targets/PPC.cpp | 2 +-
1 file changed, 1 i
@@ -0,0 +1,14 @@
+// REQUIRES: powerpc-registered-target
+// RUN: %clang -target powerpc64le -c %s -mllvm -stop-after=finalize-isel -o -
| \
+// RUN: FileCheck %s
+// RUN: %clang -target powerpc64 -c %s -mllvm -stop-after=finalize-isel -o - |
\
+// RUN: FileCheck %s
@@ -782,6 +782,8 @@ ArrayRef PPCTargetInfo::getGCCRegNames()
const {
const TargetInfo::GCCRegAlias PPCTargetInfo::GCCRegAliases[] = {
// While some of these aliases do map to different registers
// they still share the same register name.
+// Strictly speaking, "ca
https://github.com/bzEq updated https://github.com/llvm/llvm-project/pull/77557
>From e1caee46dc81e59b8eab0379e200ca2a709801c3 Mon Sep 17 00:00:00 2001
From: Kai Luo
Date: Wed, 10 Jan 2024 05:29:22 +
Subject: [PATCH 1/3] Alias
---
clang/lib/Basic/Targets/PPC.cpp | 2 +-
1 file changed, 1 i
https://github.com/bzEq created https://github.com/llvm/llvm-project/pull/77557
`ca` is not accepted in clobber list of inline assembly right now. Make `ca`
aliased to `xer`, so it can be accepted in clobber list.
Fixes #77549.
>From e1caee46dc81e59b8eab0379e200ca2a709801c3 Mon Sep 17 00:00:00
Thorsten =?utf-8?q?Schütt?= ,
Thorsten =?utf-8?q?Schütt?= ,
Thorsten =?utf-8?q?Schütt?=
Message-ID:
In-Reply-To:
bzEq wrote:
It's also exhausting memory when `llvm-lit
llvm-project/llvm/test/CodeGen/AMDGPU/llvm.exp2.ll`.
See https://lab.llvm.org/buildbot/#/builders/249/builds/13786.
https://
https://github.com/bzEq created https://github.com/llvm/llvm-project/pull/76025
This is copied from https://reviews.llvm.org/D109139.
`__STDC_NO_ATOMICS__` is predefined to indicate clang on AIX doesn't support
`_Atomic` and not shipped with `stdatomic.h` yet. Actually `_Atomic` is already
sup
@@ -282,45 +282,57 @@ static void auxSymMapping(IO &IO,
XCOFFYAML::SectAuxEntForStat &AuxSym) {
void MappingTraits>::mapping(
IO &IO, std::unique_ptr &AuxSym) {
- assert(!IO.outputting() && "We don't dump aux symbols currently.");
+
+ auto ResetAuxSym = [&](auto *AuxEnt
@@ -282,45 +282,57 @@ static void auxSymMapping(IO &IO,
XCOFFYAML::SectAuxEntForStat &AuxSym) {
void MappingTraits>::mapping(
IO &IO, std::unique_ptr &AuxSym) {
- assert(!IO.outputting() && "We don't dump aux symbols currently.");
+
+ auto ResetAuxSym = [&](auto *AuxEnt
@@ -14428,15 +14431,53 @@ SDValue PPCTargetLowering::combineSetCC(SDNode *N,
// x != 0-y --> x+y != 0
if (RHS.getOpcode() == ISD::SUB && isNullConstant(RHS.getOperand(0)) &&
RHS.hasOneUse()) {
- SDLoc DL(N);
- SelectionDAG &DAG = DCI.DAG;
- EVT VT
https://github.com/bzEq edited https://github.com/llvm/llvm-project/pull/66978
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@@ -14428,15 +14431,53 @@ SDValue PPCTargetLowering::combineSetCC(SDNode *N,
// x != 0-y --> x+y != 0
if (RHS.getOpcode() == ISD::SUB && isNullConstant(RHS.getOperand(0)) &&
RHS.hasOneUse()) {
- SDLoc DL(N);
- SelectionDAG &DAG = DCI.DAG;
- EVT VT
https://github.com/bzEq approved this pull request.
LGTM.
https://github.com/llvm/llvm-project/pull/67298
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@@ -52,7 +52,7 @@ bool
PPCTargetInfo::handleTargetFeatures(std::vector &Features,
HasDirectMove = true;
} else if (Feature == "+htm") {
HasHTM = true;
-} else if (Feature == "+float128") {
+} else if (Feature == "+float128" && !getTriple().isOSAIX()) {
@@ -52,7 +52,7 @@ bool
PPCTargetInfo::handleTargetFeatures(std::vector &Features,
HasDirectMove = true;
} else if (Feature == "+htm") {
HasHTM = true;
-} else if (Feature == "+float128") {
+} else if (Feature == "+float128" && !getTriple().isOSAIX()) {
https://github.com/bzEq deleted https://github.com/llvm/llvm-project/pull/67298
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@@ -52,7 +52,7 @@ bool
PPCTargetInfo::handleTargetFeatures(std::vector &Features,
HasDirectMove = true;
} else if (Feature == "+htm") {
HasHTM = true;
-} else if (Feature == "+float128") {
+} else if (Feature == "+float128" && !getTriple().isOSAIX()) {
https://github.com/bzEq updated https://github.com/llvm/llvm-project/pull/70480
>From 99ec6e055dd32a86bf6d589a6895658dcbe1d7bd Mon Sep 17 00:00:00 2001
From: Yeoul Na
Date: Fri, 27 Oct 2023 08:34:37 -0700
Subject: [PATCH 1/6] [Driver][BoundsSafety] Add -fbounds-safety-experimental
flag
-fbound
bzEq wrote:
> Also, is it intentional that we combined the patch to enable local-dynamic in
> clang within this patch?
Yes. For github's nature, we are unable to set parent PR in llvm-project repo,
so clang part is included in this PR.
https://github.com/llvm/llvm-project/pull/66316
_
https://github.com/bzEq deleted https://github.com/llvm/llvm-project/pull/66316
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@@ -3412,13 +3416,23 @@ SDValue
PPCTargetLowering::LowerGlobalTLSAddressAIX(SDValue Op,
return DAG.getNode(PPCISD::ADD_TLS, dl, PtrVT, TLSReg, VariableOffset);
}
- // Only Local-Exec, Initial-Exec and General-Dynamic TLS models are currently
- // supported models. If
Author: Kai Luo
Date: 2023-09-13T05:24:20Z
New Revision: ca8d2533c79ccfbcb2de4090f0d48914a60b0a3d
URL:
https://github.com/llvm/llvm-project/commit/ca8d2533c79ccfbcb2de4090f0d48914a60b0a3d
DIFF:
https://github.com/llvm/llvm-project/commit/ca8d2533c79ccfbcb2de4090f0d48914a60b0a3d.diff
LOG: [clan
Author: Kai Luo
Date: 2023-08-24T07:56:43Z
New Revision: 09ccc5563ebe70be2b5a5421df43cd5720ba1f5b
URL:
https://github.com/llvm/llvm-project/commit/09ccc5563ebe70be2b5a5421df43cd5720ba1f5b
DIFF:
https://github.com/llvm/llvm-project/commit/09ccc5563ebe70be2b5a5421df43cd5720ba1f5b.diff
LOG: Fix [
Author: Kai Luo
Date: 2023-08-24T02:10:13Z
New Revision: 1ceaec3e81044d8a671b28d1f556045cf7fe6ef0
URL:
https://github.com/llvm/llvm-project/commit/1ceaec3e81044d8a671b28d1f556045cf7fe6ef0
DIFF:
https://github.com/llvm/llvm-project/commit/1ceaec3e81044d8a671b28d1f556045cf7fe6ef0.diff
LOG: [Powe
Author: Kai Luo
Date: 2023-08-23T01:58:36Z
New Revision: 6b6ea93125bd834cae22149e18b742d498dc79a3
URL:
https://github.com/llvm/llvm-project/commit/6b6ea93125bd834cae22149e18b742d498dc79a3
DIFF:
https://github.com/llvm/llvm-project/commit/6b6ea93125bd834cae22149e18b742d498dc79a3.diff
LOG: [Powe
Author: Kai Luo
Date: 2023-08-22T04:14:34Z
New Revision: be1516d46b1c9ad873d1b30b3494c3a3d0d8e02b
URL:
https://github.com/llvm/llvm-project/commit/be1516d46b1c9ad873d1b30b3494c3a3d0d8e02b
DIFF:
https://github.com/llvm/llvm-project/commit/be1516d46b1c9ad873d1b30b3494c3a3d0d8e02b.diff
LOG: [Powe
Author: Kai Luo
Date: 2023-02-10T04:58:20Z
New Revision: 2db83b1b311bae3d14067970edf15c6a1d37
URL:
https://github.com/llvm/llvm-project/commit/2db83b1b311bae3d14067970edf15c6a1d37
DIFF:
https://github.com/llvm/llvm-project/commit/2db83b1b311bae3d14067970edf15c6a1d37.diff
LOG: [CMak
Author: Kai Luo
Date: 2022-10-19T07:26:08Z
New Revision: 2e73129483c4be78d32f4bbe3f9a3130d9fc83b7
URL:
https://github.com/llvm/llvm-project/commit/2e73129483c4be78d32f4bbe3f9a3130d9fc83b7
DIFF:
https://github.com/llvm/llvm-project/commit/2e73129483c4be78d32f4bbe3f9a3130d9fc83b7.diff
LOG: [incl
Author: Kai Luo
Date: 2022-10-13T12:03:55+08:00
New Revision: e231a580139a50aff639296c4b95a65e7d89cf1e
URL:
https://github.com/llvm/llvm-project/commit/e231a580139a50aff639296c4b95a65e7d89cf1e
DIFF:
https://github.com/llvm/llvm-project/commit/e231a580139a50aff639296c4b95a65e7d89cf1e.diff
LOG:
Author: Kai Luo
Date: 2022-07-27T01:56:25Z
New Revision: 1cbaf681b0f1e7257e7e2a63d290a20216668f17
URL:
https://github.com/llvm/llvm-project/commit/1cbaf681b0f1e7257e7e2a63d290a20216668f17
DIFF:
https://github.com/llvm/llvm-project/commit/1cbaf681b0f1e7257e7e2a63d290a20216668f17.diff
LOG: [clan
Author: Kai Luo
Date: 2022-04-08T23:25:56Z
New Revision: 549e118e93c666914a1045fde38a2cac33e1e445
URL:
https://github.com/llvm/llvm-project/commit/549e118e93c666914a1045fde38a2cac33e1e445
DIFF:
https://github.com/llvm/llvm-project/commit/549e118e93c666914a1045fde38a2cac33e1e445.diff
LOG: [Powe
Author: Kai Luo
Date: 2022-03-24T14:06:45+08:00
New Revision: b8388fa319bc68bee396a14857331fb2e7b815bd
URL:
https://github.com/llvm/llvm-project/commit/b8388fa319bc68bee396a14857331fb2e7b815bd
DIFF:
https://github.com/llvm/llvm-project/commit/b8388fa319bc68bee396a14857331fb2e7b815bd.diff
LOG:
Author: Kai Luo
Date: 2022-03-18T13:22:28+08:00
New Revision: 9247145fbae7c4273acd6b8f3b331716ca80bf18
URL:
https://github.com/llvm/llvm-project/commit/9247145fbae7c4273acd6b8f3b331716ca80bf18
DIFF:
https://github.com/llvm/llvm-project/commit/9247145fbae7c4273acd6b8f3b331716ca80bf18.diff
LOG:
Author: Kai Luo
Date: 2021-11-11T15:51:19Z
New Revision: 72362736c380699a79ba43a1411baeab76205c39
URL:
https://github.com/llvm/llvm-project/commit/72362736c380699a79ba43a1411baeab76205c39
DIFF:
https://github.com/llvm/llvm-project/commit/72362736c380699a79ba43a1411baeab76205c39.diff
LOG: [AIX]
Author: Kai Luo
Date: 2021-10-28T02:18:43Z
New Revision: 6ea2431d3f109aefa31cd4d520cc234a5aa5484a
URL:
https://github.com/llvm/llvm-project/commit/6ea2431d3f109aefa31cd4d520cc234a5aa5484a
DIFF:
https://github.com/llvm/llvm-project/commit/6ea2431d3f109aefa31cd4d520cc234a5aa5484a.diff
LOG: [clan
Author: Kai Luo
Date: 2021-07-29T14:49:26Z
New Revision: e4902e69e99d07d6d311425d87d4c1d075b72bf8
URL:
https://github.com/llvm/llvm-project/commit/e4902e69e99d07d6d311425d87d4c1d075b72bf8
DIFF:
https://github.com/llvm/llvm-project/commit/e4902e69e99d07d6d311425d87d4c1d075b72bf8.diff
LOG: [Powe
Author: Kai Luo
Date: 2021-07-23T01:16:02Z
New Revision: e4ed93cb25acc624a1d32e77d2c63c8c25fddbae
URL:
https://github.com/llvm/llvm-project/commit/e4ed93cb25acc624a1d32e77d2c63c8c25fddbae
DIFF:
https://github.com/llvm/llvm-project/commit/e4ed93cb25acc624a1d32e77d2c63c8c25fddbae.diff
LOG: [Powe
Author: Kai Luo
Date: 2020-07-05T03:43:56Z
New Revision: 68e07da3e5d5175e24caa309e2b13cb65c8c
URL:
https://github.com/llvm/llvm-project/commit/68e07da3e5d5175e24caa309e2b13cb65c8c
DIFF:
https://github.com/llvm/llvm-project/commit/68e07da3e5d5175e24caa309e2b13cb65c8c.diff
LOG: [clan
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