@@ -338,6 +382,87 @@ static Error runSPIRVCodeGen(StringRef File, const ArgList
&Args,
return Error::success();
}
+/// Run AOT compilation for Intel CPU.
+/// Calls opencl-aot tool to generate device code for Intel CPU backend.
jzc wrote:
Changed to `Calls
https://github.com/jzc edited https://github.com/llvm/llvm-project/pull/133194
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@@ -440,9 +570,15 @@ int main(int argc, char **argv) {
DryRun = Args.hasArg(OPT_dry_run);
SaveTemps = Args.hasArg(OPT_save_temps);
- OutputFile = "a.out";
- if (Args.hasArg(OPT_o))
-OutputFile = Args.getLastArgValue(OPT_o);
+ IsAOTCompileNeeded = IsIntelOffloadArch(
https://github.com/jzc updated https://github.com/llvm/llvm-project/pull/133194
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body {
background-color: #f6f8fa;
color: #24292e;
font-family: -apple-system,BlinkMacSystemFont,Segoe
UI,Helvetica,Arial,sans-serif,
https://github.com/jzc updated https://github.com/llvm/llvm-project/pull/138158
>From f1b0e2cbe8229ba00956e0eac58f97d71995b0dd Mon Sep 17 00:00:00 2001
From: "Cai, Justin"
Date: Mon, 14 Apr 2025 21:30:39 +
Subject: [PATCH 1/2] [Clang][SYCL] Add initial set of Intel OffloadArch values
---
c
https://github.com/jzc created https://github.com/llvm/llvm-project/pull/138158
Following #137070, this PR adds an initial set of Intel `OffloadArch` values
with corresponding predicates that will be used in SYCL offloading. More Intel
architectures will be added in a future PR.
>From f1b0e2cb
https://github.com/jzc updated https://github.com/llvm/llvm-project/pull/137070
>From 924f54246910cad42f97efe1bc3d3bdfec039ecb Mon Sep 17 00:00:00 2001
From: "Cai, Justin"
Date: Mon, 14 Apr 2025 21:30:39 +
Subject: [PATCH 1/4] [Clang] Move OffloadArch enum to a generic location and
add init
https://github.com/jzc updated https://github.com/llvm/llvm-project/pull/137070
>From 924f54246910cad42f97efe1bc3d3bdfec039ecb Mon Sep 17 00:00:00 2001
From: "Cai, Justin"
Date: Mon, 14 Apr 2025 21:30:39 +
Subject: [PATCH 1/3] [Clang] Move OffloadArch enum to a generic location and
add init
https://github.com/jzc edited https://github.com/llvm/llvm-project/pull/137070
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https://github.com/jzc updated https://github.com/llvm/llvm-project/pull/137070
>From 924f54246910cad42f97efe1bc3d3bdfec039ecb Mon Sep 17 00:00:00 2001
From: "Cai, Justin"
Date: Mon, 14 Apr 2025 21:30:39 +
Subject: [PATCH 1/2] [Clang] Move OffloadArch enum to a generic location and
add init
https://github.com/jzc edited https://github.com/llvm/llvm-project/pull/137070
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None
>From 924f54246910cad42f97efe1bc3d3bdfec039ecb Mon Sep 17 00:00:00 2001
From: "Cai, Justin"
Date: Mon, 14 Apr 2025 21:30:39 +
Subject: [PATCH] [Clang] Move OffloadArch enum to a generic location and add
in
https://github.com/jzc deleted https://github.com/llvm/llvm-project/pull/136697
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@@ -159,6 +160,107 @@ namespace intel {
/// the Intel runtime offload plugin.
Error containerizeOpenMPSPIRVImage(std::unique_ptr &Binary);
} // namespace intel
+
+namespace sycl {
+class PropertySetRegistry;
+
+// A property value. It can be either a 32-bit unsigned integer or
jzc wrote:
For now, I've placed the class in `Frontend/Offloading/Utility.h`. If we get
`Frontend/Offloading/SYCL` later on then I then that would be the most
appropriate place to put it.
https://github.com/llvm/llvm-project/pull/136697
_
https://github.com/jzc created https://github.com/llvm/llvm-project/pull/136697
None
>From f5388e43a3ace6429ad911aebe2a3599858abf8f Mon Sep 17 00:00:00 2001
From: "Cai, Justin"
Date: Tue, 22 Apr 2025 06:34:45 -0700
Subject: [PATCH] [SYCL] Add SYCL property set registry class
---
.../clang-syc
https://github.com/jzc updated https://github.com/llvm/llvm-project/pull/133194
>From 8f22fbe1f6272beec61e62bfae72832d75b4f25b Mon Sep 17 00:00:00 2001
From: "Cai, Justin"
Date: Fri, 14 Feb 2025 21:16:27 +
Subject: [PATCH 1/3] [SYCL] Add support AOT compilation support for Intel GPUs
in cla
https://github.com/jzc updated https://github.com/llvm/llvm-project/pull/133194
>From 8f22fbe1f6272beec61e62bfae72832d75b4f25b Mon Sep 17 00:00:00 2001
From: "Cai, Justin"
Date: Fri, 14 Feb 2025 21:16:27 +
Subject: [PATCH 1/5] [SYCL] Add support AOT compilation support for Intel GPUs
in cla
https://github.com/jzc updated https://github.com/llvm/llvm-project/pull/133194
>From 8f22fbe1f6272beec61e62bfae72832d75b4f25b Mon Sep 17 00:00:00 2001
From: "Cai, Justin"
Date: Fri, 14 Feb 2025 21:16:27 +
Subject: [PATCH 1/6] [SYCL] Add support AOT compilation support for Intel GPUs
in cla
@@ -0,0 +1,131 @@
+//===--- SYCL.h -*- C++
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Ap
@@ -0,0 +1,131 @@
+//===--- SYCL.h -*- C++
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Ap
@@ -0,0 +1,131 @@
+//===--- SYCL.h -*- C++
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Ap
https://github.com/jzc edited https://github.com/llvm/llvm-project/pull/133194
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https://github.com/jzc created https://github.com/llvm/llvm-project/pull/133194
This PR adds support for AOT compilation for Intel CPUs and GPUs in
clang-sycl-linker. When no `-arch` is passed to `clang-sycl-linker`, the output
of the tool will be the resulting linked SPIR-V bytecode. If the `-
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