jthackray wrote:
I've opened #132495 to remove quite a lot of superfluous `#include`s, which
might improve compile time.
https://github.com/llvm/llvm-project/pull/132252
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@@ -0,0 +1,105 @@
+//===-- CGBuiltin.h - Emit LLVM Code for builtins
-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Ap
https://github.com/jthackray approved this pull request.
LGTM
https://github.com/llvm/llvm-project/pull/134368
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Thanks for this fix. LGTM.
https://github.com/llvm/llvm-project/pull/133619
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@@ -289,6 +289,105 @@ multiclass ZAFPOuterProd {
defm SVMOPA : ZAFPOuterProd<"mopa">;
defm SVMOPS : ZAFPOuterProd<"mops">;
+
+// SME2 - FMOP4A, FMOP4S, BFMOP4A, BFMOP4S
+
+multiclass MOP4
checks>
@@ -289,6 +289,105 @@ multiclass ZAFPOuterProd {
defm SVMOPA : ZAFPOuterProd<"mopa">;
defm SVMOPS : ZAFPOuterProd<"mops">;
+
+// SME2 - FMOP4A, FMOP4S, BFMOP4A, BFMOP4S
+
+multiclass MOP4
checks>
@@ -0,0 +1,304 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+
+// REQUIRES: aarch64-registered-target
+// RUN: %clang_cc1 -triple aarch64 -target-feature +bf16 -target-feature
+sme-mop4 -target-feature +sme-f16f16 -target-feature +sme-i16i64
https://github.com/jthackray approved this pull request.
Thanks for creating this PR, LGTM (I wasn't able to do it earlier as one of my
kids was ill, so away from laptop)
https://github.com/llvm/llvm-project/pull/133251
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cf
jthackray wrote:
> How'd you manage to find the right ones? IMO we should be using
> include-what-you-use on these to make sure we get it right (if you have
> already, disregard this).
Yes, I used iwyu.
> Also, can you share before-split/after-split/after-this build time
> benchmarks? Does
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LGTM.
https://github.com/llvm/llvm-project/pull/132060
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jthackray wrote:
> LGTM. Does this actually fix the build time regression from the previous
> patch?
Apologies for the delay; I wasn't working yesterday.
Using a Graviton c8g.8xlarge instance, with a `ninja` build, I don't see a
large build time regression. However, this is compiling in paral
jthackray wrote:
@jurahul
> I see that some of the HLSL builtin code (like `EmitHLSLBuiltinExpr`) ended
> up in AMDGPU.cpp. Does that seem misplaced?
@jurahul Yes, apologies. Will write another PR to move it.
https://github.com/llvm/llvm-project/pull/132252
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https://github.com/jthackray approved this pull request.
LGTM. (apologies for delay; in hospital in Oxford visiting my Dad, but he's
gone back to sleep now)
https://github.com/llvm/llvm-project/pull/132368
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@@ -0,0 +1,107 @@
+//===-- CGBuiltin.h - Emit LLVM Code for builtins
-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Ap
https://github.com/jthackray created
https://github.com/llvm/llvm-project/pull/132495
None
>From 7f1f78ad0c39a8bd1b6c8e4cc7001f6282167d3c Mon Sep 17 00:00:00 2001
From: Jonathan Thackray
Date: Fri, 21 Mar 2025 23:56:42 +
Subject: [PATCH] [NFC][clang] Remove superfluous header files after r
https://github.com/jthackray updated
https://github.com/llvm/llvm-project/pull/132495
>From a55f760ad74fb22ad39c83c5787a9da14224d457 Mon Sep 17 00:00:00 2001
From: Jonathan Thackray
Date: Fri, 21 Mar 2025 23:56:42 +
Subject: [PATCH] [NFC][clang] Remove superfluous header files after refacto
https://github.com/jthackray edited
https://github.com/llvm/llvm-project/pull/132495
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jthackray wrote:
> I'd say you can merge it once CI is green.
Thanks @jhuber6.
CI is green. clang-format isn't, but running clang-format breaks some of the
AArch64 tests.
I'll wait another few hours, just in case there are more comments, and merge
later today if not.
https://github.com/llvm
jthackray wrote:
So far I've got approvals, positive comments or thumbs-up emojis from:
@jhuber6, @erichkeane, @Sirraide, @vmustya, @MacDue, @arichardson.
@s-barannikov and @davemgreen - are you okay if I merge this soon, since
`CGBuiltin.cpp` seems to get updated every few days.
I've had to
@@ -0,0 +1,8040 @@
+//===-- AArch64.cpp - Emit LLVM Code for builtins
-===//
jthackray wrote:
Thanks, fixed.
https://github.com/llvm/llvm-project/pull/132252
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@@ -0,0 +1,105 @@
+//===-- CGBuiltin.h - Emit LLVM Code for builtins
-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Ap
@@ -61,6 +61,16 @@ add_clang_library(clangCodeGen
CGAtomic.cpp
CGBlocks.cpp
CGBuiltin.cpp
+ TargetBuiltins/AArch64.cpp
jthackray wrote:
Done.
https://github.com/llvm/llvm-project/pull/132252
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@@ -0,0 +1,8530 @@
+//===-- AArch64.cpp - Emit LLVM Code for builtins
-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: A
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jthackray wrote:
> The timing of this is sort of unfortunate with #132252; the merge conflict
> there is going to be very painful. @jthackray , thoughts?
@efriedma-quic I think I can update my diff after this is merged; yes, might
take a while to resolve the diffs.
https://github.com/llvm/llv
jthackray wrote:
> This makes a lot of sense to me, just wondering why you chose
> `clang/lib/CodeGen/BuiltinTargets/` rather than
> `clang/lib/CodeGen/TargetBuiltins/`? The former shounds like it contains the
> list of all builtin targets, rather than the codegen for target-specific
> builti
jthackray wrote:
> Seems something with AArch64 has made the CI unhappy as well.
Thanks. It appears `clang-format` breaks some of the fragile `#define`s around
`NEONMAP0` and similar. If I revert the `clang-format`, it passes.
https://github.com/llvm/llvm-project/pull/132252
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LGTM.
https://github.com/llvm/llvm-project/pull/132167
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@@ -85,6 +85,9 @@ Changes to the AMDGPU Backend
Changes to the ARM Backend
--
+* The `+nosimd` attribute is now fully supported. Previously, this had no
effect when being used with
+AArch32 targets, however will now disable NEON instructions being gene
@@ -85,6 +85,9 @@ Changes to the AMDGPU Backend
Changes to the ARM Backend
--
+* The `+nosimd` attribute is now fully supported. Previously, this had no
effect when being used with
+AArch32 targets, however will now disable NEON instructions being gene
https://github.com/jthackray approved this pull request.
LGTM
https://github.com/llvm/llvm-project/pull/128854
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jthackray wrote:
typo in commit message: s/emable/enable/
https://github.com/llvm/llvm-project/pull/130623
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Thanks for the fixes. LGTM now.
https://github.com/llvm/llvm-project/pull/130623
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@@ -257,6 +266,17 @@ class SME2_Tile_Movaz_Pat(name # _PSEUDO) $tile, $base, $offset)>;
+class SME2_ZA_Tile_TwoVec_Pat
+: Pat<(intrinsic imm_ty:$tile, vt:$Zn, vt:$Zm),
+ (!cast(name # _PSEUDO) $tile, $Zn, $Zm)>;
+
+class SME2_ZA_Tile_Vec_Multi_Pat
j
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@@ -3064,6 +3064,76 @@ let TargetPrefix = "aarch64" in {
def int_aarch64_sme_usmopa_wide : SME_OuterProduct_Intrinsic;
def int_aarch64_sme_usmops_wide : SME_OuterProduct_Intrinsic;
+ class SME_OuterProduct_QuaterTile_Single
+ : DefaultAttrsIntrinsic<[],
+ [l
@@ -600,35 +624,65 @@ class sme_quarter_outer_product_i16_i32{
+multiclass sme_quarter_outer_product_i8_i32{
def _MZZ_BToS : sme_quarter_outer_product_i8_i32<{zn_u, 0}, {zm_u, 0},
subtr,
-ZPR8Mul2_Lo,
ZPR8Mul2_Hi, mnem
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@@ -600,35 +624,65 @@ class sme_quarter_outer_product_i16_i32{
+multiclass sme_quarter_outer_product_i8_i32{
jthackray wrote:
Add `// Single vectors` similar to lower down in the file.
https://github.com/llvm/llvm-project/pull/128854
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@@ -3064,6 +3064,76 @@ let TargetPrefix = "aarch64" in {
def int_aarch64_sme_usmopa_wide : SME_OuterProduct_Intrinsic;
def int_aarch64_sme_usmops_wide : SME_OuterProduct_Intrinsic;
+ class SME_OuterProduct_QuaterTile_Single
jthackray wrote:
nit: I think
https://github.com/jthackray approved this pull request.
LGTM. Glad to see the "utterly horrific" code gone :)
https://github.com/llvm/llvm-project/pull/127043
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LGTM
https://github.com/llvm/llvm-project/pull/125097
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LGTM
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LGTM
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LGTM
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https://github.com/jthackray approved this pull request.
Phew, massive diff, LGTM.
https://github.com/llvm/llvm-project/pull/123615
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LGTM
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LGTM
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Déjà vu, LGTM.
https://github.com/llvm/llvm-project/pull/123614
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LGTM
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LGTM
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@@ -2280,15 +2280,15 @@ let SVETargetGuard = "sve2p1", SMETargetGuard = "sme2"
in {
let SVETargetGuard = "sve2p1", SMETargetGuard = InvalidMode in {
// ZIPQ1, ZIPQ2, UZPQ1, UZPQ2
- def SVZIPQ1 : SInst<"svzipq1[_{d}]", "ddd", "cUcsUsiUilUlbhfd", MergeNone,
"aarch64_sve_zip
https://github.com/jthackray updated
https://github.com/llvm/llvm-project/pull/123585
>From 7e8fd043297335e28da41d28bf9ac8cc7fc5ab32 Mon Sep 17 00:00:00 2001
From: Jonathan Thackray
Date: Fri, 17 Jan 2025 17:09:22 +
Subject: [PATCH 1/2] [AArch64] Update SVE untyped intrinsics to have FP8
v
https://github.com/jthackray created
https://github.com/llvm/llvm-project/pull/123585
Update the following intrinsics to have FP8 variants:
``` c
svuint8_t svdup_laneq[_u8](svuint8_t zn, uint64_t imm_idx);
svuint8_t svextq[_u8](svuint8_t zdn, svuint8_t zm, uint64_t imm);
svint8_t svtblq[_s8](svi
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LGTM
https://github.com/llvm/llvm-project/pull/123056
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LGTM
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@@ -7429,6 +7429,11 @@ class Sema final : public SemaBase {
/// the perspective of SVE bitcasts.
bool isValidSveBitcast(QualType srcType, QualType destType);
+ /// Check for bitcast beween a regular vector type and builtin Neon vector
jthackray wrote:
ty
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@@ -1045,6 +1045,9 @@ X86 Support
Arm and AArch64 Support
^^^
+- Support for SVE2.1 and SME2.1 using the Arm C Language Extensions (ACLE) is
jthackray wrote:
Done.
https://github.com/llvm/llvm-project/pull/122705
_
https://github.com/jthackray updated
https://github.com/llvm/llvm-project/pull/122705
>From 4206edb54ccad4012970ec1b14748f81ccf5b01c Mon Sep 17 00:00:00 2001
From: Jonathan Thackray
Date: Mon, 13 Jan 2025 13:23:20 +
Subject: [PATCH 1/2] [NFC][AArch64] Add relnote saying SVE2.1 and SME2.1 no
https://github.com/jthackray created
https://github.com/llvm/llvm-project/pull/122705
None
>From 4206edb54ccad4012970ec1b14748f81ccf5b01c Mon Sep 17 00:00:00 2001
From: Jonathan Thackray
Date: Mon, 13 Jan 2025 13:23:20 +
Subject: [PATCH] [NFC][AArch64] Add relnote saying SVE2.1 and SME2.1
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LGTM
https://github.com/llvm/llvm-project/pull/121802
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LGTM
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LGTM
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LGTM
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>From 519bcca2359ee9c89b12bac6e58eb955c79cd7bc Mon Sep 17 00:00:00 2001
From: Jonathan Thackray
Date: Fri, 20 Dec 2024 14:50:37 +
Subject: [PATCH 1/2] [AArch64] Enable FEAT_SVE2p1 by default for Armv9.4-A
jthackray wrote:
> Actually this is being added as a mandatory dependency of 9.4, should it not
> be added as one of the default features instead?
Good point. I'll amend.
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c
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LGTM
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LGTM
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LGTM. Merry Christmas :)
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>From e235c1175aee293be30d3fc478d83c9b130e3452 Mon Sep 17 00:00:00 2001
From: Jonathan Thackray
Date: Fri, 13 Dec 2024 20:07:37 +
Subject: [PATCH 1/2] [AArch64] Add intrinsics for SME FP8 FVDOT, FVDOTB and
https://github.com/jthackray closed
https://github.com/llvm/llvm-project/pull/119845
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@@ -0,0 +1,54 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
UTC_ARGS: --filter-out "// kill:" --version 4
+; RUN: llc -force-streaming < %s | FileCheck %s
+target triple = "aarch64-linux"
+
+define void @test_fvdot16_1x2_indexed(i32 %slice.0,
+
@@ -5882,3 +5882,14 @@ multiclass sme2_fp8_fdot_index_za32_vg1x4;
}
+
+multiclass sme2_fp8_fdotv_index_za32_vg1x4 {
+ def NAME : sme2_fp8_multi_vec_array_vg4_index,
+SMEPseudo2Instr {
+let Uses=[FPMR, FPCR];
jthack
@@ -5882,3 +5882,14 @@ multiclass sme2_fp8_fdot_index_za32_vg1x4;
}
+
+multiclass sme2_fp8_fdotv_index_za32_vg1x4 {
+ def NAME : sme2_fp8_multi_vec_array_vg4_index,
+SMEPseudo2Instr {
+let Uses=[FPMR, FPCR];
+ }
+
+ def _PSEUDO :
@@ -748,11 +748,16 @@ let SMETargetGuard = "sme2" in {
let SMETargetGuard = "sme-f8f32" in {
def SVDOT_LANE_FP8_ZA32_VG1x2 : Inst<"svdot_lane_za32[_mf8]_vg1x2_fpm",
"vm2di>", "m", MergeNone, "aarch64_sme_fp8_fdot_lane_za32_vg1x2", [IsStreaming,
IsInOutZA, SetsFPMR, IsOverloa
https://github.com/jthackray updated
https://github.com/llvm/llvm-project/pull/119922
>From e235c1175aee293be30d3fc478d83c9b130e3452 Mon Sep 17 00:00:00 2001
From: Jonathan Thackray
Date: Fri, 13 Dec 2024 20:07:37 +
Subject: [PATCH 1/2] [AArch64] Add intrinsics for SME FP8 FVDOT, FVDOTB and
https://github.com/jthackray created
https://github.com/llvm/llvm-project/pull/119922
Add support for the following SME 8 bit floating-point dot-product intrinsics:
```
// Only if __ARM_FEATURE_SME_F8F16 != 0
void svvdot_lane_za16[_mf8]_vg1x2_fpm(uint32_t slice, svmfloat8x2_t zn,
https://github.com/jthackray edited
https://github.com/llvm/llvm-project/pull/119845
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https://github.com/jthackray edited
https://github.com/llvm/llvm-project/pull/119845
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https://github.com/jthackray approved this pull request.
LGTM
https://github.com/llvm/llvm-project/pull/119568
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https://github.com/jthackray edited
https://github.com/llvm/llvm-project/pull/119845
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https://github.com/jthackray edited
https://github.com/llvm/llvm-project/pull/119845
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https://github.com/jthackray approved this pull request.
LGTM
https://github.com/llvm/llvm-project/pull/119546
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@@ -827,11 +827,21 @@ let SMETargetGuard = "sme-lutv2" in {
let SMETargetGuard = "sme-f8f32" in {
def SVMOPA_FP8_ZA32 : Inst<"svmopa_za32[_mf8]_m_fpm", "viPPdd>", "m",
MergeNone, "aarch64_sme_fp8_fmopa_za32",
[IsStreaming, IsInOutZA, SetsFPMR,
I
@@ -827,11 +827,21 @@ let SMETargetGuard = "sme-lutv2" in {
let SMETargetGuard = "sme-f8f32" in {
def SVMOPA_FP8_ZA32 : Inst<"svmopa_za32[_mf8]_m_fpm", "viPPdd>", "m",
MergeNone, "aarch64_sme_fp8_fmopa_za32",
[IsStreaming, IsInOutZA, SetsFPMR,
I
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