@@ -0,0 +1,8 @@
+// Ensure that we can assemble NEON by just specifying an armv7
+// Apple or Windows target.
+
+// REQUIRES: arm-registered-target
+// RUN: %clang -c -target armv7-apple-darwin -o /dev/null %s
+// RUN: %clang -c -target armv7-windows -o /dev/null %s
--
https://github.com/Stylie777 edited
https://github.com/llvm/llvm-project/pull/134612
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@@ -0,0 +1,8 @@
+// Ensure that we can assemble NEON by just specifying an armv7
+// Apple or Windows target.
+
+// REQUIRES: arm-registered-target
+// RUN: %clang -c -target armv7-apple-darwin -o /dev/null %s
+// RUN: %clang -c -target armv7-windows -o /dev/null %s
--
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@@ -0,0 +1,8 @@
+// Ensure that we can assemble NEON by just specifying an armv7
+// Apple or Windows target.
+
+// REQUIRES: arm-registered-target
+// RUN: %clang -c -target armv7-apple-darwin -o /dev/null %s
+// RUN: %clang -c -target armv7-windows -o /dev/null %s
--
Stylie777 wrote:
I have created https://github.com/llvm/llvm-project/pull/134612 so I will now
close this PR.
@DavidSpickett your comments for the Release Notes have been worked on in the
new PR.
https://github.com/llvm/llvm-project/pull/134366
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https://github.com/Stylie777 created
https://github.com/llvm/llvm-project/pull/134612
Previously, `cc1as` did not consider the Features that can be included from a
target's FPU. This could lead to a situation where assembly files could not
compile as cc1as did not know if a feature was support
https://github.com/Stylie777 edited
https://github.com/llvm/llvm-project/pull/134366
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https://github.com/Stylie777 commented:
Adding my review here so it can be tracked. I will make the changes in the PR I
will open today @mstorsjo so these changes can be merged.
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@@ -0,0 +1,31 @@
+// Ensures that when targeting an ARM target with an Asm file, clang
+// collects the features from the FPU. This is critical in the
+// activation of NEON for supported targets. The Cortex-R52 will be
+// used and tested for VFP and NEON Support
+
+// RUN: %clan
https://github.com/Stylie777 commented:
Thanks @davemgreen for the re-review. I have made some updated based on your
comments.
https://github.com/llvm/llvm-project/pull/130623
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Stylie777 wrote:
I think we close it and I will open a new PR under my name next week.
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@@ -659,13 +659,21 @@ llvm::ARM::FPUKind arm::getARMTargetFeatures(const Driver
&D,
CPUArgFPUKind != llvm::ARM::FK_INVALID ? CPUArgFPUKind :
ArchArgFPUKind;
(void)llvm::ARM::getFPUFeatures(FPUKind, Features);
} else {
+bool Generic = true;
if (!ForAS) {
@@ -659,13 +659,21 @@ llvm::ARM::FPUKind arm::getARMTargetFeatures(const Driver
&D,
CPUArgFPUKind != llvm::ARM::FK_INVALID ? CPUArgFPUKind :
ArchArgFPUKind;
(void)llvm::ARM::getFPUFeatures(FPUKind, Features);
} else {
+bool Generic = true;
if (!ForAS) {
@@ -659,13 +659,21 @@ llvm::ARM::FPUKind arm::getARMTargetFeatures(const Driver
&D,
CPUArgFPUKind != llvm::ARM::FK_INVALID ? CPUArgFPUKind :
ArchArgFPUKind;
(void)llvm::ARM::getFPUFeatures(FPUKind, Features);
} else {
+bool Generic = true;
if (!ForAS) {
@@ -0,0 +1,31 @@
+// Ensures that when targeting an ARM target with an Asm file, clang
+// collects the features from the FPU. This is critical in the
+// activation of NEON for supported targets. The Cortex-R52 will be
+// used and tested for VFP and NEON Support
+
+// RUN: %clan
https://github.com/Stylie777 updated
https://github.com/llvm/llvm-project/pull/130623
>From 8b2ad7c1475ff4aee065e9feb21469d184320472 Mon Sep 17 00:00:00 2001
From: Jack Styles
Date: Fri, 7 Mar 2025 15:51:34 +
Subject: [PATCH 01/10] [NFC][ARM] Split SIMD identifier away from MVE
Previously,
https://github.com/Stylie777 updated
https://github.com/llvm/llvm-project/pull/130623
>From 8b2ad7c1475ff4aee065e9feb21469d184320472 Mon Sep 17 00:00:00 2001
From: Jack Styles
Date: Fri, 7 Mar 2025 15:51:34 +
Subject: [PATCH 1/9] [NFC][ARM] Split SIMD identifier away from MVE
Previously, t
@@ -38,6 +38,9 @@ Potentially Breaking Changes
- Fix missing diagnostics for uses of declarations when performing typename
access,
such as when performing member access on a '[[deprecated]]' type alias.
(#GH58547)
+- For ARM targets, when using cc1as, the features included
@@ -679,20 +679,18 @@ llvm::ARM::FPUKind arm::getARMTargetFeatures(const Driver
&D,
CPUArgFPUKind != llvm::ARM::FK_INVALID ? CPUArgFPUKind :
ArchArgFPUKind;
(void)llvm::ARM::getFPUFeatures(FPUKind, Features);
} else {
-bool Generic = true;
-if (!ForAS) {
https://github.com/Stylie777 edited
https://github.com/llvm/llvm-project/pull/130623
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@@ -679,20 +679,18 @@ llvm::ARM::FPUKind arm::getARMTargetFeatures(const Driver
&D,
CPUArgFPUKind != llvm::ARM::FK_INVALID ? CPUArgFPUKind :
ArchArgFPUKind;
(void)llvm::ARM::getFPUFeatures(FPUKind, Features);
} else {
-bool Generic = true;
-if (!ForAS) {
https://github.com/Stylie777 edited
https://github.com/llvm/llvm-project/pull/130623
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https://github.com/Stylie777 updated
https://github.com/llvm/llvm-project/pull/130623
>From 8b2ad7c1475ff4aee065e9feb21469d184320472 Mon Sep 17 00:00:00 2001
From: Jack Styles
Date: Fri, 7 Mar 2025 15:51:34 +
Subject: [PATCH 1/8] [NFC][ARM] Split SIMD identifier away from MVE
Previously, t
@@ -85,6 +85,9 @@ Changes to the AMDGPU Backend
Changes to the ARM Backend
--
+* The `+nosimd` attribute is now fully supported. Previously, this had no
effect when being used with
+AArch32 targets, however this will now disable NEON instructions being
https://github.com/Stylie777 created
https://github.com/llvm/llvm-project/pull/130623
`+simd` and `+nosimd` are used to emable or disable NEON Instructions
when compiling for AArch32 Targets. However, up until now, using these
has not been possible. To enable this, these options are mapped to th
Stylie777 wrote:
No worries 😀
If we remove `ARM::AEK_SIMD` is removed, the target will not be able to process
or generate NEON instructions. I have added it to all ArmV8-a (and beyond)
architectures and the Cortex-R52 CPU. This should cover all the Cortex-A and
Cortex-R targets that support i
Stylie777 wrote:
I have just pushed an update for the Unit Tests that should turn the CI green.
This is now ready for re-review @davemgreen
https://github.com/llvm/llvm-project/pull/130623
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https
https://github.com/Stylie777 updated
https://github.com/llvm/llvm-project/pull/130623
>From 7c0b94752285f2734d79e9e8d38aa20b3f7e8e61 Mon Sep 17 00:00:00 2001
From: Jack Styles
Date: Fri, 7 Mar 2025 15:51:34 +
Subject: [PATCH 1/7] [NFC][ARM] Split SIMD identifier away from MVE
Previously, t
https://github.com/Stylie777 updated
https://github.com/llvm/llvm-project/pull/130623
>From 7c0b94752285f2734d79e9e8d38aa20b3f7e8e61 Mon Sep 17 00:00:00 2001
From: Jack Styles
Date: Fri, 7 Mar 2025 15:51:34 +
Subject: [PATCH 1/4] [NFC][ARM] Split SIMD identifier away from MVE
Previously, t
https://github.com/Stylie777 edited
https://github.com/llvm/llvm-project/pull/130623
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https://github.com/Stylie777 updated
https://github.com/llvm/llvm-project/pull/130623
>From 7c0b94752285f2734d79e9e8d38aa20b3f7e8e61 Mon Sep 17 00:00:00 2001
From: Jack Styles
Date: Fri, 7 Mar 2025 15:51:34 +
Subject: [PATCH 1/6] [NFC][ARM] Split SIMD identifier away from MVE
Previously, t
@@ -334,8 +334,8 @@ ARM_CPU_NAME("cortex-r7", ARMV7R, FK_VFPV3_D16_FP16, false,
(ARM::AEK_MP | ARM::AEK_HWDIVARM))
ARM_CPU_NAME("cortex-r8", ARMV7R, FK_VFPV3_D16_FP16, false,
(ARM::AEK_MP | ARM::AEK_HWDIVARM))
-ARM_CPU_NAME("cortex-r52", ARMV8R, FK_NEO
@@ -334,8 +334,8 @@ ARM_CPU_NAME("cortex-r7", ARMV7R, FK_VFPV3_D16_FP16, false,
(ARM::AEK_MP | ARM::AEK_HWDIVARM))
ARM_CPU_NAME("cortex-r8", ARMV7R, FK_VFPV3_D16_FP16, false,
(ARM::AEK_MP | ARM::AEK_HWDIVARM))
-ARM_CPU_NAME("cortex-r52", ARMV8R, FK_NEO
https://github.com/Stylie777 edited
https://github.com/llvm/llvm-project/pull/130623
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@@ -334,8 +334,8 @@ ARM_CPU_NAME("cortex-r7", ARMV7R, FK_VFPV3_D16_FP16, false,
(ARM::AEK_MP | ARM::AEK_HWDIVARM))
ARM_CPU_NAME("cortex-r8", ARMV7R, FK_VFPV3_D16_FP16, false,
(ARM::AEK_MP | ARM::AEK_HWDIVARM))
-ARM_CPU_NAME("cortex-r52", ARMV8R, FK_NEO
https://github.com/Stylie777 commented:
Thanks for the comments @davemgreen. I need to do some more investigation here
as I think there is more going wrong than I initially thought after this change
is introduced.
https://github.com/llvm/llvm-project/pull/130623
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Stylie777 wrote:
The description is fixed. Thanks @DavidSpickett and @jthackray (I will publish
a commit to your improvements once I have a green CI so I know all is good).
https://github.com/llvm/llvm-project/pull/130623
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Stylie777 wrote:
Thanks @jthackray. The CI Failure seems to be unrelated.
https://github.com/llvm/llvm-project/pull/130623
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@@ -85,6 +85,9 @@ Changes to the AMDGPU Backend
Changes to the ARM Backend
--
+* The `+nosimd` attribute is now fully supported. Previously, this had no
effect when being used with
+AArch32 targets, however will now disable NEON instructions being gene
@@ -85,6 +85,9 @@ Changes to the AMDGPU Backend
Changes to the ARM Backend
--
+* The `+nosimd` attribute is now fully supported. Previously, this had no
effect when being used with
+AArch32 targets, however will now disable NEON instructions being gene
https://github.com/Stylie777 updated
https://github.com/llvm/llvm-project/pull/130623
>From d6772d64ff6fd515621c073b6545c40e918893b5 Mon Sep 17 00:00:00 2001
From: Jack Styles
Date: Fri, 7 Mar 2025 15:51:34 +
Subject: [PATCH 1/3] [NFC][ARM] Split SIMD identifier away from MVE
Previously, t
https://github.com/Stylie777 edited
https://github.com/llvm/llvm-project/pull/130623
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Stylie777 wrote:
I don't believe the above CI test failure to be related. This change targets
ARM. This is an unchanged architecture.
https://github.com/llvm/llvm-project/pull/124935
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@@ -1013,3 +1013,41 @@
// CHECK-MVE1_2: #define __ARM_FEATURE_MVE 1
// RUN: %clang -target arm-arm-none-eabi -march=armv8.1-m.main+mve.fp -x c -E
-dM %s -o - | FileCheck -check-prefix=CHECK-MVE3 %s
// CHECK-MVE3: #define __ARM_FEATURE_MVE 3
+
+// Cortex-R52 and Cortex-R52Plus
https://github.com/Stylie777 updated
https://github.com/llvm/llvm-project/pull/124935
>From 8da3a78692c4c0c4d4a47610d7b705f1a55f6f14 Mon Sep 17 00:00:00 2001
From: Jack Styles
Date: Wed, 29 Jan 2025 15:19:46 +
Subject: [PATCH 1/4] [ARM] Ensure FPU Selection can select mode correctly
Previo
@@ -1013,3 +1013,19 @@
// CHECK-MVE1_2: #define __ARM_FEATURE_MVE 1
// RUN: %clang -target arm-arm-none-eabi -march=armv8.1-m.main+mve.fp -x c -E
-dM %s -o - | FileCheck -check-prefix=CHECK-MVE3 %s
// CHECK-MVE3: #define __ARM_FEATURE_MVE 3
+
+// Cortex-R52 and Cortex-R52Plus
https://github.com/Stylie777 updated
https://github.com/llvm/llvm-project/pull/124935
>From 8da3a78692c4c0c4d4a47610d7b705f1a55f6f14 Mon Sep 17 00:00:00 2001
From: Jack Styles
Date: Wed, 29 Jan 2025 15:19:46 +
Subject: [PATCH 1/3] [ARM] Ensure FPU Selection can select mode correctly
Previo
https://github.com/Stylie777 updated
https://github.com/llvm/llvm-project/pull/124935
>From 1b12ad277c63e707c1b4268fc46f942349bbb1d9 Mon Sep 17 00:00:00 2001
From: Jack Styles
Date: Wed, 29 Jan 2025 15:19:46 +
Subject: [PATCH 1/2] [ARM] Ensure FPU Selection can select mode correctly
Previo
https://github.com/Stylie777 created
https://github.com/llvm/llvm-project/pull/124935
Previously, when selecting a Single Precision FPU, LLVM would ensure all
elements of the Candidate FPU matched the InputFPU that was given. However, for
cases such as Cortex-R52, there are FPU options where n
https://github.com/Stylie777 closed
https://github.com/llvm/llvm-project/pull/123028
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https://github.com/Stylie777 approved this pull request.
LGTM! Thanks
https://github.com/llvm/llvm-project/pull/123028
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https://github.com/Stylie777 commented:
Was there any tests that need changing/updating for this? If we don't have
tests for this it might be worth adding some.
https://github.com/llvm/llvm-project/pull/123028
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https://github.com/Stylie777 closed
https://github.com/llvm/llvm-project/pull/112171
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https://github.com/Stylie777 approved this pull request.
LGTM
https://github.com/llvm/llvm-project/pull/113496
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@@ -799,6 +802,24 @@ bool CFI_Parser::parseFDEInstructions(A &addressSpace,
}
break;
+#if defined(_LIBUNWIND_TARGET_AARCH64)
+ case DW_CFA_AARCH64_negate_ra_state_with_pc: {
+int64_t value =
+results->savedRegisters[UNW_AARCH64_RA_SIGN_
@@ -833,8 +841,8 @@ def HasV9_5aOps : Architecture64<9, 5, "a", "v9.5a",
[HasV9_4aOps, FeatureCPA],
!listconcat(HasV9_4aOps.DefaultExts, [FeatureCPA, FeatureLUT,
FeatureFAMINMAX])>;
def HasV9_6aOps : Architecture64<9, 6, "a", "v9.6a",
- [HasV9_5aOps],
- !listconcat(HasV
https://github.com/Stylie777 updated
https://github.com/llvm/llvm-project/pull/112171
>From a702473aacc6a9c47eb80b204ee3200c2ff2eb26 Mon Sep 17 00:00:00 2001
From: Jack Styles
Date: Thu, 3 Oct 2024 14:20:10 +0100
Subject: [PATCH 1/6] [PAuthLR] Add support for FEAT_PAuth_LR to libunwind
This in
https://github.com/Stylie777 reopened
https://github.com/llvm/llvm-project/pull/112341
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Stylie777 wrote:
It might be worth splitting each feature into its own commit rather than one
big commit, it makes the review easier. Currently it's difficult to determine
which section belongs to which feature.
https://github.com/llvm/llvm-project/pull/112341
_
https://github.com/Stylie777 closed
https://github.com/llvm/llvm-project/pull/112341
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https://github.com/Stylie777 updated
https://github.com/llvm/llvm-project/pull/112171
>From 98681d52343a055d0d626fcde36042f02c40a94a Mon Sep 17 00:00:00 2001
From: Jack Styles
Date: Thu, 3 Oct 2024 14:20:10 +0100
Subject: [PATCH 1/5] [PAuthLR] Add support for FEAT_PAuth_LR to libunwind
This in
https://github.com/Stylie777 created
https://github.com/llvm/llvm-project/pull/112171
As part of FEAT_PAuthLR, a new DWARF Frame Instruction was introduced,
`DW_CFA_AARCH64_negate_ra_state_with_pc`. This instructs Libunwind that the PC
has been used with the signing instruction. This change in
https://github.com/Stylie777 approved this pull request.
LGTM
https://github.com/llvm/llvm-project/pull/110825
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@@ -706,6 +706,11 @@ def HasV9_5aOps : SubtargetFeature<"v9.5a",
"HasV9_5aOps", "true",
"Support ARM v9.5a instructions",
[HasV9_4aOps]>;
+// Armv9.6-A is a v9-only architecture.
+def HasV9_6aOps : Subt
https://github.com/Stylie777 approved this pull request.
Agree with @tmatheson-arm that there is more standardisation we can do here,
but probably out of scope for this PR.
https://github.com/llvm/llvm-project/pull/98550
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c
@@ -106,24 +106,24 @@ def FeatureSpecRestrict : Extension<"specrestrict",
"SpecRestrict", "FEAT_CSV2_2
//===--===//
def FeatureLSE : ExtensionWithMArch<"lse", "LSE", "FEAT_LSE",
- "Enable ARMv8.1 Large Syst
https://github.com/Stylie777 closed
https://github.com/llvm/llvm-project/pull/90614
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https://github.com/Stylie777 updated
https://github.com/llvm/llvm-project/pull/90614
>From db0ca41c85b69f02f6e3b522ff3a2948e6a729fe Mon Sep 17 00:00:00 2001
From: Jack Styles
Date: Wed, 17 Apr 2024 14:17:51 +0100
Subject: [PATCH 1/4] [NFC] Add Extension Lookup to AArch64TargetParser
Currently,
https://github.com/Stylie777 updated
https://github.com/llvm/llvm-project/pull/90614
>From 59bc10d7418ed86f2fd94c8db5e34896164ef8e6 Mon Sep 17 00:00:00 2001
From: Jack Styles
Date: Wed, 17 Apr 2024 14:17:51 +0100
Subject: [PATCH 1/4] [NFC] Add Extension Lookup to AArch64TargetParser
Currently,
https://github.com/Stylie777 updated
https://github.com/llvm/llvm-project/pull/90614
>From fa5d76b2d6d095abad76d892e59751727ac2e556 Mon Sep 17 00:00:00 2001
From: Jack Styles
Date: Wed, 17 Apr 2024 14:17:51 +0100
Subject: [PATCH 1/4] [NFC] Add Extension Lookup to AArch64TargetParser
Currently,
https://github.com/Stylie777 updated
https://github.com/llvm/llvm-project/pull/90614
>From fa5d76b2d6d095abad76d892e59751727ac2e556 Mon Sep 17 00:00:00 2001
From: Jack Styles
Date: Wed, 17 Apr 2024 14:17:51 +0100
Subject: [PATCH 1/3] [NFC] Add Extension Lookup to AArch64TargetParser
Currently,
https://github.com/Stylie777 updated
https://github.com/llvm/llvm-project/pull/90614
>From b21ee486bc7a877d3134bfcaf8633f171df2a043 Mon Sep 17 00:00:00 2001
From: Jack Styles
Date: Wed, 17 Apr 2024 14:17:51 +0100
Subject: [PATCH 1/3] [NFC] Add Extension Lookup to AArch64TargetParser
Currently,
https://github.com/Stylie777 updated
https://github.com/llvm/llvm-project/pull/90614
>From b21ee486bc7a877d3134bfcaf8633f171df2a043 Mon Sep 17 00:00:00 2001
From: Jack Styles
Date: Wed, 17 Apr 2024 14:17:51 +0100
Subject: [PATCH 1/2] [NFC] Add Extension Lookup to AArch64TargetParser
Currently,
https://github.com/Stylie777 edited
https://github.com/llvm/llvm-project/pull/90614
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https://github.com/Stylie777 created
https://github.com/llvm/llvm-project/pull/90614
Currently, LLVM enables `-mbranch-protection=standard` as `bti+pac-ret`. To
align LLVM with the behaviour in GNU, this has been updated to `bti+pac-ret+pc`
when FEAT_PAuth_LR is enabled as an optional feature
https://github.com/Stylie777 approved this pull request.
https://github.com/llvm/llvm-project/pull/90440
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https://github.com/Stylie777 approved this pull request.
LGTM!
https://github.com/llvm/llvm-project/pull/90143
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https://github.com/Stylie777 closed
https://github.com/llvm/llvm-project/pull/85203
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@@ -2487,10 +2480,10 @@ AArch64ExtensionDependenciesBaseCPUTestParams
{}},
{"cortex-a520",
{},
- {"v9.2a","bf16", "crc", "dotprod", "f32mm",
"flagm",
- "fp-armv8", "fullfp16", "fp16fml", "i8mm","lse", "
Stylie777 wrote:
@jthackray I have updated the commit message as part of the most recent patch
set.
https://github.com/llvm/llvm-project/pull/85203
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@@ -74,6 +74,7 @@ Changes to the AMDGPU Backend
Changes to the ARM Backend
--
+* FEAT_F32MM is no longer activated by default when using `+sve` on v8.6-A or
greater. The feature is still availble and can be using by adding `+f32mm` to
the command line
https://github.com/Stylie777 updated
https://github.com/llvm/llvm-project/pull/85203
>From 7a2fbb00155da9e165c82614c9436e149c2b18e4 Mon Sep 17 00:00:00 2001
From: Jack Styles
Date: Thu, 14 Mar 2024 13:55:46 +
Subject: [PATCH] [AArch64] Remove Automatic Enablement of FEAT_F32MM
When `+sve`
https://github.com/Stylie777 updated
https://github.com/llvm/llvm-project/pull/85203
>From 276e3421de7ebe2e2a9a2feb02d585bf3d4e8915 Mon Sep 17 00:00:00 2001
From: Jack Styles
Date: Thu, 14 Mar 2024 10:43:22 +
Subject: [PATCH] [AArch64] Remove Automatic Enablement of FEAT_F32MM
When `+sve`
https://github.com/Stylie777 created
https://github.com/llvm/llvm-project/pull/85203
When `+sve` is passed in the command line, if the Architecture being targeted
is V8.6A/V9.1A or later, `+f32mm` is also added. This enables FEAT_32MM,
however at the time of writing no CPU's support this. This
Stylie777 wrote:
I think this can be one commit, the formatting changes can be squashed into the
commit that makes the changes. Also make sure the commit message fits in with
LLVM guidelines. See: https://llvm.org/docs/DeveloperPolicy.html#id18
https://github.com/llvm/llvm-project/pull/81466
_
https://github.com/Stylie777 edited
https://github.com/llvm/llvm-project/pull/80819
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https://github.com/Stylie777 approved this pull request.
LGTM
https://github.com/llvm/llvm-project/pull/80819
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@@ -1354,9 +1354,9 @@ let isScalarNarrowShift = 1 in {
// Signed/Unsigned Saturating Rounded Shift Right Narrow (Immediate)
def SCALAR_SQRSHRN_N: SInst<"vqrshrn_n", "(1<)1I", "SsSiSlSUsSUiSUl">;
// Signed Saturating Shift Right Unsigned Narrow (Immediate)
- def SCALAR_SQ
@@ -1354,9 +1354,9 @@ let isScalarNarrowShift = 1 in {
// Signed/Unsigned Saturating Rounded Shift Right Narrow (Immediate)
def SCALAR_SQRSHRN_N: SInst<"vqrshrn_n", "(1<)1I", "SsSiSlSUsSUiSUl">;
// Signed Saturating Shift Right Unsigned Narrow (Immediate)
- def SCALAR_SQ
https://github.com/Stylie777 commented:
One comment from me
https://github.com/llvm/llvm-project/pull/80819
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https://github.com/Stylie777 edited
https://github.com/llvm/llvm-project/pull/80819
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