https://github.com/hassnaaHamdi edited
https://github.com/llvm/llvm-project/pull/141777
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hassnaaHamdi wrote:
> This is an interesting idea, thanks for the performance numbers. It could
> also be useful for LTO without whole program visibility enabled, where most
> of the vtables and type tests will end up with public visibility making them
> ineligible for WPD. But I suspect it ma
hassnaaHamdi wrote:
> This is an interesting idea, thanks for the performance numbers. It could
> also be useful for LTO without whole program visibility enabled, where most
> of the vtables and type tests will end up with public visibility making them
> ineligible for WPD. But I suspect it ma
hassnaaHamdi wrote:
Hi
@teresajohnson @pcc @PiJoules @mingmingl-llvm
Any feedback about this? 👀
https://github.com/llvm/llvm-project/pull/141777
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@@ -1342,26 +1353,28 @@ bool DevirtModule::trySingleImplDevirt(
// If the only implementation has local linkage, we must promote to external
// to make it visible to thin LTO objects. We can only get here during the
// ThinLTO export phase.
hassnaaHamdi w
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https://github.com/hassnaaHamdi created
https://github.com/llvm/llvm-project/pull/141777
None
>From 702f64a84914d2fe467a12babd99338f2215d425 Mon Sep 17 00:00:00 2001
From: Hassnaa Hamdi
Date: Wed, 28 May 2025 14:27:34 +
Subject: [PATCH] Enable WPD without lto
---
clang/lib/CodeGen/CGVTab
https://github.com/hassnaaHamdi closed
https://github.com/llvm/llvm-project/pull/93495
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@@ -118,6 +124,37 @@ llvm::Type *CodeGenTypes::ConvertTypeForMem(QualType T,
bool ForBitField) {
return R;
}
+bool CodeGenTypes::LLVMTypeLayoutMatchesAST(QualType ASTTy,
+llvm::Type *LLVMTy) {
+ CharUnits ASTSize = Context.getTyp
https://github.com/hassnaaHamdi updated
https://github.com/llvm/llvm-project/pull/93495
>From e3f080d3b6b355e0726bc0058129ddd3066dbb2e Mon Sep 17 00:00:00 2001
From: Hassnaa Hamdi
Date: Tue, 28 May 2024 01:04:00 +
Subject: [PATCH] [Clang][AArch64][ARM]: Fix Inefficient loads/stores of
_Bit
https://github.com/hassnaaHamdi updated
https://github.com/llvm/llvm-project/pull/93495
>From 6b7cc14e5dcca7416c549bd156585e2a61d4d883 Mon Sep 17 00:00:00 2001
From: Hassnaa Hamdi
Date: Tue, 28 May 2024 01:04:00 +
Subject: [PATCH] [Clang][AArch64][ARM]: Fix Inefficient loads/stores of
_Bit
https://github.com/hassnaaHamdi created
https://github.com/llvm/llvm-project/pull/93495
- Update clang codegen for loads/stores to read/write the legal in-memory
representation for _BitInt(N <= 128) and _BitInt(N <= 64).
- AArch64: for _BitInt(N <= 128) the machine type is the smallest (un)sign
https://github.com/hassnaaHamdi closed
https://github.com/llvm/llvm-project/pull/90105
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@@ -458,6 +458,40 @@ let TargetGuard = "sme2,sme-f64f64" in {
def SVMLS_LANE_VG1x4_F64 : Inst<"svmls_lane_za64[_{d}]_vg1x4", "vm4di", "d",
MergeNone, "aarch64_sme_fmls_lane_vg1x4", [IsStreaming, IsInOutZA],
[ImmCheck<3, ImmCheck0_1>]>;
}
+let TargetGuard = "sme2p1,sme-f16f
@@ -173,6 +173,8 @@ enum ArchExtKind : unsigned {
AEK_SMEF8F16 = 69, // FEAT_SME_F8F16
AEK_SMEF8F32 = 70, // FEAT_SME_F8F32
AEK_SMEFA64 = 71, // FEAT_SME_FA64
+ AEK_JSCVT = 72, // FEAT_JSCVT
+ AEK_FCMA = 73, // FEAT_FCMA
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