[clang] [Clang][AArch64][ARM]: Fix Inefficient loads/stores of _BitInt(N) (PR #93495)

https://github.com/hassnaaHamdi closed https://github.com/llvm/llvm-project/pull/93495 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [clang] Lower _BitInt(129+) to a different type in LLVM IR (PR #91364)

@@ -118,6 +124,37 @@ llvm::Type *CodeGenTypes::ConvertTypeForMem(QualType T, bool ForBitField) { return R; } +bool CodeGenTypes::LLVMTypeLayoutMatchesAST(QualType ASTTy, +llvm::Type *LLVMTy) { + CharUnits ASTSize = Context.getTyp

[clang] [Clang][AArch64][ARM]: Fix Inefficient loads/stores of _BitInt(N) (PR #93495)

https://github.com/hassnaaHamdi updated https://github.com/llvm/llvm-project/pull/93495 >From e3f080d3b6b355e0726bc0058129ddd3066dbb2e Mon Sep 17 00:00:00 2001 From: Hassnaa Hamdi Date: Tue, 28 May 2024 01:04:00 + Subject: [PATCH] [Clang][AArch64][ARM]: Fix Inefficient loads/stores of _Bit

[clang] [Clang][AArch64][ARM]: Fix Inefficient loads/stores of _BitInt(N) (PR #93495)

https://github.com/hassnaaHamdi updated https://github.com/llvm/llvm-project/pull/93495 >From 6b7cc14e5dcca7416c549bd156585e2a61d4d883 Mon Sep 17 00:00:00 2001 From: Hassnaa Hamdi Date: Tue, 28 May 2024 01:04:00 + Subject: [PATCH] [Clang][AArch64][ARM]: Fix Inefficient loads/stores of _Bit

[clang] [Clang][AArch64][ARM]: Fix Inefficient loads/stores of _BitInt(N) (PR #93495)

https://github.com/hassnaaHamdi created https://github.com/llvm/llvm-project/pull/93495 - Update clang codegen for loads/stores to read/write the legal in-memory representation for _BitInt(N <= 128) and _BitInt(N <= 64). - AArch64: for _BitInt(N <= 128) the machine type is the smallest (un)sign

[clang] [llvm] [AArch64] Add intrinsics for bfloat16 min/max/minnm/maxnm (PR #90105)

https://github.com/hassnaaHamdi closed https://github.com/llvm/llvm-project/pull/90105 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [AArch64] Add intrinsics for bfloat16 min/max/minnm/maxnm (PR #90105)

https://github.com/hassnaaHamdi edited https://github.com/llvm/llvm-project/pull/90105 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [AArch64] Add intrinsics for bfloat16 min/max/minnm/maxnm (PR #90105)

https://github.com/hassnaaHamdi edited https://github.com/llvm/llvm-project/pull/90105 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [AArch64] Add intrinsics for 16-bit non-widening FMLA/FMLS (PR #88553)

@@ -458,6 +458,40 @@ let TargetGuard = "sme2,sme-f64f64" in { def SVMLS_LANE_VG1x4_F64 : Inst<"svmls_lane_za64[_{d}]_vg1x4", "vm4di", "d", MergeNone, "aarch64_sme_fmls_lane_vg1x4", [IsStreaming, IsInOutZA], [ImmCheck<3, ImmCheck0_1>]>; } +let TargetGuard = "sme2p1,sme-f16f

[llvm] [clang] [TargetParser] Define AEK_FCMA and AEK_JSCVT for tsv110 (PR #75516)

@@ -173,6 +173,8 @@ enum ArchExtKind : unsigned { AEK_SMEF8F16 = 69, // FEAT_SME_F8F16 AEK_SMEF8F32 = 70, // FEAT_SME_F8F32 AEK_SMEFA64 = 71, // FEAT_SME_FA64 + AEK_JSCVT = 72, // FEAT_JSCVT + AEK_FCMA = 73, // FEAT_FCMA