ego added a comment.
FYI, more issues with v0 not being accepted as an operand with unmasked
instructions.
Comment at: llvm/test/MC/RISCV/rvv/rv64zvkns.s:59
+
+vaeskf1.vi v10, v9, 1
+# CHECK-INST: vaeskf1.vi v10, v9, 1
ego wrote:
> craig.topper wrote:
> > ego
ego added inline comments.
Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td:135
+ defm VANDN_V : VALU_IV_V_X_I<"vandn", 0b01>;
+ def VBREV8_V : VALUVs2<0b010010, 0b01000, OPIVV, "vbrev8.v">;
+ defm VCLMUL_V : VALU_IV_V_X_VCLMUL<"vclmul", 0b001100>;
T
ego added a comment.
See my comment below where I can trigger an MC-layer assertion when using
"vaeskf1 v0, ...".
Comment at: llvm/test/MC/RISCV/rvv/rv64zvkns.s:1-9
+# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+zve32x
--mattr=+experimental-zvkns %s \
+# RUN:
ego added inline comments.
Comment at: llvm/lib/Support/RISCVISAInfo.cpp:827
+{{"zvkg"}, {ImpliedExtsZve32x}},
+{{"zvknha"}, {ImpliedExtsZve32x}},
+{{"zvknhb"}, {ImpliedExtsZve64x}},
ego wrote:
> How does this work? This doesn't seem to be enough,
> "
ego added inline comments.
Comment at: llvm/lib/Support/RISCVISAInfo.cpp:827
+{{"zvkb"}, {ImpliedExtsZve64x}},
+{{"zvkg"}, {ImpliedExtsZve32x}},
+{{"zvknha"}, {ImpliedExtsZve32x}},
craig.topper wrote:
> ego wrote:
> > What is the reasoning between 32
ego added a comment.
I have been working on a patch set to support Zvk. It will take me a few more
days to prepare my patches to post them publicly.
Your patches are in a very good shape and a lot of files end up looking pretty
similar.
I have a few comments, most minor.
This is my first review
