[clang] [llvm] [NVPTX] Add intrinsics for cvt .f6x2 and .ue8m0x2 variants (PR #134345)

https://github.com/durga4github edited https://github.com/llvm/llvm-project/pull/134345 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [NVPTX] Add intrinsics for cvt .f6x2 and .ue8m0x2 variants (PR #134345)

durga4github wrote: Change looks good to me overall. Let us wait for Artem's review. https://github.com/llvm/llvm-project/pull/134345 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [NVPTX] Add intrinsics for cvt .f6x2 and .ue8m0x2 variants (PR #134345)

@@ -1548,6 +1548,45 @@ let TargetPrefix = "nvvm" in { Intrinsic<[llvm_v2f16_ty], [llvm_i16_ty], [IntrNoMem, IntrNoCallback]>; def int_nvvm_e5m2x2_to_f16x2_rn_relu : ClangBuiltin<"__nvvm_e5m2x2_to_f16x2_rn_relu">, Intrinsic<[llvm_v2f16_ty], [llvm_i16_ty], [IntrNoM

[clang] [llvm] cuda clang: Fix argument order for __reduce_max_sync (PR #132881)

https://github.com/durga4github approved this pull request. The latest changes LGTM https://github.com/llvm/llvm-project/pull/132881 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [NVPTX] Add intrinsics for redux.sync f32 instructions (PR #126664)

https://github.com/durga4github closed https://github.com/llvm/llvm-project/pull/126664 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [NVPTX] Add intrinsics for redux.sync f32 instructions (PR #126664)

durga4github wrote: Merging as per offline request https://github.com/llvm/llvm-project/pull/126664 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [NVPTX] Add intrinsics for redux.sync f32 instructions (PR #126664)

https://github.com/durga4github approved this pull request. The latest revision looks good to me. https://github.com/llvm/llvm-project/pull/126664 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/c

[clang] [llvm] [NVPTX] Add intrinsics for redux.sync f32 instructions (PR #126664)

@@ -1,11 +1,13 @@ -// RUN: %clang_cc1 "-triple" "nvptx-nvidia-cuda" "-target-feature" "+ptx70" "-target-cpu" "sm_80" -emit-llvm -fcuda-is-device -o - %s | FileCheck %s -// RUN: %clang_cc1 "-triple" "nvptx64-nvidia-cuda" "-target-feature" "+ptx70" "-target-cpu" "sm_80" -emit-llvm

[clang] [llvm] [NVPTX] Add intrinsics for redux.sync f32 instructions (PR #126664)

@@ -328,6 +328,24 @@ defm REDUX_SYNC_AND : REDUX_SYNC<"and", "b32", int_nvvm_redux_sync_and>; defm REDUX_SYNC_XOR : REDUX_SYNC<"xor", "b32", int_nvvm_redux_sync_xor>; defm REDUX_SYNC_OR : REDUX_SYNC<"or", "b32", int_nvvm_redux_sync_or>; +multiclass REDUX_SYNC_F { + def : NVP

[clang] [llvm] [NVPTX] Add intrinsics for redux.sync f32 instructions (PR #126664)

@@ -328,6 +328,24 @@ defm REDUX_SYNC_AND : REDUX_SYNC<"and", "b32", int_nvvm_redux_sync_and>; defm REDUX_SYNC_XOR : REDUX_SYNC<"xor", "b32", int_nvvm_redux_sync_xor>; defm REDUX_SYNC_OR : REDUX_SYNC<"or", "b32", int_nvvm_redux_sync_or>; +multiclass REDUX_SYNC_F { + def : NVP

[clang] [llvm] [NVPTX] Add tcgen05 alloc/dealloc intrinsics (PR #124961)

https://github.com/durga4github closed https://github.com/llvm/llvm-project/pull/124961 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [NVPTX] Add tcgen05 alloc/dealloc intrinsics (PR #124961)

@@ -962,6 +962,109 @@ The ``griddepcontrol`` intrinsics allows the dependent grids and prerequisite gr For more information, refer `PTX ISA `__. +

[clang] [llvm] [NVPTX] Add tcgen05 alloc/dealloc intrinsics (PR #124961)

https://github.com/durga4github updated https://github.com/llvm/llvm-project/pull/124961 >From 467c3a41badb66b9187864a040c9eeccef1b583c Mon Sep 17 00:00:00 2001 From: Durgadoss R Date: Wed, 29 Jan 2025 16:31:06 +0530 Subject: [PATCH] [NVPTX] Add tcgen05 alloc/dealloc intrinsics This patch adds

[clang] [llvm] [NVPTX] Add tcgen05 alloc/dealloc intrinsics (PR #124961)

https://github.com/durga4github updated https://github.com/llvm/llvm-project/pull/124961 >From 632fc53beebac1d77d33c1f46893f2c868b35313 Mon Sep 17 00:00:00 2001 From: Durgadoss R Date: Wed, 29 Jan 2025 16:31:06 +0530 Subject: [PATCH] [NVPTX] Add tcgen05 alloc/dealloc intrinsics This patch adds

[clang] [llvm] [NVPTX] Add tcgen05 alloc/dealloc intrinsics (PR #124961)

https://github.com/durga4github updated https://github.com/llvm/llvm-project/pull/124961 >From bfe728f879b5a20be2269c6d9e52c1feb0cce64b Mon Sep 17 00:00:00 2001 From: Durgadoss R Date: Wed, 29 Jan 2025 16:31:06 +0530 Subject: [PATCH] [NVPTX] Add tcgen05 alloc/dealloc intrinsics This patch adds

[clang] [StrTable] Mechanically convert NVPTX builtins to use TableGen (PR #122873)

https://github.com/durga4github edited https://github.com/llvm/llvm-project/pull/122873 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [StrTable] Mechanically convert NVPTX builtins to use TableGen (PR #122873)

durga4github wrote: LGTM overall. I work with these builtins only occasionally. So, let us wait for Artem's review. https://github.com/llvm/llvm-project/pull/122873 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin

[clang] [StrTable] Mechanically convert NVPTX builtins to use TableGen (PR #122873)

@@ -0,0 +1,1078 @@ +//===--- BuiltinsNVPTX.td - NVPTX Builtin function defs -*- C++ -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: A

[clang] [StrTable] Mechanically convert NVPTX builtins to use TableGen (PR #122873)

durga4github wrote: > Ping! > > I've updated this to incorporate the changes in #123398 to the NVPTX.def file > this is replacing. > Thanks for this! https://github.com/llvm/llvm-project/pull/122873 ___ cfe-commits mailing list cfe-commits@lists

[clang] Remove incorrect CUDA defines (PR #123898)

https://github.com/durga4github approved this pull request. Changes look good to me. Let us wait for Artem's review https://github.com/llvm/llvm-project/pull/123898 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/

[clang] [llvm] [NVPTX] Add support for PTX 8.6 and CUDA 12.6 (12.8) (PR #123398)

@@ -682,6 +688,9 @@ void NVPTX::getNVPTXTargetFeatures(const Driver &D, const llvm::Triple &Triple, case CudaVersion::CUDA_##CUDA_VER: \ PtxFeature = "+ptx" #PTX_VER; \ break; +

[clang] [llvm] [NVPTX] Add support for PTX 8.6 and CUDA 12.6 (12.8) (PR #123398)

https://github.com/durga4github approved this pull request. The updates look good to me. https://github.com/llvm/llvm-project/pull/123398 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commit

[clang] [llvm] [mlir] [NVPTX] Switch front-ends and tests to ptx_kernel cc (PR #120806)

@@ -556,19 +556,16 @@ llvm.func @kernel_func() attributes {nvvm.kernel} { llvm.return } -// CHECK: !nvvm.annotations = -// CHECK-NOT: {ptr @nvvm_special_regs, !"kernel", i32 1} -// CHECK: {ptr @kernel_func, !"kernel", i32 1} +// CHECK: ptx_kernel void @kernel_func --

[clang] [llvm] [mlir] [NVPTX] Switch front-ends and tests to ptx_kernel cc (PR #120806)

@@ -556,19 +556,16 @@ llvm.func @kernel_func() attributes {nvvm.kernel} { llvm.return } -// CHECK: !nvvm.annotations = -// CHECK-NOT: {ptr @nvvm_special_regs, !"kernel", i32 1} -// CHECK: {ptr @kernel_func, !"kernel", i32 1} +// CHECK: ptx_kernel void @kernel_func --

[clang] [llvm] [llvm][NFC] `APFloat`: Add missing semantics to enum (PR #117291)

durga4github wrote: Hi @matthias-springer , Can we split this into at least two separate PRs? One for the first two items in the commit message. And one (or two) PRs for the rest of the changes. https://github.com/llvm/llvm-project/pull/117291 ___ c

[clang] [llvm] [APFloat] Add APFloat support for FP4 data type (PR #95392)

https://github.com/durga4github closed https://github.com/llvm/llvm-project/pull/95392 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [APFloat] Add APFloat support for FP4 data type (PR #95392)

https://github.com/durga4github updated https://github.com/llvm/llvm-project/pull/95392 >From af17388ffd5096a0c50b62dbd8073f957c052bb1 Mon Sep 17 00:00:00 2001 From: Durgadoss R Date: Wed, 12 Jun 2024 23:55:04 +0530 Subject: [PATCH] [APFloat] Add APFloat support for FP4 data type This patch ad

[clang] [llvm] [APFloat] Add APFloat support for FP4 data type (PR #95392)

@@ -6907,6 +7028,42 @@ TEST(APFloatTest, ConvertE2M3FToE3M2F) { EXPECT_EQ(status, APFloat::opInexact); } +TEST(APFloatTest, ConvertDoubleToE2M1F) { + bool losesInfo; durga4github wrote: Updated this also to be consistent. https://github.com/llvm/llvm-proj

[clang] [llvm] [APFloat] Add APFloat support for FP4 data type (PR #95392)

@@ -69,8 +69,8 @@ enum class fltNonfiniteBehavior { // encodings do not distinguish between signalling and quiet NaN. NanOnly, - // This behavior is present in Float6E3M2FN and Float6E2M3FN types, - // which do not support Inf or NaN values. + // This behavior is presen

[clang] [llvm] [APFloat] Add APFloat support for FP4 data type (PR #95392)

durga4github wrote: @ThomasRaoux, Could you please help review this change? https://github.com/llvm/llvm-project/pull/95392 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [APFloat] Add APFloat support for FP4 data type (PR #95392)

https://github.com/durga4github edited https://github.com/llvm/llvm-project/pull/95392 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [APFloat] Add APFloat support for FP4 data type (PR #95392)

https://github.com/durga4github created https://github.com/llvm/llvm-project/pull/95392 This patch adds APFloat type support for the E2M1 FP4 datatype. The definitions for this format are detailed in section 5.3.3 of the OCP specification, which can be accessed here: https://www.opencompute.org/

[clang] [llvm] [APFloat] Add APFloat support for FP6 data types (PR #94735)

https://github.com/durga4github closed https://github.com/llvm/llvm-project/pull/94735 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [APFloat] Add APFloat support for FP6 data types (PR #94735)

durga4github wrote: There is one test failure in Codegen/LoongArch/opt-pipeline.ll and it does not seem related to my changes here. So, merging this change. https://github.com/llvm/llvm-project/pull/94735 ___ cfe-commits mailing list cfe-commits@lists

[clang] [llvm] [APFloat] Add APFloat support for FP6 data types (PR #94735)

@@ -68,6 +68,10 @@ enum class fltNonfiniteBehavior { // `fltNanEncoding` enum. We treat all NaNs as quiet, as the available // encodings do not distinguish between signalling and quiet NaN. NanOnly, + + // This behavior is present in Float6E3M2FN and Float6E2M3FN types.

[clang] [llvm] [APFloat] Add APFloat support for FP6 data types (PR #94735)

https://github.com/durga4github updated https://github.com/llvm/llvm-project/pull/94735 >From 2ee13938a4428948ae6fdeb82de6e0c15e2dd9f8 Mon Sep 17 00:00:00 2001 From: Durgadoss R Date: Wed, 5 Jun 2024 19:22:31 +0530 Subject: [PATCH] [APFloat] Add APFloat support for FP6 data types This patch ad

[clang] [llvm] [APFloat] Add APFloat support for FP6 data types (PR #94735)

@@ -68,6 +68,10 @@ enum class fltNonfiniteBehavior { // `fltNanEncoding` enum. We treat all NaNs as quiet, as the available // encodings do not distinguish between signalling and quiet NaN. NanOnly, + + // This behavior is present in Float6E3M2FN and Float6E2M3FN types.

[clang] [llvm] [APFloat] Add APFloat support for FP6 data types (PR #94735)

@@ -139,6 +143,10 @@ static constexpr fltSemantics semFloat8E4M3FNUZ = { static constexpr fltSemantics semFloat8E4M3B11FNUZ = { 4, -10, 4, 8, fltNonfiniteBehavior::NanOnly, fltNanEncoding::NegativeZero}; static constexpr fltSemantics semFloatTF32 = {127, -126, 11, 19}; +sta

[clang] [llvm] [APFloat] Add APFloat support for FP6 data types (PR #94735)

@@ -68,6 +68,10 @@ enum class fltNonfiniteBehavior { // `fltNanEncoding` enum. We treat all NaNs as quiet, as the available // encodings do not distinguish between signalling and quiet NaN. NanOnly, + + // This behavior is present in Float6E3M2FN and Float6E2M3FN types.

[clang] [llvm] [APFloat] Add APFloat support for FP6 data types (PR #94735)

https://github.com/durga4github updated https://github.com/llvm/llvm-project/pull/94735 >From 94b25ae304a102cc8c0196f3ca6c460dd4de7026 Mon Sep 17 00:00:00 2001 From: Durgadoss R Date: Wed, 5 Jun 2024 19:22:31 +0530 Subject: [PATCH] [APFloat] Add APFloat support for FP6 data types This patch ad

[clang] [llvm] [APFloat] Add APFloat support for FP6 data types (PR #94735)

https://github.com/durga4github updated https://github.com/llvm/llvm-project/pull/94735 >From 3fd700cb6cf349218558ad8caae081629e01d986 Mon Sep 17 00:00:00 2001 From: Durgadoss R Date: Wed, 5 Jun 2024 19:22:31 +0530 Subject: [PATCH] [APFloat] Add APFloat support for FP6 data types This patch ad

[clang] [llvm] [APFloat] Add APFloat support for FP6 data types (PR #94735)

@@ -1881,6 +1890,20 @@ TEST(APFloatTest, getSmallest) { EXPECT_TRUE(test.isFiniteNonZero()); EXPECT_TRUE(test.isDenormal()); EXPECT_TRUE(test.bitwiseIsEqual(expected)); + + test = APFloat::getSmallest(APFloat::Float6E3M2FN(), false); + expected = APFloat(APFloat::Float6

[clang] [llvm] [APFloat] Add APFloat support for FP6 data types (PR #94735)

@@ -47,6 +47,10 @@ static std::string convertToString(double d, unsigned Prec, unsigned Pad, return std::string(Buffer.data(), Buffer.size()); } +static bool hasNanOrInf(APFloat::Semantics S) { + return (S != APFloat::S_Float6E3M2FN) && (S != APFloat::S_Float6E2M3FN); +} -

[clang] [llvm] [APFloat] Add APFloat support for FP6 data types (PR #94735)

https://github.com/durga4github updated https://github.com/llvm/llvm-project/pull/94735 >From 44b05720e7abe2344925158f7b76904990155500 Mon Sep 17 00:00:00 2001 From: Durgadoss R Date: Wed, 5 Jun 2024 19:22:31 +0530 Subject: [PATCH] [APFloat] Add APFloat support for FP6 data types This patch ad

[clang] [llvm] [APFloat] Add APFloat support for FP6 data types (PR #94735)

durga4github wrote: @ThomasRaoux , Could you please help review this change? https://github.com/llvm/llvm-project/pull/94735 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [APFloat] Add APFloat support for FP6 data types (PR #94735)

https://github.com/durga4github updated https://github.com/llvm/llvm-project/pull/94735 >From ac137c57ee35e1662b40796637eb4b25aa773849 Mon Sep 17 00:00:00 2001 From: Durgadoss R Date: Wed, 5 Jun 2024 19:22:31 +0530 Subject: [PATCH] [APFloat] Add APFloat support for FP6 data types This patch ad

[clang] [llvm] [APFloat] Add APFloat support for FP6 data types (PR #94735)

https://github.com/durga4github created https://github.com/llvm/llvm-project/pull/94735 This patch adds APFloat type support for two FP6 data types, E2M3 and E3M2. The definitions for the two formats are detailed in section 5.3.2 of the OCP specification, which can be accessed here: https://www.