[PATCH] D159188: [AArch64][SME] Make the overloaded svreinterpret_* functions streaming-compatible.

david-arm added inline comments. Comment at: clang/include/clang/Basic/Attr.td:418 def TargetARM : TargetArch<["arm", "thumb", "armeb", "thumbeb"]>; -def TargetAArch64 : TargetArch<["aarch64"]>; +def TargetAArch64 : TargetArch<["aarch64", "aarch64_be"]>; def TargetAnyArm : Targ

[PATCH] D156115: [Clang][SVE] Permit specific predicate-as-counter registers in inline assembly

This revision was landed with ongoing or failed builds. This revision was automatically updated to reflect the committed changes. Closed by commit rG4cf11d8a65df: [Clang][SVE] Permit specific predicate-as-counter registers in inline assembly (authored by david-arm). Repository: rG LLVM Github M

[PATCH] D156115: [Clang][SVE] Permit specific predicate-as-counter registers in inline assembly

david-arm updated this revision to Diff 543529. david-arm added a comment. - Addressed review comments on tests CHANGES SINCE LAST ACTION https://reviews.llvm.org/D156115/new/ https://reviews.llvm.org/D156115 Files: clang/lib/Basic/Targets/AArch64.cpp clang/test/CodeGen/aarch64-sve-inlin

[PATCH] D156115: [Clang][SVE] Permit specific predicate-as-counter registers in inline assembly

david-arm created this revision. david-arm added reviewers: sdesmalen, MattDevereau, hassnaa-arm. Herald added subscribers: ctetreau, psnobl, kristof.beyls. Herald added a reviewer: efriedma. Herald added a project: All. david-arm requested review of this revision. Herald added a project: clang. He

[PATCH] D151461: [Clang][SVE2.1] Add builtins and intrinsics for SVBFMLSLB/T

david-arm accepted this revision. david-arm added a comment. This revision is now accepted and ready to land. LGTM! I left a nit, which you could just address before landing the patch? Comment at: clang/test/CodeGen/aarch64-sve2p1-intrinsics/acle_sve2p1_bfmlsl.c:48 +// +svfloat

[PATCH] D150953: [Clang][SVE2.1] Add clang support for prototypes using svcount_t

david-arm accepted this revision. david-arm added a comment. This revision is now accepted and ready to land. LGTM! Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D150953/new/ https://reviews.llvm.org/D150953

[PATCH] D127910: [Clang][AArch64][SME] Add vector load/store (ld1/st1) intrinsics

david-arm added a comment. Thanks a lot for making all the changes @bryanpkc - it's looking really good now! I just have a few minor comments/suggestions and then I think it looks good to go. Comment at: clang/include/clang/Basic/arm_sme.td:22 +let TargetGuard = "sme" in { +

[PATCH] D127910: [Clang][AArch64][SME] Add vector load/store (ld1/st1) intrinsics

david-arm added a comment. Hi @bryanpkc, this is looking a lot better now and thanks for addressing the comments! I've not reviewed all of the patch yet, but I do have a few more comments. The most important ones are about performing immediate range checks for the builtins and not declaring the

[PATCH] D141056: [SVE][CGBuiltins] Remove need for instcombine from ACLE tests.

david-arm accepted this revision. david-arm added a comment. This revision is now accepted and ready to land. LGTM! Thanks for making the changes @paulwalker-arm. :) Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D141056/new/ https://reviews.llvm.org

[PATCH] D141056: [SVE][CGBuiltins] Remove need for instcombine from ACLE tests.

david-arm added inline comments. Comment at: clang/lib/CodeGen/CGBuiltin.cpp:9092 + if (BytesPerElt > 1) { +Value *Scale = ConstantInt::get(Int64Ty, Log2_32(BytesPerElt)); +Ops[2] = Builder.CreateShl(Ops[2], Scale); Given this seems a frequen

[PATCH] D140983: [IRBuilder] Use canonical i64 type for insertelement index used by vector splats.

david-arm accepted this revision. david-arm added a comment. This revision is now accepted and ready to land. LGTM! The change seems sensible to me, although perhaps worth waiting a day or two in case anyone else has objections? I noticed that we still create inserts using 32-bit indices in a fe

[PATCH] D138788: [SVE] Change some bfloat lane intrinsics to use i32 immediates

This revision was landed with ongoing or failed builds. This revision was automatically updated to reflect the committed changes. Closed by commit rGbfb6f47e9ea4: [SVE] Change some bfloat lane intrinsics to use i32 immediates (authored by david-arm). Changed prior to commit: https://reviews.llv

[PATCH] D138788: [SVE] Change some bfloat lane intrinsics to use i32 immediates

david-arm updated this revision to Diff 480451. david-arm added a comment. I did try to avoid having to create an intrinsic with a different name, but I was thwarted at every turn! It is with great regret that I report these two problems: 1. When you write an IR test file containing a declarati

[PATCH] D138788: [SVE] Change some bfloat lane intrinsics to use i32 immediates

david-arm marked an inline comment as done. david-arm added inline comments. Comment at: llvm/include/llvm/IR/IntrinsicsAArch64.td:2527 -def int_aarch64_sve_bfdot_lane : SVE_4Vec_BF16_Indexed; -def int_aarch64_sve_bfmlalb_lane : SVE_4Vec_BF16_Indexed; -def int_aarch64_sve_bfm

[PATCH] D138788: [SVE] Change some bfloat lane intrinsics to use i32 immediates

david-arm marked an inline comment as done. david-arm added inline comments. Comment at: llvm/include/llvm/IR/IntrinsicsAArch64.td:2527 -def int_aarch64_sve_bfdot_lane : SVE_4Vec_BF16_Indexed; -def int_aarch64_sve_bfmlalb_lane : SVE_4Vec_BF16_Indexed; -def int_aarch64_sve_bfm

[PATCH] D138788: [SVE] Change some bfloat lane intrinsics to use i32 immediates

david-arm updated this revision to Diff 478868. david-arm added a comment. - Actually done the upgrade stuff properly this time. :) CHANGES SINCE LAST ACTION https://reviews.llvm.org/D138788/new/ https://reviews.llvm.org/D138788 Files: clang/include/clang/Basic/arm_sve.td clang/test/Code

[PATCH] D138788: [SVE] Change some bfloat lane intrinsics to use i32 immediates

david-arm updated this revision to Diff 478494. david-arm edited the summary of this revision. david-arm added a comment. - Changed patch to use autoupgrade mechanism. CHANGES SINCE LAST ACTION https://reviews.llvm.org/D138788/new/ https://reviews.llvm.org/D138788 Files: clang/include/clan

[PATCH] D138788: [SVE] Change some bfloat lane intrinsics to use i32 immediates

david-arm created this revision. david-arm added reviewers: sdesmalen, paulwalker-arm, kmclaughlin. Herald added subscribers: ctetreau, psnobl, hiraditya, tschuett. Herald added a reviewer: efriedma. Herald added a project: All. david-arm requested review of this revision. Herald added projects: cl

[PATCH] D127910: [Clang][AArch64] Add SME C intrinsics for load and store

david-arm added a comment. Hi @sagarkulkarni19, just a gentle ping to see if you are still planning to do more work on this patch? Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D127910/new/ https://reviews.llvm.org/D127910

[PATCH] D127910: [Clang][AArch64] Add SME C intrinsics for load and store

david-arm added a comment. Hi @sagarkulkarni19, thank you for working on the ACLE builtins for SME! I've had a look through and I have a few comments, mostly around how the code is structured. It would be good if you could try to separate SVE from SME in this implementation, in the same way tha

[PATCH] D134352: [AArch64] Add Neoverse V2 CPU support

This revision was landed with ongoing or failed builds. This revision was automatically updated to reflect the committed changes. david-arm marked 3 inline comments as done. Closed by commit rGfbb119412f14: [AArch64] Add Neoverse V2 CPU support (authored by david-arm). Changed prior to commit:

[PATCH] D134352: [AArch64] Add Neoverse V2 CPU support

david-arm marked 3 inline comments as done. david-arm added inline comments. Comment at: llvm/include/llvm/Support/AArch64TargetParser.def:239 +AARCH64_CPU_NAME("neoverse-v2", ARMV9A, FK_NEON_FP_ARMV8, false, + (AArch64::AEK_SVE | AArch64::AEK_SVE2 | AArch64::AEK_

[PATCH] D134352: [AArch64] Add Neoverse V2 CPU support

david-arm updated this revision to Diff 462833. david-arm added a comment. - Added SVE2BITPERM to AArch64TargetParser.def and updated the unit test. CHANGES SINCE LAST ACTION https://reviews.llvm.org/D134352/new/ https://reviews.llvm.org/D134352 Files: clang/docs/ReleaseNotes.rst clang/t

[PATCH] D134352: [AArch64] Add Neoverse V2 CPU support

david-arm updated this revision to Diff 462420. david-arm added a comment. - Added AEK_MTE to target parser flags. CHANGES SINCE LAST ACTION https://reviews.llvm.org/D134352/new/ https://reviews.llvm.org/D134352 Files: clang/docs/ReleaseNotes.rst clang/test/Driver/aarch64-mcpu.c clang/

[PATCH] D134352: [AArch64] Add Neoverse V2 CPU support

david-arm added inline comments. Comment at: llvm/lib/Target/AArch64/AArch64.td:1112 + FeatureNEON, FeatureSVE2BitPerm, FeatureFP16FML, + FeatureMTE, FeatureRandGen]; list Saphira= [HasV8_4aOps, F

[PATCH] D134352: [AArch64] Add Neoverse V2 CPU support

david-arm added a comment. In D134352#3806896 , @tschuett wrote: > `VScaleForTuning` is 1 for N2 and V2. It is 2 for V1. I though the V2 is more > like the V1 than the N2? > Sorry. This is throughput right? Hi @tschuett, Neoverse V2 will have 128-bit SV

[PATCH] D134352: [AArch64] Add Neoverse V2 CPU support

david-arm updated this revision to Diff 462124. david-arm added a comment. - Added FEAT_RNG to the neoverse-v2 CPU. - Added message to release notes. CHANGES SINCE LAST ACTION https://reviews.llvm.org/D134352/new/ https://reviews.llvm.org/D134352 Files: clang/docs/ReleaseNotes.rst clang/

[PATCH] D134352: [AArch64] Add Neoverse V2 CPU support

david-arm marked 3 inline comments as done. david-arm added a comment. Thanks for the quick review @dmgreen! CHANGES SINCE LAST ACTION https://reviews.llvm.org/D134352/new/ https://reviews.llvm.org/D134352 ___ cfe-commits mailing list cfe-commits@l

[PATCH] D134352: [AArch64] Add Neoverse V2 CPU support

david-arm updated this revision to Diff 461898. david-arm added a comment. - Changed lists of tuning features. - Removed redundant arch features from list. - Combined neoverse-v2 and neoverse-n2 cases together in AArch64Subtarget. CHANGES SINCE LAST ACTION https://reviews.llvm.org/D134352/new/

[PATCH] D134352: [AArch64] Add Neoverse V2 CPU support

david-arm created this revision. david-arm added reviewers: sdesmalen, paulwalker-arm, dmgreen, MarkMurrayARM, CarolineConcatto. Herald added subscribers: hiraditya, kristof.beyls. Herald added a project: All. david-arm requested review of this revision. Herald added projects: clang, LLVM. Herald

[PATCH] D129137: [NFC][LoopVectorize] Explicitly disable tail-folding on some SVE tests

This revision was landed with ongoing or failed builds. This revision was automatically updated to reflect the committed changes. Closed by commit rGceb6c23b708d: [NFC][LoopVectorize] Explicitly disable tail-folding on some SVE tests (authored by david-arm). Herald added a project: clang. Herald a

[PATCH] D113394: [IR] In ConstantFoldShuffleVectorInstruction use zeroinitializer for splats of 0

This revision was automatically updated to reflect the committed changes. david-arm marked an inline comment as done. Closed by commit rG2a48b6993a97: [IR] In ConstantFoldShuffleVectorInstruction use zeroinitializer for splats of 0 (authored by david-arm). Herald added a project: clang. Herald add

[PATCH] D110258: [AArch64] Always add -tune-cpu argument to -cc1 driver

This revision was landed with ongoing or failed builds. This revision was automatically updated to reflect the committed changes. Closed by commit rG607fb1bb8c91: [AArch64] Always add -tune-cpu argument to -cc1 driver (authored by david-arm). Changed prior to commit: https://reviews.llvm.org/D1

[PATCH] D110258: [AArch64] Always add -tune-cpu argument to -cc1 driver

david-arm updated this revision to Diff 380663. CHANGES SINCE LAST ACTION https://reviews.llvm.org/D110258/new/ https://reviews.llvm.org/D110258 Files: clang/docs/ReleaseNotes.rst clang/lib/Driver/ToolChains/Clang.cpp clang/test/Driver/aarch64-mtune.c llvm/docs/ReleaseNotes.rst llvm/

[PATCH] D110258: [AArch64] Always add -tune-cpu argument to -cc1 driver

david-arm added inline comments. Comment at: clang/test/Driver/aarch64-mtune.c:5 +// RUN: %clang -target aarch64-unknown-unknown -c -### %s 2>&1 \ +// RUN: | FileCheck %s -check-prefix=notune +// notune-NOT: "-tune-cpu" "generic" sdesmalen wrote: > nit: Did you

[PATCH] D110258: [AArch64] Always add -tune-cpu argument to -cc1 driver

david-arm updated this revision to Diff 380649. david-arm added a comment. - Added release notes for both clang and llvm. CHANGES SINCE LAST ACTION https://reviews.llvm.org/D110258/new/ https://reviews.llvm.org/D110258 Files: clang/docs/ReleaseNotes.rst clang/lib/Driver/ToolChains/Clang.

[PATCH] D110258: [AArch64] Always add -tune-cpu argument to -cc1 driver

david-arm updated this revision to Diff 380325. david-arm added a comment. - Added something to the ReleaseNotes file. CHANGES SINCE LAST ACTION https://reviews.llvm.org/D110258/new/ https://reviews.llvm.org/D110258 Files: clang/lib/Driver/ToolChains/Clang.cpp clang/test/Driver/aarch64-m

[PATCH] D110258: [AArch64] Always add -tune-cpu argument to -cc1 driver

david-arm added a comment. In D110258#3055488 , @dmgreen wrote: > If D111551 was folded into this patch, > would it be possible to add tests for -tune-cpu enabling/disabling features > at the correct times? Similar to

[PATCH] D110258: [AArch64] Always add -tune-cpu argument to -cc1 driver

david-arm added a comment. Gentle ping! CHANGES SINCE LAST ACTION https://reviews.llvm.org/D110258/new/ https://reviews.llvm.org/D110258 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-com

[PATCH] D110258: [AArch64] Always add -tune-cpu argument to -cc1 driver

david-arm updated this revision to Diff 378180. david-arm marked an inline comment as done. david-arm added a comment. - Fixed formatting issues. CHANGES SINCE LAST ACTION https://reviews.llvm.org/D110258/new/ https://reviews.llvm.org/D110258 Files: clang/lib/Driver/ToolChains/Clang.cpp

[PATCH] D110258: [AArch64] Always add -tune-cpu argument to -cc1 driver

david-arm added a comment. Hi @dmgreen, would you be happy for me to do the splitting-out of arch and tuning features in a separate follow-on patch? I think it's a good idea and I don't object to doing it, but I'm not sure that it really needs to hold up this initial patch? I personally think i

[PATCH] D110258: [AArch64] Always add -tune-cpu argument to -cc1 driver

david-arm added a comment. In D110258#3023818 , @dmgreen wrote: > Sounds great. Glad to see us taking this route. > > Unfortunately I think we do need to split the subtargetfeatures up into arch > flags and tune flags. Same for the details in > AArch64

[PATCH] D110258: [AArch64] Always add -tune-cpu argument to -cc1 driver

david-arm updated this revision to Diff 375169. david-arm retitled this revision from "[AArch64][Clang] Always add -tune-cpu argument to -cc1 driver" to "[AArch64] Always add -tune-cpu argument to -cc1 driver". david-arm edited the summary of this revision. david-arm added a comment. Herald added

[PATCH] D110258: [AArch64][Clang] Always add -tune-cpu argument to -cc1 driver

david-arm added a comment. Hi @dmgreen, this is specifically being introduced for SVE targets to help make informed cost model decisions regarding the value of vscale - see D110259 . We thought that using the "tune-cpu" attribute might be a good way of doing th

[PATCH] D110258: [AArch64][Clang] Always add -tune-cpu argument to -cc1 driver

david-arm created this revision. david-arm added reviewers: sdesmalen, c-rhodes, peterwaller-arm, dmgreen. Herald added a subscriber: kristof.beyls. david-arm requested review of this revision. Herald added a project: clang. Herald added a subscriber: cfe-commits. This patch ensures that we always

[PATCH] D109883: [Analysis] Add support for vscale in computeKnownBitsFromOperator

This revision was landed with ongoing or failed builds. This revision was automatically updated to reflect the committed changes. Closed by commit rGf988f680649a: [Analysis] Add support for vscale in computeKnownBitsFromOperator (authored by david-arm). Herald added a project: clang. Herald added

[PATCH] D107764: [OpenMP][OpenMPIRBuilder] Implement loop unrolling.

david-arm added a comment. Hi, this has broken the build for me too. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D107764/new/ https://reviews.llvm.org/D107764 ___ cfe-commits mailing list cfe-commits@li

[PATCH] D108138: [SimplifyCFG] Remove switch statements before vectorization

david-arm added a comment. In D108138#2967133 , @lebedev.ri wrote: > How is it conceptually different to break apart IR in LV itself, or do the > same in a special pass just before that? > If we want to go this road, we need to completely make `switch`e

[PATCH] D108138: [SimplifyCFG] Remove switch statements before vectorization

david-arm added a comment. In D108138#2967100 , @lebedev.ri wrote: > IMO anything other than enhancing LV is wrong. Hi @lebedev.ri I personally disagree here. Adding support to LV for this is significantly more work (and IMO unnecessary) because there

[PATCH] D108138: [SimplifyCFG] Remove switch statements before vectorization

david-arm added a comment. In D108138#2948975 , @dmgreen wrote: >> I'm under the impression that the vectoriser has a policy of never making >> scalar transformations > > I'm not sure what you mean. I've not looked into the details, but it could > presu

[PATCH] D108138: [SimplifyCFG] Remove switch statements before vectorization

david-arm added a comment. In D108138#2947229 , @lebedev.ri wrote: > I'm not sure i'm sold on this, even though i'm aware that selects hurt > vectorization. > How does this Simplify the CFG? I think it would be best to teach LV selects, > or at worst do

[PATCH] D104852: [AArch64][SVEIntrinsicOpts] Convect cntb/h/w/d to vscale intrinsic or constant.

david-arm accepted this revision. david-arm added a comment. This revision is now accepted and ready to land. LGTM! Thanks a lot for making the changes. :) Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D104852/new/ https://reviews.llvm.org/D104852

[PATCH] D104852: [AArch64][SVEIntrinsicOpts] Convect cntb/h/w/d to vscale intrinsic or constant.

david-arm added inline comments. Comment at: llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp:671 + case AArch64SVEPredPattern::vl8: +return NumElts >= Pattern + ? Optional(IC.replaceInstUsesWith( I was actually wondering if we could comm

[PATCH] D104852: [AArch64][SVEIntrinsicOpts] Convect cntb/h/w/d to vscale intrinsic or constant.

david-arm added a comment. Hi @junparser, the patch looks sensible to me! I just had a couple of minor comments if that's ok. Comment at: llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp:658 +return IC.replaceInstUsesWith(II, VScale); + } else if (Pattern >= AArch64

[PATCH] D96270: [release][docs] Update contributions to LLVM 12 for scalable vectors.

david-arm closed this revision. david-arm added a comment. Merged to LLVM Release 12.x branch CHANGES SINCE LAST ACTION https://reviews.llvm.org/D96270/new/ https://reviews.llvm.org/D96270 ___ cfe-commits mailing list cfe-commits@lists.llvm.org htt

[PATCH] D96270: [release][docs] Update contributions to LLVM 12 for scalable vectors.

david-arm updated this revision to Diff 322316. CHANGES SINCE LAST ACTION https://reviews.llvm.org/D96270/new/ https://reviews.llvm.org/D96270 Files: clang/docs/ReleaseNotes.rst Index: clang/docs/ReleaseNotes.rst === --- clang

[PATCH] D96270: [release][docs] Update contributions to LLVM 12 for scalable vectors.

david-arm created this revision. david-arm added reviewers: sdesmalen, willlovett, c-rhodes. david-arm requested review of this revision. Herald added a project: clang. Herald added a subscriber: cfe-commits. Repository: rG LLVM Github Monorepo https://reviews.llvm.org/D96270 Files: clang/do

[PATCH] D89031: [SVE] Add support to vectorize_width loop pragma for scalable vectors

This revision was automatically updated to reflect the committed changes. Closed by commit rG38d18d93534d: [SVE] Add support to vectorize_width loop pragma for scalable vectors (authored by david-arm). Changed prior to commit: https://reviews.llvm.org/D89031?vs=315121&id=315341#toc Repository:

[PATCH] D89031: [SVE] Add support to vectorize_width loop pragma for scalable vectors

david-arm updated this revision to Diff 315121. david-arm added a comment. - Updated documentation as per review comments. - Fixed an issue with using value->prettyPrint on a null ptr. - Reworked the code that sets vectorize.enable. CHANGES SINCE LAST ACTION https://reviews.llvm.org/D89031/new

[PATCH] D89031: [SVE] Add support to vectorize_width loop pragma for scalable vectors

david-arm added inline comments. Comment at: clang/lib/CodeGen/CGLoopInfo.cpp:751-753 + // they effectively want vectorization disabled. We leave the + // scalable flag unspecified in this case to avoid setting the + // vectorize.enable flag later on. -

[PATCH] D89031: [SVE] Add support to vectorize_width loop pragma for scalable vectors

david-arm added a comment. Hi everyone, I realise that most people have probably been on holiday recently, but just a gentle ping here to see if anyone could take another look? Thanks! CHANGES SINCE LAST ACTION https://reviews.llvm.org/D89031/new/ https://reviews.llvm.org/D89031 ___

[PATCH] D89031: [SVE] Add support to vectorize_width loop pragma for scalable vectors

david-arm added inline comments. Comment at: clang/include/clang/Basic/Attr.td:3356 EnumArgument<"State", "LoopHintState", - ["enable", "disable", "numeric", "assume_safety", "full"], - ["Enable", "Disable", "Num

[PATCH] D89031: [SVE] Add support to vectorize_width loop pragma for scalable vectors

david-arm updated this revision to Diff 312802. david-arm edited the summary of this revision. Herald added a subscriber: NickHung. CHANGES SINCE LAST ACTION https://reviews.llvm.org/D89031/new/ https://reviews.llvm.org/D89031 Files: clang/docs/LanguageExtensions.rst clang/include/clang/Ba

[PATCH] D89031: [SVE] Add support to vectorize_width loop pragma for scalable vectors

david-arm added a comment. Hi @SjoerdMeijer I think that given we now support scalable vectors we thought it made sense to be able to specify whether the user wants 'fixed' or 'scalable' vectorisation along with the vector width, although without specifying the additional property the default c

[PATCH] D89031: [SVE] Add support to vectorize_width loop pragma for scalable vectors

david-arm updated this revision to Diff 304488. CHANGES SINCE LAST ACTION https://reviews.llvm.org/D89031/new/ https://reviews.llvm.org/D89031 Files: clang/docs/LanguageExtensions.rst clang/include/clang/Basic/Attr.td clang/include/clang/Basic/DiagnosticParseKinds.td clang/include/clan

[PATCH] D89031: [SVE] Add support to vectorize_width loop pragma for scalable vectors

david-arm added a comment. I'll hold off on any more changes for now to give @fhahn a chance to reply to your comment @sdesmalen about the fallback behaviour when scalable vectorisation is unsupported. Comment at: clang/include/clang/Basic/DiagnosticSemaKinds.td:939 +def warn

[PATCH] D89031: [SVE] Add support to vectorize_width loop pragma for scalable vectors

david-arm updated this revision to Diff 302773. david-arm marked an inline comment as done. david-arm edited the summary of this revision. CHANGES SINCE LAST ACTION https://reviews.llvm.org/D89031/new/ https://reviews.llvm.org/D89031 Files: clang/docs/LanguageExtensions.rst clang/include/c

[PATCH] D90230: [SVE] Add fatal error for unnamed SVE variadic arguments

This revision was automatically updated to reflect the committed changes. Closed by commit rGcea69fa4dcc4: [SVE] Add fatal error for unnamed SVE variadic arguments (authored by david-arm). Herald added a project: clang. Herald added a subscriber: cfe-commits. Repository: rG LLVM Github Monorepo

[PATCH] D89031: [SVE] Add support to vectorize_width loop pragma for scalable vectors

david-arm marked an inline comment as done. david-arm added inline comments. Comment at: clang/lib/Sema/SemaStmtAttr.cpp:144 + assert(ValueExpr && "Attribute must have a valid value expression."); + if (S.CheckLoopHintExpr(ValueExpr, St->getBeginLoc())) +return

[PATCH] D89031: [SVE] Add support to vectorize_width loop pragma for scalable vectors

david-arm updated this revision to Diff 299014. david-arm added a comment. - Rebase. CHANGES SINCE LAST ACTION https://reviews.llvm.org/D89031/new/ https://reviews.llvm.org/D89031 Files: clang/docs/LanguageExtensions.rst clang/include/clang/Basic/Attr.td clang/include/clang/Basic/Diagn

[PATCH] D89031: [SVE] Add support to vectorize_width loop pragma for scalable vectors

david-arm created this revision. david-arm added reviewers: sdesmalen, ctetreau, fhahn, c-rhodes. Herald added subscribers: cfe-commits, psnobl, tschuett. Herald added a reviewer: efriedma. Herald added a reviewer: aaron.ballman. Herald added a project: clang. david-arm requested review of this rev

[PATCH] D87700: [SVE] Replace / operator in TypeSize/ElementCount with divideCoefficientBy

This revision was automatically updated to reflect the committed changes. Closed by commit rGbafdd11326a4: [SVE] Replace / operator in TypeSize/ElementCount with divideCoefficientBy (authored by david-arm). Herald added a project: clang. Herald added a subscriber: cfe-commits. Changed prior to co

[PATCH] D86720: [clang][aarch64] Drop experimental from __ARM_FEATURE_SVE_BITS macro

david-arm accepted this revision. david-arm added a comment. This revision is now accepted and ready to land. LGTM Comment at: clang/lib/Basic/Targets/AArch64.cpp:381 if (Opts.ArmSveVectorBits) -Builder.defineMacro("__ARM_FEATURE_SVE_BITS_EXPERIMENTAL", +Builder.defi

[PATCH] D86065: [SVE] Make ElementCount members private

This revision was automatically updated to reflect the committed changes. Closed by commit rGf4257c5832aa: [SVE] Make ElementCount members private (authored by david-arm). Changed prior to commit: https://reviews.llvm.org/D86065?vs=288370&id=288594#toc Repository: rG LLVM Github Monorepo CH

[PATCH] D86065: [SVE] Make ElementCount members private

david-arm updated this revision to Diff 288370. david-arm added a comment. - Removed isPowerOf2() function since this is potentially misleading - it's only the known minimum value that we're checking. - Renamed isEven to isKnownEven to try and make it clear that returning true indicates we know

[PATCH] D86065: [SVE] Make ElementCount members private

david-arm added inline comments. Comment at: llvm/include/llvm/Support/TypeSize.h:108 + + bool isPowerOf2() const { return isPowerOf2_32(Min); } }; paulwalker-arm wrote: > I don't believe this is safe. For example we know SVE supported vector > lengths only h

[PATCH] D86065: [SVE] Make ElementCount members private

david-arm updated this revision to Diff 288260. david-arm edited the summary of this revision. CHANGES SINCE LAST ACTION https://reviews.llvm.org/D86065/new/ https://reviews.llvm.org/D86065 Files: clang/lib/CodeGen/CGBuiltin.cpp clang/lib/CodeGen/CodeGenTypes.cpp llvm/include/llvm/Analys

[PATCH] D86065: [SVE] Make ElementCount members private

david-arm added a comment. Hi @ctetreau, ok for now I'm going to completely remove the operators and revert the code using those operators to how it was before. I'm not sure what you mean about the predicate functions so I've left those for now, since they aren't needed for this patch. The purp

[PATCH] D86065: [SVE] Make ElementCount members private

david-arm updated this revision to Diff 287672. david-arm added a comment. Herald added a subscriber: rogfer01. - Changed comparison function from gt to ogt and added a olt (less than) comparison function too. - Instead of adding the ">>=" operator I've added "/=" instead as I think this is more

[PATCH] D86065: [SVE] Make ElementCount members private

david-arm added a comment. Hi @fpetrogalli, if you don't mind I think I'll stick with Paul's idea for ogt because this matches the IR neatly, i.e. "fcmp ogt". Also, for me personally it's much simpler and more intuitive. CHANGES SINCE LAST ACTION https://reviews.llvm.org/D86065/new/ https:/

[PATCH] D86065: [SVE] Make ElementCount members private

david-arm updated this revision to Diff 287003. CHANGES SINCE LAST ACTION https://reviews.llvm.org/D86065/new/ https://reviews.llvm.org/D86065 Files: clang/lib/CodeGen/CGBuiltin.cpp clang/lib/CodeGen/CodeGenTypes.cpp llvm/include/llvm/Analysis/VectorUtils.h llvm/include/llvm/CodeGen/Va

[PATCH] D86065: [SVE] Make ElementCount members private

david-arm added a comment. Hi @ctetreau, I agree with @efriedma that keeping the two classes distinct for now seems best. The reason is I spent quite a lot of time trying to unify these classes already and I hit a stumbling block - TypeSize has the ugly uint64_t() cast operator, which makes uni

[PATCH] D85977: [release][docs] Update contributions to LLVM 11 for SVE.

david-arm added inline comments. Comment at: llvm/docs/ReleaseNotes.rst:70 + ``VFDatabase`` class. When scanning through the set of vector + functions associated to a scalar call, the loop vectorizer now + relies on ``VFDatabase``, instead of ``TargetLibraryInfo``. ---

[PATCH] D86065: [SVE] Make ElementCount members private

david-arm created this revision. david-arm added reviewers: sdesmalen, ctetreau, efriedma, fpetrogalli, kmclaughlin, c-rhodes. Herald added subscribers: llvm-commits, cfe-commits, psnobl, hiraditya, tschuett. Herald added projects: clang, LLVM. david-arm requested review of this revision. This p

[PATCH] D85743: [CodeGen][AArch64] Support arm_sve_vector_bits attribute

david-arm added inline comments. Comment at: clang/lib/CodeGen/CGCall.cpp:1342 + if (SrcSize.getKnownMinSize() <= DstSize.getKnownMinSize() || + (isa(SrcTy) || + isa(DstTy))) { I think if you restructure the code here you could do: if (isa(SrcTy) ||

[PATCH] D82943: [SVE] Add more warnings checks to clang and LLVM SVE tests

This revision was not accepted when it landed; it landed in state "Needs Review". This revision was automatically updated to reflect the committed changes. Closed by commit rG9a1a7d888b53: [SVE] Add more warnings checks to clang and LLVM SVE tests (authored by david-arm). Repository: rG LLVM G

[PATCH] D82943: [SVE] Add more warnings checks to clang and LLVM SVE tests

This revision was automatically updated to reflect the committed changes. Closed by commit rG9a1a7d888b53: [SVE] Add more warnings checks to clang and LLVM SVE tests (authored by david-arm). Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D82943/new/ h

[PATCH] D82943: [SVE] Add more warnings checks to clang and LLVM SVE tests

david-arm created this revision. david-arm added reviewers: sdesmalen, ctetreau, kmclaughlin. Herald added subscribers: llvm-commits, cfe-commits, psnobl, arphaman, rkruppe, tschuett. Herald added a reviewer: rengolin. Herald added a reviewer: efriedma. Herald added projects: clang, LLVM. There a

[PATCH] D82746: [CodeGen] Fix warning in getNode for EXTRACT_SUBVECTOR

This revision was automatically updated to reflect the committed changes. Closed by commit rGc02332a69399: [CodeGen] Fix warning in getNode for EXTRACT_SUBVECTOR (authored by david-arm). Herald added a project: clang. Herald added a subscriber: cfe-commits. Changed prior to commit: https://revi

[PATCH] D82501: [sve][acle] Add reinterpret intrinsics for brain float.

david-arm accepted this revision. david-arm added a comment. This revision is now accepted and ready to land. Can you remove the duplicate tests before submitting? Otherwise LGTM! Comment at: llvm/test/CodeGen/AArch64/sve-bitcast-bfloat.ll:8 + +define @bitcast_bfloat_to_i8( %v

[PATCH] D82501: [sve][acle] Add reinterpret intrinsics for brain float.

david-arm added inline comments. Comment at: clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_reinterpret-bfloat.c:5 + +#include + Hi @fpetrogalli, in the same way that you asked @kmclaughlin if she could add the ASM-NOT check line in her patch, are you able

[PATCH] D82298: [AArch64][SVE] Add bfloat16 support to load intrinsics

david-arm added inline comments. Comment at: clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ldnf1.c:2-4 +// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -D__ARM_FEATURE_BF16_SCALAR_ARITHMETIC -D__ARM_FEATURE_SVE_BF16 -triple aarch64-none-linux-gnu -target-feature +sve -target-featur

[PATCH] D82182: [AArch64][SVE] Add bfloat16 support to perm and select intrinsics

david-arm accepted this revision. david-arm added a comment. This revision is now accepted and ready to land. LGTM! Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D82182/new/ https://reviews.llvm.org/D82182

[PATCH] D80712: [SVE] Add checks for no warnings in SVE tests

david-arm added a comment. Hi @sdesmalen @efriedma , hopefully I've addressed your review comments with my latest patch! CHANGES SINCE LAST ACTION https://reviews.llvm.org/D80712/new/ https://reviews.llvm.org/D80712 ___ cfe-commits mailing list

[PATCH] D79587: [CodeGen][SVE] Legalisation of extends with scalable types

david-arm added a comment. Sorry I forgot to mention I think we have an existing test file for extends: llvm/test/CodeGen/AArch64/sve-sext-zext.ll It might be worth adding these cases to that file instead of creating a new one? CHANGES SINCE LAST ACTION https://reviews.llvm.org/D79587/new/

[PATCH] D79587: [CodeGen][SVE] Legalisation of extends with scalable types

david-arm added a comment. Hi Kerry, just a couple of comments about the use of getVectorNumElements() - we're trying to remove calls to this function so it would be good if you could use getVectorElementCount() instead. Thanks! Comment at: llvm/lib/Target/AArch64/AArch64ISe

[PATCH] D80712: [SVE] Add checks for no warnings in SVE tests

david-arm added a comment. Hi @efriedma, at least amongst all the tests in llvm/test/CodeGen/AArch64/sve-* there are still 66 with warnings. @sdesmalen and I discussed this and our reason for adding checks for warnings is mainly to do with the fact we are still fixing up cases and implementing

[PATCH] D79587: [CodeGen][SVE] Legalisation of extends with scalable types

david-arm added a comment. Hi @efriedma, is there a target-independent equivalent of SUNPKHI? From a quick glance at the codebase where X86 uses ISD::SIGN_EXTEND_VECTOR_INREG it seems vector shuffles are still required for the Hi part, which is fine for fixed length vectors I guess. Repositor

[PATCH] D79587: [CodeGen][SVE] Legalisation of extends with scalable types

david-arm added a comment. Hi Kerry, I think we do already have some suitable test files where perhaps you could add your tests instead of creating new files? For example, there are: CodeGen/AArch64/sve-int-arith.ll (perhaps integer divides and shifts could live there?) CodeGen/AArch64/sve-int-