https://github.com/davemgreen updated
https://github.com/llvm/llvm-project/pull/126945
>From 410d78202cac8221048a83ea466b59cb6e78ea87 Mon Sep 17 00:00:00 2001
From: Tomas Matheson
Date: Wed, 12 Feb 2025 14:31:47 +
Subject: [PATCH 1/2] Add missing Neon Types
The AAPCS64 adds a number of vec
https://github.com/davemgreen edited
https://github.com/llvm/llvm-project/pull/126945
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davemgreen wrote:
I was discussing with @tmatheson-arm and he said I could take this over. I've
updated this branch (apparently that does work), trying to address the issues
and clean things up a bit. The new types are not longer a keyword, but that
seems to be OK providing we mark them as imp
davemgreen wrote:
These two are failing:
Clang.CodeGen/paren-list-agg-init.cpp
Clang.CodeGenCXX/microsoft-abi-throw.cpp
Can you try and fix them? (or remove them from this review and handle them
separately). The others look OK.
https://github.com/llvm/llvm-project/pull/140373
__
@@ -22,7 +22,7 @@ define signext i8 @test1(i32 %A) {
; CHECK-V7: @ %bb.0:
; CHECK-V7-NEXT:sbfx r0, r0, #8, #8
; CHECK-V7-NEXT:bx lr
-; CHECk-V7: sbfx r0, r0, #8, #8
+; CHECK-V7: sbfx r0, r0, #8, #8
davemgreen wrote:
Same here.
https://github.com
@@ -121,7 +121,7 @@ define i32 @test_orr_extract_from_mul_1(i32 %x, i32 %y) {
; CHECK-THUMB-NEXT:orrs r0, r1
; CHECK-THUMB-NEXT:bx lr
entry:
-; CHECk-THUMB: orrs r0, r1
+; CHECK-THUMB: orrs r0, r1
davemgreen wrote:
You can remove this line entirely, th
https://github.com/davemgreen updated
https://github.com/llvm/llvm-project/pull/135064
>From 9a56ee32712c213b0fa06257bda9c2f31ec44416 Mon Sep 17 00:00:00 2001
From: David Green
Date: Thu, 15 May 2025 20:36:44 +0100
Subject: [PATCH] [AArch64] Change the coercion type of structs with pointer
mem
Author: David Green
Date: 2025-05-15T11:51:58+01:00
New Revision: f8f11c541dec9bfc19f80918cf12da71d6ae7b99
URL:
https://github.com/llvm/llvm-project/commit/f8f11c541dec9bfc19f80918cf12da71d6ae7b99
DIFF:
https://github.com/llvm/llvm-project/commit/f8f11c541dec9bfc19f80918cf12da71d6ae7b99.diff
L
https://github.com/davemgreen edited
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davemgreen wrote:
It looks like this came from #122280 / #122716. Sorry about the break, it
should have updated the CPU dependencies correctly too.
LGTM
https://github.com/llvm/llvm-project/pull/139212
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https://github.com/davemgreen edited
https://github.com/llvm/llvm-project/pull/139055
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@@ -1262,7 +1262,7 @@ INSTANTIATE_TEST_SUITE_P(
AArch64CPUAliasTestParams::PrintToStringParamName);
// Note: number of CPUs includes aliases.
-static constexpr unsigned NumAArch64CPUArchs = 89;
+static constexpr unsigned NumAArch64CPUArchs = 90;
davemgreen
https://github.com/davemgreen commented:
Can you add a release-note that this new CPU has been added?
https://github.com/llvm/llvm-project/pull/139055
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https://github.com/llvm/llvm-project/pull/135064
Rate limit · GitHub
body {
background-color: #f6f8fa;
color: #24292e;
font-family: -apple-system,BlinkMacSystemFont,Segoe
UI,Helvetica,Arial,san
https://github.com/davemgreen updated
https://github.com/llvm/llvm-project/pull/135064
>From d9e27ec881ec493174f3aee7a4faec567640e5e8 Mon Sep 17 00:00:00 2001
From: David Green
Date: Wed, 9 Apr 2025 11:18:25 +0100
Subject: [PATCH 1/3] [AArch64] Add a test case for the coerced arguments. NFC
--
davemgreen wrote:
Rebase and ping - thanks.
https://github.com/llvm/llvm-project/pull/135064
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https://github.com/davemgreen closed
https://github.com/llvm/llvm-project/pull/137330
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https://github.com/davemgreen approved this pull request.
Thanks. LGTM
https://github.com/llvm/llvm-project/pull/137330
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@@ -862,7 +862,7 @@ def ProcessorFeatures {
FeatureSB, FeatureSSBS, FeaturePAuth,
FeatureFlagM, FeaturePredRes,
FeatureSVE, FeatureSVE2, FeatureComplxNum,
FeatureCRC, FeatureDotProd,
https://github.com/davemgreen commented:
Hi - I tried this with the latest
https://github.com/gcc-mirror/gcc/blob/master/libstdc%2B%2B-v3/config/cpu/aarch64/opt/ext/opt_random.h
and it seemed to need some fixes and then it might have failed to mangle the
types if they were used? I can provide
@@ -201,6 +201,42 @@ SVE_OPAQUE_TYPE(__SVCount_t, __SVCount_t, SveCount,
SveCountTy)
SVE_SCALAR_TYPE(__mfp8, __mfp8, MFloat8, MFloat8Ty, 8)
+// Unlike the SVE types above, the Neon vector types are parsed as keywords and
+// mapped to the equivalent __attribute__(neon_vector
@@ -201,6 +201,42 @@ SVE_OPAQUE_TYPE(__SVCount_t, __SVCount_t, SveCount,
SveCountTy)
SVE_SCALAR_TYPE(__mfp8, __mfp8, MFloat8, MFloat8Ty, 8)
+// Unlike the SVE types above, the Neon vector types are parsed as keywords and
+// mapped to the equivalent __attribute__(neon_vector
@@ -201,6 +201,42 @@ SVE_OPAQUE_TYPE(__SVCount_t, __SVCount_t, SveCount,
SveCountTy)
SVE_SCALAR_TYPE(__mfp8, __mfp8, MFloat8, MFloat8Ty, 8)
+// Unlike the SVE types above, the Neon vector types are parsed as keywords and
+// mapped to the equivalent __attribute__(neon_vector
@@ -1366,6 +1366,13 @@ static QualType
ConvertDeclSpecToType(TypeProcessingState &state) {
break;
#include "clang/Basic/OpenCLImageTypes.def"
+#define NEON_VECTOR_TYPE(Name, BaseType, ElBits, NumEls, VectorKind)
\
+ case DeclSpec::TST_##Name:
https://github.com/davemgreen edited
https://github.com/llvm/llvm-project/pull/126945
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davemgreen wrote:
@john-brawn-arm did the work for AArch64, I'm not sure if he would have an idea
how much work it would involve for the Arm backend.
https://github.com/llvm/llvm-project/pull/137101
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davemgreen wrote:
I believe the backend would still need work to make sure this is supported,
which has not been done yet. I was expecting it to fail more noisily, but it
appears the strict nodes are lowered to generic nodes. That doesn't mean that
strict-fp is supported by the Arm backend, as
https://github.com/davemgreen updated
https://github.com/llvm/llvm-project/pull/135064
>From 8655b5aff2162bfc13d3f263d6b7830e0186c097 Mon Sep 17 00:00:00 2001
From: David Green
Date: Wed, 9 Apr 2025 11:18:25 +0100
Subject: [PATCH 1/2] [AArch64] Add a test case for the coerced arguments. NFC
--
@@ -485,6 +485,39 @@ ABIArgInfo AArch64ABIInfo::classifyArgumentType(QualType
Ty, bool IsVariadicFn,
}
Size = llvm::alignTo(Size, Alignment);
+// If the Aggregate is made up of pointers, use an array of pointers for
the
+// coerced type. This prevents having
https://github.com/davemgreen updated
https://github.com/llvm/llvm-project/pull/135064
>From 8655b5aff2162bfc13d3f263d6b7830e0186c097 Mon Sep 17 00:00:00 2001
From: David Green
Date: Wed, 9 Apr 2025 11:18:25 +0100
Subject: [PATCH 1/2] [AArch64] Add a test case for the coerced arguments. NFC
--
https://github.com/davemgreen approved this pull request.
Thanks. LGTM
https://github.com/llvm/llvm-project/pull/130623
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@@ -419,6 +419,9 @@ Bug Fixes to Attribute Support
- No longer crashing on ``__attribute__((align_value(N)))`` during template
instantiation when the function parameter type is not a pointer or reference.
(#GH26612)
+- The ``+nosimd`` attribute is now fully supported for AA
https://github.com/davemgreen edited
https://github.com/llvm/llvm-project/pull/130623
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https://github.com/davemgreen updated
https://github.com/llvm/llvm-project/pull/135064
>From 33a204bcc884178971c4327528b1e3b75336914e Mon Sep 17 00:00:00 2001
From: David Green
Date: Wed, 9 Apr 2025 11:18:25 +0100
Subject: [PATCH 1/6] [AArch64] Add a test case for the coerced arguments. NFC
--
@@ -679,21 +679,17 @@ llvm::ARM::FPUKind arm::getARMTargetFeatures(const Driver
&D,
CPUArgFPUKind != llvm::ARM::FK_INVALID ? CPUArgFPUKind :
ArchArgFPUKind;
(void)llvm::ARM::getFPUFeatures(FPUKind, Features);
} else {
-bool Generic = true;
-if (!ForAS) {
https://github.com/davemgreen updated
https://github.com/llvm/llvm-project/pull/135064
>From 33a204bcc884178971c4327528b1e3b75336914e Mon Sep 17 00:00:00 2001
From: David Green
Date: Wed, 9 Apr 2025 11:18:25 +0100
Subject: [PATCH 1/5] [AArch64] Add a test case for the coerced arguments. NFC
--
@@ -38,6 +38,9 @@ Potentially Breaking Changes
- Fix missing diagnostics for uses of declarations when performing typename
access,
such as when performing member access on a '[[deprecated]]' type alias.
(#GH58547)
+- For ARM targets, when using cc1as, the features included
https://github.com/davemgreen approved this pull request.
The other thing this patch does is bring the preprocessor features for
-march=armv8.1-m in line with the assembly features. It was previously enabling
__ARM_VFPV2__ but not allowing vfpv2 instructions.
I'm still not sure about the Win/D
@@ -679,21 +679,17 @@ llvm::ARM::FPUKind arm::getARMTargetFeatures(const Driver
&D,
CPUArgFPUKind != llvm::ARM::FK_INVALID ? CPUArgFPUKind :
ArchArgFPUKind;
(void)llvm::ARM::getFPUFeatures(FPUKind, Features);
} else {
-bool Generic = true;
-if (!ForAS) {
@@ -485,6 +485,24 @@ ABIArgInfo AArch64ABIInfo::classifyArgumentType(QualType
Ty, bool IsVariadicFn,
}
Size = llvm::alignTo(Size, Alignment);
+// If the Aggregate is made up of pointers, use an array of pointers for
the
+// coerced type. This prevents having
https://github.com/davemgreen updated
https://github.com/llvm/llvm-project/pull/135064
>From 33a204bcc884178971c4327528b1e3b75336914e Mon Sep 17 00:00:00 2001
From: David Green
Date: Wed, 9 Apr 2025 11:18:25 +0100
Subject: [PATCH 1/4] [AArch64] Add a test case for the coerced arguments. NFC
--
https://github.com/davemgreen created
https://github.com/llvm/llvm-project/pull/135064
The aim here is to avoid a ptrtoint->inttoptr round-trip through the function
argument whilst keeping the calling convention the same. Given a struct which
is <= 128bits in size, which can only contain either
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https://github.com/davemgreen approved this pull request.
Thanks, LGTM
https://github.com/llvm/llvm-project/pull/134802
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https://github.com/davemgreen commented:
Thanks - this looks good.
https://github.com/llvm/llvm-project/pull/130623
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davemgreen wrote:
I didn't believe that the backend supports it properly yet (or was tested
at-all). I'm not sure of the details on why that was deemed OK not to support
it. @sdesmalen-arm and @paulwalker-arm might know more.
https://github.com/llvm/llvm-project/pull/132772
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davemgreen wrote:
I was going to suggest in #130623 that we undid this part of the change and
made it an NFC except for +[no]simd. But after looking at it this morning.. I
wasn't sure. It at least it deserved to be its own change :)
I believe that if it used `if (!ForAS || !Generic)` then it
@@ -1,93 +1,93 @@
-// Test of the AArch32 values of -mtp=, checking that each one maps to
-// the right target features.
-
-// RUN: %clang --target=armv7-linux -mtp=cp15 -### -S %s 2>&1 | \
-// RUN: FileCheck -check-prefix=ARMv7_THREAD_POINTER-HARD %s
-// ARMv7_THREAD_POINTER-HARD
davemgreen wrote:
The way we tried to mitigate this in the past was to use
-target=aarch64-arm-none-eabi for our downstream compiler, and have downstream
differences gated on the arm vendor. It can help keep the upstream tests the
same if they use -target=aarch64-unknown-linux-gnu, and have do
https://github.com/davemgreen approved this pull request.
Thanks for the cleanup, LGTM.
(You could probably have just submitted this without review, but that is
getting more rare nowadays).
https://github.com/llvm/llvm-project/pull/134359
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@@ -1,93 +1,93 @@
-// Test of the AArch32 values of -mtp=, checking that each one maps to
-// the right target features.
-
-// RUN: %clang --target=armv7-linux -mtp=cp15 -### -S %s 2>&1 | \
-// RUN: FileCheck -check-prefix=ARMv7_THREAD_POINTER-HARD %s
-// ARMv7_THREAD_POINTER-HARD
@@ -679,20 +679,18 @@ llvm::ARM::FPUKind arm::getARMTargetFeatures(const Driver
&D,
CPUArgFPUKind != llvm::ARM::FK_INVALID ? CPUArgFPUKind :
ArchArgFPUKind;
(void)llvm::ARM::getFPUFeatures(FPUKind, Features);
} else {
-bool Generic = true;
-if (!ForAS) {
https://github.com/davemgreen edited
https://github.com/llvm/llvm-project/pull/130623
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@@ -38,6 +38,9 @@ Potentially Breaking Changes
- Fix missing diagnostics for uses of declarations when performing typename
access,
such as when performing member access on a '[[deprecated]]' type alias.
(#GH58547)
+- For ARM targets, when using cc1as, the features included
@@ -0,0 +1,31 @@
+// Ensures that when targeting an ARM target with an Asm file, clang
+// collects the features from the FPU. This is critical in the
+// activation of NEON for supported targets. The Cortex-R52 will be
+// used and tested for VFP and NEON Support
+
+// RUN: %clan
@@ -1067,7 +1067,8 @@ def ProcessorFeatures {
FeatureDotProd, FeatureFPARMv8,
FeatureMatMulInt8,
FeatureSSBS, FeatureCCIDX,
FeatureJS, FeatureLSE, FeatureRAS,
Featur
https://github.com/davemgreen approved this pull request.
Thanks, LGTM
https://github.com/llvm/llvm-project/pull/132368
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@@ -288,6 +288,7 @@ StringRef sys::detail::getHostCPUNameForARM(StringRef
ProcCpuinfoContent) {
if (Implementer == "0x4e") { // NVIDIA Corporation
return StringSwitch(Part)
.Case("0x004", "carmel")
+.Case("0x10", "olympus")
davemgreen wro
@@ -872,6 +883,16 @@ def ProcessorFeatures {
list Carmel = [HasV8_2aOps, FeatureNEON, FeatureSHA2,
FeatureAES,
FeatureFullFP16, FeatureCRC, FeatureLSE,
FeatureRAS, FeatureRDM,
FeatureFPARMv8];
+ li
@@ -0,0 +1,8040 @@
+//===-- AArch64.cpp - Emit LLVM Code for builtins
-===//
davemgreen wrote:
This looks like it should be Arm.cpp, as it is the common code between the Arm
and AArch64 backends.
https://github.com/llvm/llvm-project/pul
@@ -334,8 +334,8 @@ ARM_CPU_NAME("cortex-r7", ARMV7R, FK_VFPV3_D16_FP16, false,
(ARM::AEK_MP | ARM::AEK_HWDIVARM))
ARM_CPU_NAME("cortex-r8", ARMV7R, FK_VFPV3_D16_FP16, false,
(ARM::AEK_MP | ARM::AEK_HWDIVARM))
-ARM_CPU_NAME("cortex-r52", ARMV8R, FK_NEO
davemgreen wrote:
Sorry for the delay, my computer got very slow at building things. - What goes
wrong if ARM::AEK_SIMD is removed from the CPU and architecture definitions? If
it is needed then there are some other cpu's where it might need to be added
too. But I'm not sure what needs it. (Ta
davemgreen wrote:
NEON is never mandatory AFAIU in the architecture (FP too). We might assume it
to be present though, as I believe it comes from the default -mfpu. (For
example FK_CRYPTO_NEON_FP_ARMV8 from armv8-a).
Using something like this: https://godbolt.org/z/EKEMsaMdW. If I take this
p
@@ -334,8 +334,8 @@ ARM_CPU_NAME("cortex-r7", ARMV7R, FK_VFPV3_D16_FP16, false,
(ARM::AEK_MP | ARM::AEK_HWDIVARM))
ARM_CPU_NAME("cortex-r8", ARMV7R, FK_VFPV3_D16_FP16, false,
(ARM::AEK_MP | ARM::AEK_HWDIVARM))
-ARM_CPU_NAME("cortex-r52", ARMV8R, FK_NEO
@@ -85,6 +85,9 @@ Changes to the AMDGPU Backend
Changes to the ARM Backend
--
+* The `+nosimd` attribute is now fully supported. Previously, this had no
effect when being used with
+AArch32 targets, however this will now disable NEON instructions being
=?utf-8?q?Csanád_Hajdú?= ,
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https://github.com/davemgreen closed
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https://github.com/davemgreen approved this pull request.
LGTM
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davemgreen wrote:
It probably needs to not happen with -fno-unaligned-access (or +strict-align),
unless the load / store is known to be 16byte aligned. See
https://github.com/llvm/llvm-project/issues/119732 from recently. (Also I guess
they shouldn't work in BE, but I believe that is not suppo
https://github.com/davemgreen commented:
Thanks - this looks sensible to me if these are always present on Grace (I'm
not sure how to check that, I will leave for someone else to review). It
currently uses a bit of a mixture of specifying features individually
(FeatureAES and FeatureSVEAES) an
@@ -944,6 +944,15 @@ def ProcessorFeatures {
list Falkor = [HasV8_0aOps, FeatureCRC, FeatureSHA2,
FeatureAES,
FeatureFPARMv8, FeatureNEON,
FeaturePerfMon,
FeatureRDM];
+ list Grace= [HasV9_0aO
@@ -0,0 +1,451 @@
+; RUN: llc -mtriple=aarch64 -verify-machineinstrs --mattr=+cpa -O0
-global-isel=0 -fast-isel=0 %s -o - 2>&1 | FileCheck %s
--check-prefixes=CHECK-CPA-O0
+; RUN: llc -mtriple=aarch64 -verify-machineinstrs --mattr=+cpa -O3
-global-isel=0 -fast-isel=0 %s -o - 2>
@@ -5025,6 +5025,11 @@ def msve_vector_bits_EQ : Joined<["-"],
"msve-vector-bits=">, Group,
HelpText<"Specify the size in bits of an SVE vector register. Defaults to
the"
" vector length agnostic value of \"scalable\". (AArch64 only)">;
+
+def mcpa_codegen : Flag<
@@ -401,7 +401,7 @@ def tblockaddress: SDNode<"ISD::TargetBlockAddress",
SDTPtrLeaf, [],
def add: SDNode<"ISD::ADD" , SDTIntBinOp ,
[SDNPCommutative, SDNPAssociative]>;
-def ptradd : SDNode<"ISD::ADD" , SDTPtrAddOp, []>;
+def
https://github.com/davemgreen approved this pull request.
https://github.com/llvm/llvm-project/pull/126278
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https://github.com/davemgreen milestoned
https://github.com/llvm/llvm-project/pull/124466
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davemgreen wrote:
/cherry-pick 9f1c825fb62319b94ac9604f733afd59e9eb461b
https://github.com/llvm/llvm-project/pull/124466
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https://github.com/davemgreen closed
https://github.com/llvm/llvm-project/pull/124466
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@@ -708,7 +708,7 @@ AArch64TargetInfo::getVScaleRange(const LangOptions
&LangOpts) const {
return std::pair(
LangOpts.VScaleMin ? LangOpts.VScaleMin : 1, LangOpts.VScaleMax);
- if (hasFeature("sve"))
+ if (hasFeature("sve") || hasFeature("sme"))
https://github.com/davemgreen updated
https://github.com/llvm/llvm-project/pull/124466
>From c43c26262c25ffb99ee411c05d19739d83cf1c05 Mon Sep 17 00:00:00 2001
From: David Green
Date: Sun, 26 Jan 2025 13:47:58 +
Subject: [PATCH 1/2] [AArch64] Enable vscale_range with +sme
If we have +sme bu
davemgreen wrote:
Is it worth adding a release note, if this is altering the ABI between versions?
https://github.com/llvm/llvm-project/pull/124760
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@@ -708,7 +708,7 @@ AArch64TargetInfo::getVScaleRange(const LangOptions
&LangOpts) const {
return std::pair(
LangOpts.VScaleMin ? LangOpts.VScaleMin : 1, LangOpts.VScaleMax);
- if (hasFeature("sve"))
+ if (hasFeature("sve") || hasFeature("sme"))
@@ -708,7 +708,7 @@ AArch64TargetInfo::getVScaleRange(const LangOptions
&LangOpts) const {
return std::pair(
LangOpts.VScaleMin ? LangOpts.VScaleMin : 1, LangOpts.VScaleMax);
- if (hasFeature("sve"))
+ if (hasFeature("sve") || hasFeature("sme"))
https://github.com/davemgreen edited
https://github.com/llvm/llvm-project/pull/124466
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https://github.com/davemgreen created
https://github.com/llvm/llvm-project/pull/124466
If we have +sme but not +sve, we would not set vscale_range on functions. It
should be valid to apply it with the same range with just +sme, which can help
improve the performance of generated code.
>From 7
davemgreen wrote:
Hi - that sounds like GISel might be miss-compiling it? It doesn't support
bf16, so shouldn't be trying to use those instructions for fp16. I can try and
take a look.
https://github.com/llvm/llvm-project/pull/120363
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davemgreen wrote:
Ah - thanks. It is hopefully fixed in 6dc356d6985fc49d1b69c20cc27f6b066742144a?
https://github.com/llvm/llvm-project/pull/120363
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Author: David Green
Date: 2025-01-21T10:36:58Z
New Revision: 6dc356d6985fc49d1b69c20cc27f6b066742144a
URL:
https://github.com/llvm/llvm-project/commit/6dc356d6985fc49d1b69c20cc27f6b066742144a
DIFF:
https://github.com/llvm/llvm-project/commit/6dc356d6985fc49d1b69c20cc27f6b066742144a.diff
LOG: [
https://github.com/davemgreen closed
https://github.com/llvm/llvm-project/pull/120363
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@@ -9053,22 +9053,19 @@ class SIMDThreeSameVectorBF16MatrixMul
let mayRaiseFPException = 1, Uses = [FPCR] in
class SIMD_BFCVTN
- : BaseSIMDMixedTwoVector<0, 0, 0b10, 0b10110, V128, V128,
+ : BaseSIMDMixedTwoVector<0, 0, 0b10, 0b10110, V128, V64,
davemgreen w
@@ -4064,31 +4072,59 @@ static Value *upgradeX86IntrinsicCall(StringRef Name,
CallBase *CI, Function *F,
static Value *upgradeAArch64IntrinsicCall(StringRef Name, CallBase *CI,
Function *F, IRBuilder<> &Builder) {
- Intrinsic::ID New
davemgreen wrote:
I agree the current behaviour isn't very consistent. It would be good to come
up with a single rule and stick to it, whatever it is. FeatureAMVS /
FEAT_AMUv1p1 came up recently too, which is enabled for some cpus that do not
have it (like Neoverse V3).
It looks like GCC is t
davemgreen wrote:
Is this a system-reg only extension?
It was enabled in #115296, which has an explanation why it was enabled.
I'm not sure how well we implement the sys-reg only extensions always being
enabled idea, or if the best way to handle that is making them required
features. But this
@@ -323,9 +321,10 @@ bfloat16x8_t test_vcvtq_low_bf16_f32(float32x4_t a) {
// CHECK-A64-NEXT: entry:
// CHECK-A64-NEXT:[[TMP0:%.*]] = bitcast <8 x bfloat> [[INACTIVE:%.*]] to
<16 x i8>
// CHECK-A64-NEXT:[[TMP1:%.*]] = bitcast <4 x float> [[A:%.*]] to <16 x i8>
-// CHE
https://github.com/davemgreen closed
https://github.com/llvm/llvm-project/pull/122965
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https://github.com/davemgreen approved this pull request.
Thanks LGTM. Let us know if we should squash and merge (I never know who has
access).
https://github.com/llvm/llvm-project/pull/122965
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https://github.com/davemgreen edited
https://github.com/llvm/llvm-project/pull/117007
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@@ -2033,6 +2041,25 @@ bool
AArch64TargetLowering::shouldExpandGetActiveLaneMask(EVT ResVT,
return false;
}
+bool AArch64TargetLowering::shouldExpandGetAliasLaneMask(
davemgreen wrote:
Can this be removed now?
https://github.com/llvm/llvm-project/pull/117
@@ -567,6 +567,9 @@ std::string SDNode::getOperationName(const SelectionDAG *G)
const {
case ISD::EXPERIMENTAL_VECTOR_HISTOGRAM:
return "histogram";
+ case ISD::EXPERIMENTAL_ALIAS_LANE_MASK:
+return "alias_mask";
davemgreen wrote:
alias_lane_mask
https://github.com/davemgreen commented:
If you want to upgrade the whilewr intrinsics (which I think sounds OK to me),
then it will need auto-update code something like in
https://github.com/llvm/llvm-project/pull/120363/files#diff-0c0305d510a076cef711c006c1d9fd78c95cade1f597d21ee46fd753e69823
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