changpeng wrote:
> but we do have `v_cos_bf16` in `llvm/test/MC/AMDGPU/gfx1250_asm_vop1.s`?
I meant your original subject is v_sin_bf16, but the patch is about v_cos_bf16
https://github.com/llvm/llvm-project/pull/149355
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cf
https://github.com/changpeng approved this pull request.
LGTM. Changed subject to "v_cos_bf16_e64" based on the contents.
https://github.com/llvm/llvm-project/pull/149355
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https://github.com/changpeng updated
https://github.com/llvm/llvm-project/pull/148141
>From c9cf9873e35205f9715acd545680713c0dd912aa Mon Sep 17 00:00:00 2001
From: Changpeng Fang
Date: Fri, 11 Jul 2025 01:04:04 -0700
Subject: [PATCH 1/3] =?UTF-8?q?AMDGPU:=20Remove=20"gws"=20from=20the=20?=
=?U
https://github.com/changpeng updated
https://github.com/llvm/llvm-project/pull/148991
>From 074800e1906bcce1cc0110c759a6d141ce4ea322 Mon Sep 17 00:00:00 2001
From: Changpeng Fang
Date: Tue, 15 Jul 2025 16:37:20 -0700
Subject: [PATCH 1/2] AMDGPU: Implement builtins for gfx1250 wmma instructions
https://github.com/changpeng updated
https://github.com/llvm/llvm-project/pull/148141
>From c9cf9873e35205f9715acd545680713c0dd912aa Mon Sep 17 00:00:00 2001
From: Changpeng Fang
Date: Fri, 11 Jul 2025 01:04:04 -0700
Subject: [PATCH 1/3] =?UTF-8?q?AMDGPU:=20Remove=20"gws"=20from=20the=20?=
=?U
@@ -816,12 +816,12 @@ kernel void test_target_features_kernel(global int *i) {
// NOCPU: attributes #[[ATTR10]] = { convergent nounwind }
//.
// GFX900: attributes #[[ATTR0:[0-9]+]] = { "objc_arc_inert" }
-// GFX900: attributes #[[ATTR1]] = { convergent norecurse nounwind
"den
https://github.com/changpeng closed
https://github.com/llvm/llvm-project/pull/148292
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>From c220c16d134dd1a1690e973abd4ca5b2401e6510 Mon Sep 17 00:00:00 2001
From: Changpeng Fang
Date: Fri, 11 Jul 2025 13:20:00 -0700
Subject: [PATCH] AMDGPU: Implement s_wait_asynccnt and s_wait_tensorcnt
@@ -266,7 +266,7 @@ AMDGPUTargetInfo::AMDGPUTargetInfo(const llvm::Triple
&Triple,
MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
CUMode = !(GPUFeatures & llvm::AMDGPU::FEATURE_WGP);
- for (auto F : {"image-insts", "gws", "vmem-to-lds-load-insts"})
+ for (auto F : {
@@ -816,12 +816,12 @@ kernel void test_target_features_kernel(global int *i) {
// NOCPU: attributes #[[ATTR10]] = { convergent nounwind }
//.
// GFX900: attributes #[[ATTR0:[0-9]+]] = { "objc_arc_inert" }
-// GFX900: attributes #[[ATTR1]] = { convergent norecurse nounwind
"den
https://github.com/changpeng updated
https://github.com/llvm/llvm-project/pull/148141
>From c9cf9873e35205f9715acd545680713c0dd912aa Mon Sep 17 00:00:00 2001
From: Changpeng Fang
Date: Fri, 11 Jul 2025 01:04:04 -0700
Subject: [PATCH 1/3] =?UTF-8?q?AMDGPU:=20Remove=20"gws"=20from=20the=20?=
=?U
https://github.com/changpeng updated
https://github.com/llvm/llvm-project/pull/148141
>From c9cf9873e35205f9715acd545680713c0dd912aa Mon Sep 17 00:00:00 2001
From: Changpeng Fang
Date: Fri, 11 Jul 2025 01:04:04 -0700
Subject: [PATCH 1/2] =?UTF-8?q?AMDGPU:=20Remove=20"gws"=20from=20the=20?=
=?U
changpeng wrote:
Need to fix two additional LIT tests...
https://github.com/llvm/llvm-project/pull/148141
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https://github.com/llvm/llvm-project/pull/148141
Since this feature is no longer universally available, we may need it in the
IR.
Fixes: SWDEV-541399
>From c9cf9873e35205f9715acd545680713c0dd912aa Mon Sep 17 00:00:00 2001
From: Changpeng Fang
Date: Fri,
https://github.com/changpeng closed
https://github.com/llvm/llvm-project/pull/146636
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@@ -5354,6 +5368,22 @@ AMDGPURegisterBankInfo::getInstrMapping(const
MachineInstr &MI) const {
}
case Intrinsic::amdgcn_pops_exiting_wave_id:
return getDefaultMappingSOP(MI);
+case Intrinsic::amdgcn_tensor_load_to_lds_d2:
+case Intrinsic::amdgcn_tensor_st
@@ -3580,6 +3580,37 @@ def int_amdgcn_fdiv_fast : DefaultAttrsIntrinsic<
[IntrNoMem, IntrSpeculatable]
>;
+class AMDGPUTensorLoadStore:
+ Intrinsic<
+[],
+[llvm_v4i32_ty, // D# group 0
+ llvm_v8i32_ty, // D# group 1
+ llvm_v4i32_ty, // D# group 2
+ llvm_
@@ -621,6 +621,32 @@ Value *CodeGenFunction::EmitAMDGPUBuiltinExpr(unsigned
BuiltinID,
llvm::Function *F = CGM.getIntrinsic(IID, {LoadTy});
return Builder.CreateCall(F, {Addr});
}
+ case AMDGPU::BI__builtin_amdgcn_tensor_load_to_lds:
+ case AMDGPU::BI__builtin_amdg
https://github.com/changpeng updated
https://github.com/llvm/llvm-project/pull/146636
>From b6aa91862046fdd021e638f0f22e9cbbbfba418f Mon Sep 17 00:00:00 2001
From: Changpeng Fang
Date: Tue, 1 Jul 2025 22:41:41 -0700
Subject: [PATCH 1/2] AMDGPU: Implement tensor load and store instructions for
https://github.com/changpeng edited
https://github.com/llvm/llvm-project/pull/146636
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@@ -5354,6 +5368,22 @@ AMDGPURegisterBankInfo::getInstrMapping(const
MachineInstr &MI) const {
}
case Intrinsic::amdgcn_pops_exiting_wave_id:
return getDefaultMappingSOP(MI);
+case Intrinsic::amdgcn_tensor_load_to_lds_d2:
+case Intrinsic::amdgcn_tensor_st
@@ -1092,19 +1092,23 @@ let SubtargetPredicate = isGFX12Plus in {
}
let WaveSizePredicate = isWave32 in {
-let Mnemonic = "global_load_tr_b128" in
-defm GLOBAL_LOAD_TR_B128_w32 : FLAT_Global_Load_Pseudo
<"global_load_tr_b128_w32", VReg_128>;
-let Mnemonic = "
@@ -621,6 +621,32 @@ Value *CodeGenFunction::EmitAMDGPUBuiltinExpr(unsigned
BuiltinID,
llvm::Function *F = CGM.getIntrinsic(IID, {LoadTy});
return Builder.CreateCall(F, {Addr});
}
+ case AMDGPU::BI__builtin_amdgcn_tensor_load_to_lds:
+ case AMDGPU::BI__builtin_amdg
https://github.com/changpeng edited
https://github.com/llvm/llvm-project/pull/146636
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@@ -621,6 +621,32 @@ Value *CodeGenFunction::EmitAMDGPUBuiltinExpr(unsigned
BuiltinID,
llvm::Function *F = CGM.getIntrinsic(IID, {LoadTy});
return Builder.CreateCall(F, {Addr});
}
+ case AMDGPU::BI__builtin_amdgcn_tensor_load_to_lds:
+ case AMDGPU::BI__builtin_amdg
https://github.com/changpeng created
https://github.com/llvm/llvm-project/pull/146636
None
>From b6aa91862046fdd021e638f0f22e9cbbbfba418f Mon Sep 17 00:00:00 2001
From: Changpeng Fang
Date: Tue, 1 Jul 2025 22:41:41 -0700
Subject: [PATCH] AMDGPU: Implement tensor load and store instructions for
https://github.com/changpeng closed
https://github.com/llvm/llvm-project/pull/146409
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https://github.com/changpeng created
https://github.com/llvm/llvm-project/pull/146409
These two instructions are supported by gfx1250. We define the instructions
and implement the corresponding intrinsic and builtin.
>From ea949512b4c2234dffad366cf782f6e5c62f37d7 Mon Sep 17 00:00:00 2001
Fro
https://github.com/changpeng closed
https://github.com/llvm/llvm-project/pull/146293
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https://github.com/llvm/llvm-project/pull/146293
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>From d6f55a31a5b9cc0716149424e219d219c2970d0c Mon Sep 17 00:00:00 2001
From: Changpeng Fang
Date: Sun, 29 Jun 2025 16:03:46 -0700
Subject: [PATCH] AMDGPU: support s_monitor_sleep on gfx1250
Co-Authored
https://github.com/changpeng closed
https://github.com/llvm/llvm-project/pull/146289
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>From fc2039dcf338f04977b2a0b43e8714cb5eb0f440 Mon Sep 17 00:00:00 2001
From: Changpeng Fang
Date: Fri, 27 Jun 2025 14:59:33 -0700
Subject: [PATCH] AMDGPU: Implement intrinsic/builtins for gfx1250 load
https://github.com/changpeng closed
https://github.com/llvm/llvm-project/pull/146024
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changpeng wrote:
@Artem-B : any further suggestions? Thanks.
https://github.com/llvm/llvm-project/pull/138162
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changpeng wrote:
> In practice this should be a single use of an internal function and should
> not require this hint. Is this papering over a different issue?
If in practice the single-used internal function should always be inlined, then
we must have an issue for ubuntu 24.04:
The stub is in
https://github.com/changpeng closed
https://github.com/llvm/llvm-project/pull/99551
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>From 31601c539553d7af0efd94722eabf4627f8a387c Mon Sep 17 00:00:00 2001
From: Changpeng Fang
Date: Thu, 18 Jul 2024 11:03:24 -0700
Subject: [PATCH 1/2] AMDGPU: Add back half and bfloat support for
global
@@ -1590,10 +1590,14 @@ let OtherPredicates = [isGFX12Plus] in {
let WaveSizePredicate = isWave32 in {
defm : GlobalFLATLoadPats ;
defm : GlobalFLATLoadPats ;
+defm : GlobalFLATLoadPats ;
+defm : GlobalFLATLoadPats ;
}
let WaveSizePredicate = isWave64 in
https://github.com/changpeng closed
https://github.com/llvm/llvm-project/pull/99540
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https://github.com/changpeng created
https://github.com/llvm/llvm-project/pull/99540
half and bfloat are common types for 16-bit elements. The support of them was
original there and dropped due to some reasons. This work adds the support of
the float types back.
>From 31601c539553d7af0efd947
https://github.com/changpeng closed
https://github.com/llvm/llvm-project/pull/92612
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@@ -0,0 +1,25 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
UTC_ARGS: --version 4
+//RUN: %clang_cc1 %s -emit-llvm -O1 -o - | FileCheck %s
changpeng wrote:
add "triple spir", same as other tests in the same directory
https://
https://github.com/changpeng updated
https://github.com/llvm/llvm-project/pull/92612
>From 2468a85a47499d90a99610846c632332eb7307b8 Mon Sep 17 00:00:00 2001
From: Changpeng Fang
Date: Fri, 17 May 2024 15:13:07 -0700
Subject: [PATCH 1/3] [OpenCL] Fix an infinite loop in builidng
AddrSpaceQualTy
https://github.com/changpeng edited
https://github.com/llvm/llvm-project/pull/92612
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@@ -3054,6 +3054,13 @@ QualType ASTContext::removeAddrSpaceQualType(QualType T)
const {
if (!T.hasAddressSpace())
return T;
+ // For arrays, strip the qualifier off the element type, then reconstruct the
+ // array type
+ if (T.getTypePtr()->isArrayType()) {
+Qua
@@ -537,8 +537,9 @@ void AggExprEmitter::EmitArrayInit(Address DestPtr,
llvm::ArrayType *AType,
elementType.isTriviallyCopyableType(CGF.getContext())) {
CodeGen::CodeGenModule &CGM = CGF.CGM;
ConstantEmitter Emitter(CGF);
+Qualifiers Quals;
QualType GVAr
https://github.com/changpeng updated
https://github.com/llvm/llvm-project/pull/92612
>From 2468a85a47499d90a99610846c632332eb7307b8 Mon Sep 17 00:00:00 2001
From: Changpeng Fang
Date: Fri, 17 May 2024 15:13:07 -0700
Subject: [PATCH 1/2] [OpenCL] Fix an infinite loop in builidng
AddrSpaceQualTy
@@ -537,8 +537,9 @@ void AggExprEmitter::EmitArrayInit(Address DestPtr,
llvm::ArrayType *AType,
elementType.isTriviallyCopyableType(CGF.getContext())) {
CodeGen::CodeGenModule &CGM = CGF.CGM;
ConstantEmitter Emitter(CGF);
+Qualifiers Quals;
QualType GVAr
@@ -535,20 +535,23 @@ void AggExprEmitter::EmitArrayInit(Address DestPtr,
llvm::ArrayType *AType,
elementType.isTriviallyCopyableType(CGF.getContext())) {
CodeGen::CodeGenModule &CGM = CGF.CGM;
ConstantEmitter Emitter(CGF);
-LangAS AS = ArrayQTy.getAddressSpa
https://github.com/changpeng created
https://github.com/llvm/llvm-project/pull/92612
In building AddrSpaceQualType
(https://github.com/llvm/llvm-project/pull/90048), there is a bug in
removeAddrSpaceQualType() for arrays. Arrays are weird because qualifiers on
the element type also count as
@@ -535,20 +535,23 @@ void AggExprEmitter::EmitArrayInit(Address DestPtr,
llvm::ArrayType *AType,
elementType.isTriviallyCopyableType(CGF.getContext())) {
CodeGen::CodeGenModule &CGM = CGF.CGM;
ConstantEmitter Emitter(CGF);
-LangAS AS = ArrayQTy.getAddressSpa
changpeng wrote:
[test.cl.txt](https://github.com/llvm/llvm-project/files/15355457/test.cl.txt)
https://github.com/llvm/llvm-project/pull/90048
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@@ -535,20 +535,23 @@ void AggExprEmitter::EmitArrayInit(Address DestPtr,
llvm::ArrayType *AType,
elementType.isTriviallyCopyableType(CGF.getContext())) {
CodeGen::CodeGenModule &CGM = CGF.CGM;
ConstantEmitter Emitter(CGF);
-LangAS AS = ArrayQTy.getAddressSpa
@@ -535,20 +535,23 @@ void AggExprEmitter::EmitArrayInit(Address DestPtr,
llvm::ArrayType *AType,
elementType.isTriviallyCopyableType(CGF.getContext())) {
CodeGen::CodeGenModule &CGM = CGF.CGM;
ConstantEmitter Emitter(CGF);
-LangAS AS = ArrayQTy.getAddressSpa
@@ -535,20 +535,23 @@ void AggExprEmitter::EmitArrayInit(Address DestPtr,
llvm::ArrayType *AType,
elementType.isTriviallyCopyableType(CGF.getContext())) {
CodeGen::CodeGenModule &CGM = CGF.CGM;
ConstantEmitter Emitter(CGF);
-LangAS AS = ArrayQTy.getAddressSpa
https://github.com/changpeng closed
https://github.com/llvm/llvm-project/pull/86707
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https://github.com/changpeng updated
https://github.com/llvm/llvm-project/pull/86707
>From 485dff66813104ad73d8eada7cd7d43edf9d093d Mon Sep 17 00:00:00 2001
From: Changpeng Fang
Date: Tue, 26 Mar 2024 11:06:48 -0700
Subject: [PATCH 1/3] AMDGPU: Simplify EmitAMDGPUBuiltinExpr for load
transpose
https://github.com/changpeng updated
https://github.com/llvm/llvm-project/pull/86707
>From 485dff66813104ad73d8eada7cd7d43edf9d093d Mon Sep 17 00:00:00 2001
From: Changpeng Fang
Date: Tue, 26 Mar 2024 11:06:48 -0700
Subject: [PATCH 1/2] AMDGPU: Simplify EmitAMDGPUBuiltinExpr for load
transpose
https://github.com/changpeng created
https://github.com/llvm/llvm-project/pull/86707
We should not manually get the types of the loading data.
Instead, we can get the types from the intrinsics directly.
>From 485dff66813104ad73d8eada7cd7d43edf9d093d Mon Sep 17 00:00:00 2001
From: Changpeng Fa
https://github.com/changpeng edited
https://github.com/llvm/llvm-project/pull/86313
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@@ -18533,51 +18533,35 @@ Value
*CodeGenFunction::EmitAMDGPUBuiltinExpr(unsigned BuiltinID,
}
case AMDGPU::BI__builtin_amdgcn_global_load_tr_b64_i32:
case AMDGPU::BI__builtin_amdgcn_global_load_tr_b64_v2i32:
- case AMDGPU::BI__builtin_amdgcn_global_load_tr_b128_v4bf16:
changpeng wrote:
ping
https://github.com/llvm/llvm-project/pull/86313
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changpeng wrote:
> There is no issue in changing the names in principle. Curious, what is the
> rationale to use more demangled names?
more user friendly.
https://github.com/llvm/llvm-project/pull/86313
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changpeng wrote:
> > global_load_re_b64
>
> Type global_load_re_b64.
Changed! Thanks.
https://github.com/llvm/llvm-project/pull/86313
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https://github.com/changpeng edited
https://github.com/llvm/llvm-project/pull/86313
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https://github.com/changpeng created
https://github.com/llvm/llvm-project/pull/86313
Rename the intrinsics to close to the instruction mnemonic names:
Use global_load_re_b64 and global_load_tr_b128 instead of global_load_tr.
This patch also removes f16/bf16 versions of builtins/intrinsics.
changpeng wrote:
I am going to propose to rename intrinsics and remove f16/bf16 versions of
builtins/intrinsics
https://github.com/llvm/llvm-project/pull/86202
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https://github.com/changpeng closed
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changpeng wrote:
[AMD Official Use Only - General]
I am fine to remove f16/bf16 versions. Enumerating all possible types could be
very painful. For example we gave up enumerating for B64, and ended up using
v2i32 only. What do others think removing f16/bf16 versions? Thanks
Get Outlook for iO
changpeng wrote:
> I don't think intrinsics are meant for users. Builtins are the user-facing
> front. :-)
Then renaing the intrinsics should be relatively at a lower priority. We may do
it in a separate patch once we have reached an agreement.
https://github.com/llvm/llvm-project/pull/86202
changpeng wrote:
> > > Do you want to rename intrinsics as well? Because now intrinsic names do
> > > not match builtin names.
> >
> >
> > Do we have to match builtins with intrinsics? Renaming intrinsics here
> > means we will have to duplicate the intrinsics.
>
> Is that because of the man
changpeng wrote:
> Do you want to rename intrinsics as well? Because now intrinsic names do not
> match builtin names.
Do we have to match builtins with intrinsics? Renaming intrinsics here means we
will have to duplicate the intrinsics.
https://github.com/llvm/llvm-project/pull/86202
__
https://github.com/changpeng created
https://github.com/llvm/llvm-project/pull/86202
Make the name of a clang builtin as close to the mnemonic instruction name as
possible. The data type suffix may not be enough to tell what instruction the
builtin is going to produce.
This patch also add
https://github.com/changpeng closed
https://github.com/llvm/llvm-project/pull/84248
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https://github.com/changpeng created
https://github.com/llvm/llvm-project/pull/84248
FeatureDot11Insts (dot11-insts) for:
v_dot4_f32_fp8_fp8, v_dot4_f32_fp8_bf8,
v_dot4_f32_bf8_fp8, v_dot4_f32_bf8_bf8
>From 1bfc1e048d10e57c3d07038f52b072163f3b4ff9 Mon Sep 17 00:00:00 2001
From: Changpeng Fa
https://github.com/changpeng closed
https://github.com/llvm/llvm-project/pull/79394
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https://github.com/changpeng updated
https://github.com/llvm/llvm-project/pull/79394
>From 0f3af077baeff26d9796db73e7af19b097272fa2 Mon Sep 17 00:00:00 2001
From: Changpeng Fang
Date: Wed, 24 Jan 2024 16:28:23 -0800
Subject: [PATCH] [AMDGPU] Rename AMDGPULoadTr intrinsic class. NFC.
This cla
https://github.com/changpeng closed
https://github.com/llvm/llvm-project/pull/79218
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https://github.com/changpeng approved this pull request.
https://github.com/llvm/llvm-project/pull/2
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@@ -2496,6 +2496,26 @@ def int_amdgcn_flat_atomic_fmax_num :
AMDGPUAtomicRtn;
def int_amdgcn_global_atomic_fmin_num : AMDGPUAtomicRtn;
def int_amdgcn_global_atomic_fmax_num : AMDGPUAtomicRtn;
+class AMDGPUGlobalLoadTr :
+ Intrinsic<
+[data_ty],
+[global_ptr_ty],
+
@@ -18178,6 +18178,51 @@ Value *CodeGenFunction::EmitAMDGPUBuiltinExpr(unsigned
BuiltinID,
llvm::Function *F = CGM.getIntrinsic(IID, {ArgTy});
return Builder.CreateCall(F, {Addr, Val, ZeroI32, ZeroI32, ZeroI1});
}
+ case AMDGPU::BI__builtin_amdgcn_global_load_tr_b64
https://github.com/changpeng closed
https://github.com/llvm/llvm-project/pull/71989
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https://github.com/changpeng reopened
https://github.com/llvm/llvm-project/pull/71989
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https://github.com/changpeng closed
https://github.com/llvm/llvm-project/pull/71989
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changpeng wrote:
> Typo in subject "**Guard** return ..."?
You are right. Thanks.
https://github.com/llvm/llvm-project/pull/71989
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https://github.com/changpeng edited
https://github.com/llvm/llvm-project/pull/71989
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changpeng wrote:
> Any tests?
Encountered this issue during a downstream branch testing. No test for trunk
yet but think the issue should be here.
https://github.com/llvm/llvm-project/pull/71989
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https://github.com/changpeng closed
https://github.com/llvm/llvm-project/pull/70484
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Author: Changpeng Fang
Date: 2023-08-11T16:37:42-07:00
New Revision: d77c62053c944652846c00a35c921e14b43b1877
URL:
https://github.com/llvm/llvm-project/commit/d77c62053c944652846c00a35c921e14b43b1877
DIFF:
https://github.com/llvm/llvm-project/commit/d77c62053c944652846c00a35c921e14b43b1877.diff
Author: Changpeng Fang
Date: 2023-08-09T18:23:18-07:00
New Revision: 4608686849bcb6e20de827750862d5345cbd
URL:
https://github.com/llvm/llvm-project/commit/4608686849bcb6e20de827750862d5345cbd
DIFF:
https://github.com/llvm/llvm-project/commit/4608686849bcb6e20de827750862d5345cbd.diff
Author: Changpeng Fang
Date: 2022-03-17T14:12:36-07:00
New Revision: dd5895cc39864393f8ca357bc4e23e8d7b5b9723
URL:
https://github.com/llvm/llvm-project/commit/dd5895cc39864393f8ca357bc4e23e8d7b5b9723
DIFF:
https://github.com/llvm/llvm-project/commit/dd5895cc39864393f8ca357bc4e23e8d7b5b9723.diff
Author: chfang
Date: Thu Aug 18 17:04:54 2016
New Revision: 279165
URL: http://llvm.org/viewvc/llvm-project?rev=279165&view=rev
Log:
AMDGPU: Add clang builtin for ds_swizzle.
Summary:
int __builtin_amdgcn_ds_swizzle (int a, int imm);
while imm is a constant.
Differential Revision:
http://rev
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