@@ -43,63 +43,6 @@
// CHECK-CRBITS: "-target-feature" "+crbits"
-// RUN: %clang -target powerpc64le-unknown-linux-gnu -mcpu=pwr10 -emit-llvm \
-// RUN: -S %s -o - | FileCheck %s --check-prefix=HAS-CRBITS
-// RUN: %clang -target powerpc64le-unknown-linux-gnu -mcpu=pwr10 -mcr
@@ -1,8 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
UTC_ARGS: --version 3
; RUN: llc -verify-machineinstrs -mcpu=pwr7 < %s | FileCheck %s
-; RUN: llc -verify-machineinstrs -O1 -mcpu=pwr7 < %s | FileCheck %s
+; RUN: llc -verify-machinein
https://github.com/amy-kwan approved this pull request.
LGTM.
https://github.com/llvm/llvm-project/pull/130324
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https://github.com/amy-kwan approved this pull request.
Thanks for clarifying my earlier comment. LGTM.
https://github.com/llvm/llvm-project/pull/118004
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@@ -473,7 +473,7 @@ class LLVM_LIBRARY_VISIBILITY PS3PPUTargetInfo : public
OSTargetInfo {
this->IntMaxType = TargetInfo::SignedLongLong;
this->Int64Type = TargetInfo::SignedLongLong;
this->SizeType = TargetInfo::UnsignedInt;
-this->resetDataLayout("E-m:e-p:32:
https://github.com/amy-kwan commented:
For the most part, I think it looks good but I just have one comment about a
change that (I think) doesn't need to happen.
https://github.com/llvm/llvm-project/pull/118004
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https://github.com/amy-kwan approved this pull request.
LGTM for using `CGT.ConvertType()` like you did previously. I agree that if we
were to do a larger/refactoring patch, that can be separate since this PR fixes
the current codegen.
https://github.com/llvm/llvm-project/pull/104816
_
https://github.com/amy-kwan commented:
I'm not an expert here, but I think the change you made makes sense since the
`Ty` is supposed to be the first field.
Also, might be a dumb question, I saw we have 32-bit Linux run lines, but is
that still worth testing?
https://github.com/llvm/llvm-proj
@@ -6143,23 +6143,23 @@ void PPCDAGToDAGISel::Select(SDNode *N) {
" ELF/AIX or 32-bit AIX in the following.");
// Transforms the ISD::TOC_ENTRY node for 32-bit AIX large code model mode,
-// or 64-bit medium (ELF-only), or large (ELF and AIX) code model code
@@ -479,14 +479,6 @@ static void addTocDataOptions(const llvm::opt::ArgList
&Args,
return false;
}();
- // Currently only supported for small code model.
- if (TOCDataGloballyinEffect &&
- (Args.getLastArgValue(options::OPT_mcmodel_EQ).equals("large") ||
-
@@ -6141,24 +6141,23 @@ void PPCDAGToDAGISel::Select(SDNode *N) {
assert((isPPC64 || (isAIXABI && !isPPC64)) && "We are dealing with 64-bit"
" ELF/AIX or 32-bit AIX in the following.");
-// Transforms the ISD::TOC_ENTRY node for 32-bit AIX large code model m
@@ -1292,8 +1291,9 @@ void PPCAsmPrinter::emitInstruction(const MachineInstr
*MI) {
unsigned Op = MI->getOpcode();
-// Change the opcode to load address for tocdata
-TmpInst.setOpcode(Op == PPC::ADDItocL8 ? PPC::ADDI8 : PPC::LA);
+// Change the opcode to load
https://github.com/amy-kwan approved this pull request.
I don't have any further comments. LGTM.
https://github.com/llvm/llvm-project/pull/82809
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@@ -3362,6 +3367,54 @@ SDValue PPCTargetLowering::LowerGlobalTLSAddress(SDValue
Op,
return LowerGlobalTLSAddressLinux(Op, DAG);
}
+/// updateForAIXShLibTLSModelOpt - Helper to initialize TLS model opt settings,
+/// and then apply the update.
+static void updateForAIXShLibT
https://github.com/amy-kwan approved this pull request.
LGTM after all the updates. Thanks!
https://github.com/llvm/llvm-project/pull/84132
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https://github.com/amy-kwan approved this pull request.
LGTM as well.
https://github.com/llvm/llvm-project/pull/88829
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@@ -6,6 +6,9 @@
// RUN: %clang -target powerpc64-unknown-aix -maix-small-local-exec-tls -S
-emit-llvm \
// RUN:%s -o - | FileCheck %s --check-prefix=CHECK-AIX_SMALL_LOCALEXEC_TLS
+// RUN: %clang -target powerpc64-unknown-aix -maix-small-local-dynamic-tls -S
-emit-llvm \
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@@ -3362,6 +3362,65 @@ SDValue PPCTargetLowering::LowerGlobalTLSAddress(SDValue
Op,
return LowerGlobalTLSAddressLinux(Op, DAG);
}
+/// updateForAIXShLibTLSModelOpt - Helper to initialize TLS model opt settings,
+/// and then apply the update.
+static void updateForAIXShLibT
https://github.com/amy-kwan approved this pull request.
Thank you for addressing my comment!
I think I do not have any further comments, so unless if anyone has any other
comments LGTM.
https://github.com/llvm/llvm-project/pull/84132
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@@ -3369,6 +3369,59 @@ SDValue
PPCTargetLowering::LowerGlobalTLSAddressAIX(SDValue Op,
bool Is64Bit = Subtarget.isPPC64();
bool HasAIXSmallLocalExecTLS = Subtarget.hasAIXSmallLocalExecTLS();
TLSModel::Model Model = getTargetMachine().getTLSModel(GV);
+ // Initialize TLS
amy-kwan wrote:
This also fails on PPC, as well:
https://lab.llvm.org/buildbot/#/builders/36/builds/43998/steps/12/logs/stdio
https://github.com/llvm/llvm-project/pull/86339
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Stefan =?utf-8?q?Gränitz?=
Message-ID:
In-Reply-To:
amy-kwan wrote:
Hi @weliveindetail!
I just wanted to give a heads up, that I believe
13078cbc3eeb0ae91c370ce0f604f7165b26e0c8 is causing a failure of the
clang-ppc64le-rhel bot:
https://lab.llvm.org/buildbot/#/builders/57/builds/33764/step
amy-kwan wrote:
Hi @Abhinkop!
I was wondering if there was any progress regarding the patch to resolve the
stage 2 failure, as our bot is still red
(https://lab.llvm.org/buildbot/#/builders/36/builds/43929/steps/12/logs/stdio).
Please let me know if you would also like me to test any patches, a
amy-kwan wrote:
> @amy-kwan I'm looking at it now. I will most probably raise a review some
> time later in the evening or tomorrow if I am not able to complete it today.
Sounds good, thank you so much, @Abhinkop!
https://github.com/llvm/llvm-project/pull/86131
amy-kwan wrote:
Thanks @Abhinkop for the patch! I have approved the compiler-rt patch since it
does appear to resolve the check-runtimes/check-all issue for the asan test
case.
If you also would like me to test a follow up patch for
`llvm-project/llvm/lib/IR/Core.cpp`, I would be happy to do
amy-kwan wrote:
I have also found one more that is not related to the sanitizers, but when
`llvm-project/llvm/lib/IR/Core.cpp`:
https://lab.llvm.org/buildbot/#/builders/36/builds/43840/steps/12/logs/stdio
Would it be possible to also resolve this one, as well?
https://github.com/llvm/llvm-pr
amy-kwan wrote:
Thanks @AaronBallman.
Not sure how I missed it, but I just noticed in my local build of
check-runtimes/check-all. This is also present on the following bot:
https://lab.llvm.org/buildbot/#/builders/57/builds/33656
https://github.com/llvm/llvm-project/pull/86131
@@ -3369,6 +3369,48 @@ SDValue
PPCTargetLowering::LowerGlobalTLSAddressAIX(SDValue Op,
bool Is64Bit = Subtarget.isPPC64();
bool HasAIXSmallLocalExecTLS = Subtarget.hasAIXSmallLocalExecTLS();
TLSModel::Model Model = getTargetMachine().getTLSModel(GV);
+ // Initialize heu
@@ -3369,6 +3369,48 @@ SDValue
PPCTargetLowering::LowerGlobalTLSAddressAIX(SDValue Op,
bool Is64Bit = Subtarget.isPPC64();
bool HasAIXSmallLocalExecTLS = Subtarget.hasAIXSmallLocalExecTLS();
TLSModel::Model Model = getTargetMachine().getTLSModel(GV);
+ // Initialize heu
@@ -848,6 +848,14 @@ void PPCAsmPrinter::emitInstruction(const MachineInstr
*MI) {
return MCSymbolRefExpr::VariantKind::VK_PPC_AIX_TLSLE;
if (Model == TLSModel::InitialExec)
return MCSymbolRefExpr::VariantKind::VK_PPC_AIX_TLSIE;
+ // On AIX, TLS mode
@@ -848,6 +848,14 @@ void PPCAsmPrinter::emitInstruction(const MachineInstr
*MI) {
return MCSymbolRefExpr::VariantKind::VK_PPC_AIX_TLSLE;
if (Model == TLSModel::InitialExec)
return MCSymbolRefExpr::VariantKind::VK_PPC_AIX_TLSIE;
+ // On AIX, TLS mode
@@ -3369,6 +3369,48 @@ SDValue
PPCTargetLowering::LowerGlobalTLSAddressAIX(SDValue Op,
bool Is64Bit = Subtarget.isPPC64();
bool HasAIXSmallLocalExecTLS = Subtarget.hasAIXSmallLocalExecTLS();
TLSModel::Model Model = getTargetMachine().getTLSModel(GV);
+ // Initialize heu
@@ -3369,6 +3369,48 @@ SDValue
PPCTargetLowering::LowerGlobalTLSAddressAIX(SDValue Op,
bool Is64Bit = Subtarget.isPPC64();
bool HasAIXSmallLocalExecTLS = Subtarget.hasAIXSmallLocalExecTLS();
TLSModel::Model Model = getTargetMachine().getTLSModel(GV);
+ // Initialize heu
@@ -4958,6 +4958,10 @@ def maix_small_local_exec_tls : Flag<["-"],
"maix-small-local-exec-tls">,
"where the offset from the TLS base is encoded as an "
"immediate operand (AIX 64-bit only). "
"This access sequence is not used for variables larg
https://github.com/amy-kwan approved this pull request.
I've also tested this locally, and it resolves the issue I saw earlier on the
PPC bots.
https://github.com/llvm/llvm-project/pull/86131
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htt
amy-kwan wrote:
> I'm confused as to how this code ever compiled in the first place... In each
> case, this is C++ code that's failing:
>
> ```
> /home/buildbots/llvm-external-buildbots/workers/ppc64le-clang-rhel-test/clang-ppc64le-rhel/llvm-project/compiler-rt/lib/sanitizer_common/sanitizer_po
amy-kwan wrote:
I believe this patch is causing some issues on two PPC bots. Would you be able
to help take a look?
https://lab.llvm.org/buildbot/#/builders/57/builds/33601/steps/5/logs/stdio
https://lab.llvm.org/buildbot/#/builders/36/builds/43759/steps/12/logs/stdio
https://github.com/llvm/ll
@@ -16570,32 +16570,53 @@ Value *CodeGenFunction::EmitPPCBuiltinExpr(unsigned
BuiltinID,
#include "llvm/TargetParser/PPCTargetParser.def"
auto GenAIXPPCBuiltinCpuExpr = [&](unsigned SupportMethod, unsigned FieldIdx,
- unsigned CompOp,
+
@@ -141,46 +149,98 @@ PPC_LNX_CPU("power10",47)
#define AIX_BUILTIN_PPC_TRUE 1
#define AIX_BUILTIN_PPC_FALSE 0
#define USE_SYS_CONF 2
-
- // Supported COMPARE_OP values.
- #define COMP_EQ 0
-
+ #define SYS_CALL 3
#endif
// The value of SUPPORT_METHOD can be AIX_BU
https://github.com/amy-kwan approved this pull request.
Thank you for the updates!
For me personally, I have no further comments. Unless if anyone else has any
comments, I think LGTM.
https://github.com/llvm/llvm-project/pull/66316
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@@ -145,9 +164,97 @@ namespace {
.addImm(0);
if (IsAIX) {
- // The variable offset and region handle are copied in r4 and r3. The
- // copies are followed by GETtlsADDR32AIX/GETtlsADDR64AIX
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@@ -16560,32 +16560,72 @@ Value *CodeGenFunction::EmitPPCBuiltinExpr(unsigned
BuiltinID,
#include "llvm/TargetParser/PPCTargetParser.def"
auto GenAIXPPCBuiltinCpuExpr = [&](unsigned SupportMethod, unsigned FieldIdx,
- unsigned CompOp,
+
@@ -364,7 +364,14 @@ class LLVM_LIBRARY_VISIBILITY PPCTargetInfo : public
TargetInfo {
// have Glibc since it is Glibc that provides the HWCAP[2] in the auxv.
static constexpr int MINIMUM_AIX_OS_MAJOR = 7;
static constexpr int MINIMUM_AIX_OS_MINOR = 2;
- bool supportsCp
@@ -16560,32 +16560,72 @@ Value *CodeGenFunction::EmitPPCBuiltinExpr(unsigned
BuiltinID,
#include "llvm/TargetParser/PPCTargetParser.def"
auto GenAIXPPCBuiltinCpuExpr = [&](unsigned SupportMethod, unsigned FieldIdx,
- unsigned CompOp,
+
@@ -364,7 +364,14 @@ class LLVM_LIBRARY_VISIBILITY PPCTargetInfo : public
TargetInfo {
// have Glibc since it is Glibc that provides the HWCAP[2] in the auxv.
static constexpr int MINIMUM_AIX_OS_MAJOR = 7;
static constexpr int MINIMUM_AIX_OS_MINOR = 2;
- bool supportsCp
https://github.com/amy-kwan commented:
Group review comments.
https://github.com/llvm/llvm-project/pull/82809
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@@ -132,6 +132,14 @@ PPC_LNX_CPU("power10",47)
#ifndef AIX_POWERPC_USE_SYS_CONF
#define AIX_POWERPC_USE_SYS_CONF
#define AIX_SYSCON_IMPL_IDX 1
+ #define AIX_SYSCON_CACHE_IDX 5
+ #define AIX_SYSCON_SMT_IDX 44
+ #define AIX_SYSCON_VMX_IDX 46
+ #define AIX_SYSCON_DFP_IDX
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@@ -16560,32 +16560,69 @@ Value *CodeGenFunction::EmitPPCBuiltinExpr(unsigned
BuiltinID,
#include "llvm/TargetParser/PPCTargetParser.def"
auto GenAIXPPCBuiltinCpuExpr = [&](unsigned SupportMethod, unsigned FieldIdx,
- unsigned CompOp,
+
@@ -145,9 +164,96 @@ namespace {
.addImm(0);
if (IsAIX) {
- // The variable offset and region handle are copied in r4 and r3. The
- // copies are followed by GETtlsADDR32AIX/GETtlsADDR64AIX
@@ -145,9 +164,96 @@ namespace {
.addImm(0);
if (IsAIX) {
- // The variable offset and region handle are copied in r4 and r3. The
- // copies are followed by GETtlsADDR32AIX/GETtlsADDR64AIX
@@ -145,9 +164,96 @@ namespace {
.addImm(0);
if (IsAIX) {
- // The variable offset and region handle are copied in r4 and r3. The
- // copies are followed by GETtlsADDR32AIX/GETtlsADDR64AIX
@@ -370,11 +370,22 @@ namespace llvm {
/// G8RC = TLSGD_AIX, TOC_ENTRY, TOC_ENTRY
/// Op that combines two register copies of TOC entries
/// (region handle into R3 and variable offset into R4) followed by a
-/// GET_TLS_ADDR node which will be expanded to a cal
@@ -145,9 +164,96 @@ namespace {
.addImm(0);
if (IsAIX) {
- // The variable offset and region handle are copied in r4 and r3. The
- // copies are followed by GETtlsADDR32AIX/GETtlsADDR64AIX
@@ -145,9 +164,96 @@ namespace {
.addImm(0);
if (IsAIX) {
- // The variable offset and region handle are copied in r4 and r3. The
- // copies are followed by GETtlsADDR32AIX/GETtlsADDR64AIX
https://github.com/amy-kwan commented:
A question: For `PPCTLSDynamicCall.cpp`, would it be better if we instead
reworded some of the sentences and not use `Load*@toc`?
I thought about this for a bit and I think the full sentences may be a bit
better, so I added some sample comment suggestions
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@@ -141,23 +149,30 @@ PPC_LNX_CPU("power10",47)
#define AIX_BUILTIN_PPC_TRUE 1
#define AIX_BUILTIN_PPC_FALSE 0
#define USE_SYS_CONF 2
+ #define SYS_CALL 3
// Supported COMPARE_OP values.
#define COMP_EQ 0
+ #define COMP_GT 1
+ #define COMP_GE 2
+ #define COMP
@@ -16560,32 +16560,69 @@ Value *CodeGenFunction::EmitPPCBuiltinExpr(unsigned
BuiltinID,
#include "llvm/TargetParser/PPCTargetParser.def"
auto GenAIXPPCBuiltinCpuExpr = [&](unsigned SupportMethod, unsigned FieldIdx,
- unsigned CompOp,
+
@@ -16560,32 +16560,69 @@ Value *CodeGenFunction::EmitPPCBuiltinExpr(unsigned
BuiltinID,
#include "llvm/TargetParser/PPCTargetParser.def"
auto GenAIXPPCBuiltinCpuExpr = [&](unsigned SupportMethod, unsigned FieldIdx,
- unsigned CompOp,
+
@@ -361,6 +439,9 @@ ABIArgInfo PPC32_SVR4_ABIInfo::classifyReturnType(QualType
RetTy) const {
return ABIArgInfo::getDirect(CoerceTy);
}
}
+ if (isComplexInRegABI && RetTy->isAnyComplexType()) {
amy-kwan wrote:
Braces not needed here.
https://git
@@ -223,6 +223,8 @@ CODEGENOPT(MCDCCoverage , 1, 0) ///< Enable MC/DC code
coverage criteria.
/// If -fpcc-struct-return or -freg-struct-return is specified.
ENUM_CODEGENOPT(StructReturnConvention, StructReturnConventionKind, 2,
SRCK_Default)
+ /// If -fcomplex-ppc-gnu-ab
@@ -2540,6 +2540,10 @@ def ffp_contract : Joined<["-"], "ffp-contract=">,
Group,
HelpText<"Form fused FP ops (e.g. FMAs)">,
Values<"fast,on,off,fast-honor-pragmas">;
+def fcomplex_ppc_gnu_abi : Flag<["-"], "fcomplex-ppc-gnu-abi">,
Group, Visibility<[ClangOption, CC1Optio
@@ -271,22 +271,33 @@ namespace {
class PPC32_SVR4_ABIInfo : public DefaultABIInfo {
bool IsSoftFloatABI;
bool IsRetSmallStructInRegABI;
+ bool isComplexInRegABI;
+ // Size of GPR in bits
amy-kwan wrote:
```suggestion
bool IsComplexInRegABI;
// Size
@@ -337,12 +350,77 @@ CharUnits
PPC32_SVR4_ABIInfo::getParamTypeAlignment(QualType Ty) const {
return CharUnits::fromQuantity(4);
}
+ABIArgInfo PPC32_SVR4_ABIInfo::handleComplex(QualType Ty,
+ uint64_t &TypeSize) const {
+
+ asse
https://github.com/amy-kwan commented:
I think the braces can also be omitted on the conditions within the `clang/*`
files.
https://github.com/llvm/llvm-project/pull/77732
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https://github.com/amy-kwan approved this pull request.
Aside from the comments about updating the assert in `SemaChecking.cpp` and the
two comments in `PPCTargetParser.def`, this also LGTM.
https://github.com/llvm/llvm-project/pull/80069
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@@ -16542,12 +16542,62 @@ Value *CodeGenFunction::EmitPPCBuiltinExpr(unsigned
BuiltinID,
Intrinsic::ID ID = Intrinsic::not_intrinsic;
+#include "llvm/TargetParser/PPCTargetParser.def"
+ // This lambda function converts builtin_cpu_is() into directly
amy-k
@@ -16542,12 +16542,62 @@ Value *CodeGenFunction::EmitPPCBuiltinExpr(unsigned
BuiltinID,
Intrinsic::ID ID = Intrinsic::not_intrinsic;
+#include "llvm/TargetParser/PPCTargetParser.def"
+ // This lambda function converts builtin_cpu_is() into directly
+ // returning true o
@@ -126,4 +126,57 @@ PPC_LNX_CPU("power10",47)
#undef PPC_LNX_DEFINE_OFFSETS
#undef PPC_LNX_FEATURE
#undef PPC_LNX_CPU
+
+// Definition of following value are found in the AIX header file
+#ifndef AIX_POWERPC_SYS_CONF
+#define AIX_POWERPC_SYS_CONF
+#define AIX_SYSCON_IMPL_IDX
@@ -126,4 +126,61 @@ PPC_LNX_CPU("power10",47)
#undef PPC_LNX_DEFINE_OFFSETS
#undef PPC_LNX_FEATURE
#undef PPC_LNX_CPU
+
+// Definition of the following values are found in the AIX header
+// file: .
+#ifndef AIX_POWERPC_USE_SYS_CONF
+ #define AIX_POWERPC_USE_SYS_CONF
+ #defi
@@ -16542,12 +16542,62 @@ Value *CodeGenFunction::EmitPPCBuiltinExpr(unsigned
BuiltinID,
Intrinsic::ID ID = Intrinsic::not_intrinsic;
+#include "llvm/TargetParser/PPCTargetParser.def"
+ // This lambda function converts builtin_cpu_is() into directly
+ // returning true o
@@ -126,4 +126,61 @@ PPC_LNX_CPU("power10",47)
#undef PPC_LNX_DEFINE_OFFSETS
#undef PPC_LNX_FEATURE
#undef PPC_LNX_CPU
+
+// Definition of the following values are found in the AIX header
+// file: .
+#ifndef AIX_POWERPC_USE_SYS_CONF
+ #define AIX_POWERPC_USE_SYS_CONF
+ #defi
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https://github.com/llvm/llvm-project/pull/67999
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https://github.com/amy-kwan approved this pull request.
Two minor nits but also LGTM.
https://github.com/llvm/llvm-project/pull/67999
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@@ -265,6 +269,62 @@ bool AIXTargetCodeGenInfo::initDwarfEHRegSizeTable(
return PPC_initDwarfEHRegSizeTable(CGF, Address, Is64Bit, /*IsAIX*/ true);
}
+void AIXTargetCodeGenInfo::setTargetAttributes(
+const Decl *D, llvm::GlobalValue *GV, CodeGen::CodeGenModule &M) const
@@ -82,8 +82,7 @@ void MCSectionXCOFF::printSwitchToSection(const MCAsmInfo
&MAI, const Triple &T,
}
if (isCsect() && getMappingClass() == XCOFF::XMC_TD) {
-assert((getKind().isBSSExtern() || getKind().isBSSLocal()) &&
- "Unexepected section kind for toc-dat
@@ -126,4 +126,53 @@ PPC_LNX_CPU("power10",47)
#undef PPC_LNX_DEFINE_OFFSETS
#undef PPC_LNX_FEATURE
#undef PPC_LNX_CPU
+
+// Definition of the following values are found in the AIX header file:
.
+#ifndef AIX_POWERPC_SYS_CONF
+#define AIX_POWERPC_SYS_CONF
+ #define AIX_SYSCON
@@ -904,8 +904,18 @@ bool PPCTargetInfo::validateCpuSupports(StringRef
FeatureStr) const {
}
bool PPCTargetInfo::validateCpuIs(StringRef CPUName) const {
+ llvm::Triple Triple = getTriple();
amy-kwan wrote:
Check clang-format for indentation.
https://githu
@@ -126,4 +126,53 @@ PPC_LNX_CPU("power10",47)
#undef PPC_LNX_DEFINE_OFFSETS
#undef PPC_LNX_FEATURE
#undef PPC_LNX_CPU
+
+// Definition of the following values are found in the AIX header file:
.
+#ifndef AIX_POWERPC_SYS_CONF
+#define AIX_POWERPC_SYS_CONF
+ #define AIX_SYSCON
@@ -126,4 +126,53 @@ PPC_LNX_CPU("power10",47)
#undef PPC_LNX_DEFINE_OFFSETS
#undef PPC_LNX_FEATURE
#undef PPC_LNX_CPU
+
+// Definition of the following values are found in the AIX header file:
.
+#ifndef AIX_POWERPC_SYS_CONF
+#define AIX_POWERPC_SYS_CONF
+ #define AIX_SYSCON
@@ -126,4 +126,53 @@ PPC_LNX_CPU("power10",47)
#undef PPC_LNX_DEFINE_OFFSETS
#undef PPC_LNX_FEATURE
#undef PPC_LNX_CPU
+
+// Definition of the following values are found in the AIX header file:
.
+#ifndef AIX_POWERPC_SYS_CONF
+#define AIX_POWERPC_SYS_CONF
+ #define AIX_SYSCON
@@ -16542,12 +16542,64 @@ Value *CodeGenFunction::EmitPPCBuiltinExpr(unsigned
BuiltinID,
Intrinsic::ID ID = Intrinsic::not_intrinsic;
+ // The lambda function converts builtin_cpu_is function into directly
+ // returning false or true, or it gets and checks the informati
@@ -126,4 +126,53 @@ PPC_LNX_CPU("power10",47)
#undef PPC_LNX_DEFINE_OFFSETS
#undef PPC_LNX_FEATURE
#undef PPC_LNX_CPU
+
+// Definition of the following values are found in the AIX header file:
.
+#ifndef AIX_POWERPC_SYS_CONF
+#define AIX_POWERPC_SYS_CONF
amy-
@@ -126,4 +126,53 @@ PPC_LNX_CPU("power10",47)
#undef PPC_LNX_DEFINE_OFFSETS
#undef PPC_LNX_FEATURE
#undef PPC_LNX_CPU
+
+// Definition of the following values are found in the AIX header file:
.
+#ifndef AIX_POWERPC_SYS_CONF
+#define AIX_POWERPC_SYS_CONF
+ #define AIX_SYSCON
@@ -362,8 +362,16 @@ class LLVM_LIBRARY_VISIBILITY PPCTargetInfo : public
TargetInfo {
// We support __builtin_cpu_supports/__builtin_cpu_is on targets that
// have Glibc since it is Glibc that provides the HWCAP[2] in the auxv.
+ static constexpr int MINIMUM_AIX_OS_MAJO
@@ -126,4 +126,53 @@ PPC_LNX_CPU("power10",47)
#undef PPC_LNX_DEFINE_OFFSETS
#undef PPC_LNX_FEATURE
#undef PPC_LNX_CPU
+
+// Definition of the following values are found in the AIX header file:
.
+#ifndef AIX_POWERPC_SYS_CONF
+#define AIX_POWERPC_SYS_CONF
+ #define AIX_SYSCON
https://github.com/amy-kwan commented:
Group review comments.
https://github.com/llvm/llvm-project/pull/80069
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https://github.com/amy-kwan edited
https://github.com/llvm/llvm-project/pull/80069
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@@ -16542,12 +16542,64 @@ Value *CodeGenFunction::EmitPPCBuiltinExpr(unsigned
BuiltinID,
Intrinsic::ID ID = Intrinsic::not_intrinsic;
+ // The lambda function converts builtin_cpu_is function into directly
+ // returning false or true, or it gets and checks the informati
@@ -16542,12 +16542,64 @@ Value *CodeGenFunction::EmitPPCBuiltinExpr(unsigned
BuiltinID,
Intrinsic::ID ID = Intrinsic::not_intrinsic;
+ // The lambda function converts builtin_cpu_is function into directly
+ // returning false or true, or it gets and checks the informati
@@ -10347,6 +10347,8 @@ def err_x86_builtin_tile_arg_duplicate : Error<
def err_builtin_target_unsupported : Error<
"builtin is not supported on this target">;
+def err_builtin_aix_os_unsupported : Error<
+ "this builtin is available only on AIX 7.2 and later operating syst
https://github.com/amy-kwan edited
https://github.com/llvm/llvm-project/pull/80069
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