https://github.com/AmrDeveloper updated
https://github.com/llvm/llvm-project/pull/141369
>From 3a8bcd052d25d138b3a9a53bbcc69d48500b4b41 Mon Sep 17 00:00:00 2001
From: AmrDeveloper
Date: Sat, 24 May 2025 14:18:06 +0200
Subject: [PATCH 1/7] [CIR] Upstream global initialization for ComplexType
--
@@ -0,0 +1,11 @@
+// RUN: cir-opt %s -verify-diagnostics -split-input-file
+
+!s32i = !cir.int
AmrDeveloper wrote:
Nice, thats better, i think i will do this with Vector too in next PR's
https://github.com/llvm/llvm-project/pull/141369
__
https://github.com/AmrDeveloper updated
https://github.com/llvm/llvm-project/pull/141369
>From 3a8bcd052d25d138b3a9a53bbcc69d48500b4b41 Mon Sep 17 00:00:00 2001
From: AmrDeveloper
Date: Sat, 24 May 2025 14:18:06 +0200
Subject: [PATCH 1/6] [CIR] Upstream global initialization for ComplexType
--
https://github.com/AmrDeveloper updated
https://github.com/llvm/llvm-project/pull/141369
>From 3a8bcd052d25d138b3a9a53bbcc69d48500b4b41 Mon Sep 17 00:00:00 2001
From: AmrDeveloper
Date: Sat, 24 May 2025 14:18:06 +0200
Subject: [PATCH 1/5] [CIR] Upstream global initialization for ComplexType
--
@@ -577,12 +577,31 @@ mlir::Attribute ConstantEmitter::tryEmitPrivate(const
APValue &value,
case APValue::Union:
cgm.errorNYI("ConstExprEmitter::tryEmitPrivate struct or union");
return {};
- case APValue::FixedPoint:
case APValue::ComplexInt:
- case APValue::Co
https://github.com/AmrDeveloper closed
https://github.com/llvm/llvm-project/pull/14
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@@ -1548,6 +1548,20 @@ OpFoldResult cir::VecExtractOp::fold(FoldAdaptor
adaptor) {
return elements[index];
}
+//===--===//
+// VecShuffleDynamicOp
+//===-
https://github.com/AmrDeveloper updated
https://github.com/llvm/llvm-project/pull/141411
>From 12295ee3a5613d7473ab33a4579015a2217617a0 Mon Sep 17 00:00:00 2001
From: AmrDeveloper
Date: Sun, 25 May 2025 17:21:34 +0200
Subject: [PATCH 1/2] [CIR] Upstream ShuffleDynamicOp for VectorType
---
cla
@@ -1427,13 +1427,13 @@ OpFoldResult cir::SelectOp::fold(FoldAdaptor adaptor) {
//===--===//
LogicalResult cir::ShiftOp::verify() {
mlir::Operation *op = getOperation();
- mlir::Type resType = getResult().g
https://github.com/AmrDeveloper updated
https://github.com/llvm/llvm-project/pull/141369
>From 3a8bcd052d25d138b3a9a53bbcc69d48500b4b41 Mon Sep 17 00:00:00 2001
From: AmrDeveloper
Date: Sat, 24 May 2025 14:18:06 +0200
Subject: [PATCH 1/4] [CIR] Upstream global initialization for ComplexType
--
@@ -385,6 +385,13 @@ mlir::Type CIRGenTypes::convertType(QualType type) {
break;
}
+ case Type::Complex: {
+const ComplexType *ct = cast(ty);
+mlir::Type elementTy = convertType(ct->getElementType());
AmrDeveloper wrote:
Thanks for your comment
https://github.com/AmrDeveloper updated
https://github.com/llvm/llvm-project/pull/141369
>From 3a8bcd052d25d138b3a9a53bbcc69d48500b4b41 Mon Sep 17 00:00:00 2001
From: AmrDeveloper
Date: Sat, 24 May 2025 14:18:06 +0200
Subject: [PATCH 1/3] [CIR] Upstream global initialization for ComplexType
--
AmrDeveloper wrote:
There will be a follow-up PR for folding
https://github.com/llvm/llvm-project/pull/141411
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https://github.com/AmrDeveloper created
https://github.com/llvm/llvm-project/pull/141411
This change adds support for the Dynamic Shuffle op for VectorType
Issue https://github.com/llvm/llvm-project/issues/136487
>From 12295ee3a5613d7473ab33a4579015a2217617a0 Mon Sep 17 00:00:00 2001
From: Amr
https://github.com/AmrDeveloper updated
https://github.com/llvm/llvm-project/pull/141369
>From 3a8bcd052d25d138b3a9a53bbcc69d48500b4b41 Mon Sep 17 00:00:00 2001
From: AmrDeveloper
Date: Sat, 24 May 2025 14:18:06 +0200
Subject: [PATCH 1/2] [CIR] Upstream global initialization for ComplexType
--
https://github.com/AmrDeveloper created
https://github.com/llvm/llvm-project/pull/141369
This change adds support for zero and global init for ComplexType
#141365
>From 3a8bcd052d25d138b3a9a53bbcc69d48500b4b41 Mon Sep 17 00:00:00 2001
From: AmrDeveloper
Date: Sat, 24 May 2025 14:18:06 +0200
S
AmrDeveloper wrote:
- This PR has implementation for the global init Complex value. I will backport
it to the incubator once it is merged.
- Not totally sure if it's good idea or not to rename it to `ConstComplexAttr`
similar to Const Array, Vector and Record, We can discuss it 馃憤馃徎
https://gi
https://github.com/AmrDeveloper updated
https://github.com/llvm/llvm-project/pull/14
>From 05ef5317602f61debe9a4d853e61a7e508a5a00d Mon Sep 17 00:00:00 2001
From: AmrDeveloper
Date: Thu, 22 May 2025 19:38:08 +0200
Subject: [PATCH 1/5] [CIR] Allow use different Int types together in Vec Shif
https://github.com/AmrDeveloper updated
https://github.com/llvm/llvm-project/pull/14
>From 875db6ee30e8075be50914f62a508511157e8a6f Mon Sep 17 00:00:00 2001
From: AmrDeveloper
Date: Thu, 22 May 2025 19:38:08 +0200
Subject: [PATCH 1/4] [CIR] Allow use different Int types together in Vec Shif
https://github.com/AmrDeveloper closed
https://github.com/llvm/llvm-project/pull/140597
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@@ -1427,13 +1427,13 @@ OpFoldResult cir::SelectOp::fold(FoldAdaptor adaptor) {
//===--===//
LogicalResult cir::ShiftOp::verify() {
mlir::Operation *op = getOperation();
- mlir::Type resType = getResult().g
https://github.com/AmrDeveloper updated
https://github.com/llvm/llvm-project/pull/14
>From 2a56a5d8db006bd466db00989806d548ce042b37 Mon Sep 17 00:00:00 2001
From: AmrDeveloper
Date: Thu, 22 May 2025 19:38:08 +0200
Subject: [PATCH 1/3] [CIR] Allow use different Int types together in Vec Shif
@@ -1427,13 +1427,13 @@ OpFoldResult cir::SelectOp::fold(FoldAdaptor adaptor) {
//===--===//
LogicalResult cir::ShiftOp::verify() {
mlir::Operation *op = getOperation();
- mlir::Type resType = getResult().g
@@ -1427,12 +1427,12 @@ OpFoldResult cir::SelectOp::fold(FoldAdaptor adaptor) {
//===--===//
LogicalResult cir::ShiftOp::verify() {
mlir::Operation *op = getOperation();
- mlir::Type resType = getResult().g
https://github.com/AmrDeveloper updated
https://github.com/llvm/llvm-project/pull/14
>From 2a56a5d8db006bd466db00989806d548ce042b37 Mon Sep 17 00:00:00 2001
From: AmrDeveloper
Date: Thu, 22 May 2025 19:38:08 +0200
Subject: [PATCH 1/2] [CIR] Allow use different Int types together in Vec Shif
https://github.com/AmrDeveloper created
https://github.com/llvm/llvm-project/pull/14
Update the verification of ShiftOp for Vector to allow performing shift op
between signed and unsigned integers, similar to LLVM IR
Issue https://github.com/llvm/llvm-project/issues/136487
>From 2a56a5d8d
https://github.com/AmrDeveloper updated
https://github.com/llvm/llvm-project/pull/123806
>From 38031e9aed519f4fd3b21dff7e79c69a0150efd9 Mon Sep 17 00:00:00 2001
From: AmrDeveloper
Date: Tue, 21 Jan 2025 20:11:21 +0100
Subject: [PATCH] [Clang] Improve testing of non std functions with name
infi
https://github.com/AmrDeveloper closed
https://github.com/llvm/llvm-project/pull/140774
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https://github.com/llvm/llvm-project/pull/140783
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AmrDeveloper wrote:
- Test cases for Unsigned and FP will be added after merging:
https://github.com/llvm/llvm-project/pull/140774
- There will be a follow-up PR for folding
https://github.com/llvm/llvm-project/pull/140597
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https://github.com/AmrDeveloper updated
https://github.com/llvm/llvm-project/pull/140597
>From e43d04b1eb1660dcf1a99d405858efd3a9647657 Mon Sep 17 00:00:00 2001
From: AmrDeveloper
Date: Sun, 18 May 2025 21:14:03 +0200
Subject: [PATCH 1/2] [CIR] Upstream comparion ops for VectorType
---
clang/
https://github.com/AmrDeveloper edited
https://github.com/llvm/llvm-project/pull/140774
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https://github.com/AmrDeveloper created
https://github.com/llvm/llvm-project/pull/140774
This change adds support for lowering BitCastOp
>From 5e5676c1e3efe38bceb09ca90a4e4b7500cbb6e8 Mon Sep 17 00:00:00 2001
From: AmrDeveloper
Date: Tue, 20 May 2025 19:29:32 +0200
Subject: [PATCH] [CIR][LL
@@ -587,3 +587,118 @@ void foo11() {
// OGCG: %[[TMP_B:.*]] = load <4 x i32>, ptr %[[VEC_B]], align 16
// OGCG: %[[XOR:.*]] = xor <4 x i32> %[[TMP_A]], %[[TMP_B]]
// OGCG: store <4 x i32> %[[XOR]], ptr {{.*}}, align 16
+
+void foo12() {
AmrDeveloper wrote:
Uns
@@ -135,4 +135,38 @@ cir.func @vector_insert_element_test() {
// CHECK:cir.return
// CHECK: }
+cir.func @vector_splat_test() {
+%0 = cir.alloca !cir.vector<4 x !s32i>, !cir.ptr>,
["a", init]
+%1 = cir.alloca !cir.vector<4 x !s32i>, !cir.ptr>,
["shl", init]
+
https://github.com/AmrDeveloper created
https://github.com/llvm/llvm-project/pull/140597
This change adds support for Cmp ops for VectorType
Issue https://github.com/llvm/llvm-project/issues/136487
>From e43d04b1eb1660dcf1a99d405858efd3a9647657 Mon Sep 17 00:00:00 2001
From: AmrDeveloper
Date
@@ -135,4 +135,38 @@ cir.func @vector_insert_element_test() {
// CHECK:cir.return
// CHECK: }
+cir.func @vector_splat_test() {
+%0 = cir.alloca !cir.vector<4 x !s32i>, !cir.ptr>,
["a", init]
+%1 = cir.alloca !cir.vector<4 x !s32i>, !cir.ptr>,
["shl", init]
+
https://github.com/AmrDeveloper closed
https://github.com/llvm/llvm-project/pull/140099
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@@ -2037,4 +2037,37 @@ def VecExtractOp : CIR_Op<"vec.extract", [Pure,
let hasFolder = 1;
}
+
+//===--===//
+// VecSplat
+//===--===//
+
+/
https://github.com/AmrDeveloper updated
https://github.com/llvm/llvm-project/pull/140099
>From ab09038c757369b0ecc6c968bb50debdc024b1ce Mon Sep 17 00:00:00 2001
From: AmrDeveloper
Date: Wed, 14 May 2025 22:25:09 +0200
Subject: [PATCH 1/3] [CIR][LLVMLowering] Upstream binary operators for
Vecto
https://github.com/AmrDeveloper updated
https://github.com/llvm/llvm-project/pull/140099
>From ab09038c757369b0ecc6c968bb50debdc024b1ce Mon Sep 17 00:00:00 2001
From: AmrDeveloper
Date: Wed, 14 May 2025 22:25:09 +0200
Subject: [PATCH 1/3] [CIR][LLVMLowering] Upstream binary operators for
Vecto
https://github.com/AmrDeveloper closed
https://github.com/llvm/llvm-project/pull/139444
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AmrDeveloper wrote:
I will quickly merge it as a fix for the previous elementTypeIfVector PR to
make it buildable
https://github.com/llvm/llvm-project/pull/140177
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https://github.com/llvm/llvm-project/pull/140177
Fix for elementTypeIfVector
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https://github.com/AmrDeveloper updated
https://github.com/llvm/llvm-project/pull/139444
>From 46d3b466df954eee87a5e5e7df5cb03802d468c7 Mon Sep 17 00:00:00 2001
From: AmrDeveloper
Date: Sat, 10 May 2025 20:37:05 +0200
Subject: [PATCH 1/2] [CIR] Upstream unary operators for VectorType
---
.../
@@ -54,10 +54,12 @@ namespace direct {
namespace {
/// If the given type is a vector type, return the vector's element type.
/// Otherwise return the given type unchanged.
-// TODO(cir): Return the vector element type once we have support for vectors
-// instead of the identity
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@@ -54,10 +54,12 @@ namespace direct {
namespace {
/// If the given type is a vector type, return the vector's element type.
/// Otherwise return the given type unchanged.
-// TODO(cir): Return the vector element type once we have support for vectors
-// instead of the identity
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https://github.com/llvm/llvm-project/pull/140099
>From de3e5aa6af44a082060ad0edc8ba9bf213b0fba5 Mon Sep 17 00:00:00 2001
From: AmrDeveloper
Date: Wed, 14 May 2025 22:25:09 +0200
Subject: [PATCH 1/2] [CIR][LLVMLowering] Upstream binary operators for
Vecto
@@ -1076,20 +1074,41 @@ mlir::LogicalResult
CIRToLLVMUnaryOpLowering::matchAndRewrite(
rewriter.replaceOp(op, adaptor.getInput());
return mlir::success();
case cir::UnaryOpKind::Minus: {
- assert(!isVector &&
- "Add vector handling when vector
https://github.com/AmrDeveloper created
https://github.com/llvm/llvm-project/pull/140125
Upstream vector support in the element type if vector as a required change for
upstreaming other Vec Ops
Issue https://github.com/llvm/llvm-project/issues/136487
>From b9f624e508db8349516f909f0c8e9cb85c04
@@ -400,4 +400,165 @@ void foo9() {
// OGCG: %[[TMP_A:.*]] = load <4 x i32>, ptr %[[VEC_A]], align 16
// OGCG: %[[TMP_B:.*]] = load <4 x i32>, ptr %[[VEC_B]], align 16
// OGCG: %[[SHR:.*]] = ashr <4 x i32> %[[TMP_A]], %[[TMP_B]]
-// OGCG: store <4 x i32> %[[SHR]], ptr %[[SHR_RE
@@ -57,7 +57,11 @@ namespace {
// TODO(cir): Return the vector element type once we have support for vectors
// instead of the identity type.
mlir::Type elementTypeIfVector(mlir::Type type) {
- assert(!cir::MissingFeatures::vectorType());
+ if (auto vecType = mlir::dyn_cast(t
https://github.com/AmrDeveloper created
https://github.com/llvm/llvm-project/pull/140099
This change adds support for binary ops for VectorType
Issue https://github.com/llvm/llvm-project/issues/136487
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AmrDeveloper wrote:
More test cases will be added when Bin and Comp operators are upstreamed for
Vector
https://github.com/llvm/llvm-project/pull/139827
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https://github.com/AmrDeveloper created
https://github.com/llvm/llvm-project/pull/139827
This change adds support for splat op for VectorType
Issue https://github.com/llvm/llvm-project/issues/136487
>From e9b7f553f7ad8a9167a9aa4a11c86ccdb8472cdd Mon Sep 17 00:00:00 2001
From: AmrDeveloper
Dat
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@@ -1399,8 +1400,10 @@ mlir::LogicalResult
CIRToLLVMShiftOpLowering::matchAndRewrite(
if (op.getIsShiftleft()) {
rewriter.replaceOpWithNewOp(op, llvmTy, val, amt);
} else {
-assert(!cir::MissingFeatures::vectorType());
-bool isUnsigned = !cirValTy.isSigned();
+
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@@ -1399,8 +1400,10 @@ mlir::LogicalResult
CIRToLLVMShiftOpLowering::matchAndRewrite(
if (op.getIsShiftleft()) {
rewriter.replaceOpWithNewOp(op, llvmTy, val, amt);
} else {
-assert(!cir::MissingFeatures::vectorType());
-bool isUnsigned = !cirValTy.isSigned();
+
https://github.com/AmrDeveloper closed
https://github.com/llvm/llvm-project/pull/138592
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@@ -213,3 +213,68 @@ void foo4() {
// OGCG: %[[TMP2:.*]] = load i32, ptr %[[IDX]], align 4
// OGCG: %[[ELE:.*]] = extractelement <4 x i32> %[[TMP1]], i32 %[[TMP2]]
// OGCG: store i32 %[[ELE]], ptr %[[INIT]], align 4
+
+void foo9() {
AmrDeveloper wrote:
Both of
@@ -1399,8 +1400,10 @@ mlir::LogicalResult
CIRToLLVMShiftOpLowering::matchAndRewrite(
if (op.getIsShiftleft()) {
rewriter.replaceOpWithNewOp(op, llvmTy, val, amt);
} else {
-assert(!cir::MissingFeatures::vectorType());
-bool isUnsigned = !cirValTy.isSigned();
+
https://github.com/AmrDeveloper closed
https://github.com/llvm/llvm-project/pull/139146
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https://github.com/AmrDeveloper created
https://github.com/llvm/llvm-project/pull/139465
This change adds support for shift ops for VectorType
Issue https://github.com/llvm/llvm-project/issues/136487
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https://github.com/AmrDeveloper created
https://github.com/llvm/llvm-project/pull/139444
This change adds support for unary ops for VectorType
Issue https://github.com/llvm/llvm-project/issues/136487
>From 9fd2f92f9122c8c79c4977e00dab93bfaa468787 Mon Sep 17 00:00:00 2001
From: AmrDeveloper
Da
https://github.com/AmrDeveloper updated
https://github.com/llvm/llvm-project/pull/138592
>From 793bd974b779450a84c72d54237067ab56a59cdc Mon Sep 17 00:00:00 2001
From: AmrDeveloper
Date: Mon, 5 May 2025 23:01:02 +0200
Subject: [PATCH 1/5] [clang][OpenMP] Add error for large expr in collapse
---
@@ -15901,6 +15901,13 @@ ExprResult
SemaOpenMP::VerifyPositiveIntegerConstantInClause(
<< E->getSourceRange();
return ExprError();
}
+
+ if (!Result.isRepresentableByInt64()) {
AmrDeveloper wrote:
In our implementation, yes, because we const ev
https://github.com/AmrDeveloper updated
https://github.com/llvm/llvm-project/pull/138592
>From 793bd974b779450a84c72d54237067ab56a59cdc Mon Sep 17 00:00:00 2001
From: AmrDeveloper
Date: Mon, 5 May 2025 23:01:02 +0200
Subject: [PATCH 1/4] [clang][OpenMP] Add error for large expr in collapse
---
AmrDeveloper wrote:
> Thank you for the fix! I've added a few more reviewers. This is a pretty
> general problem, so I think we may want additional test coverage for
> basically any of the OpenMP clauses which accept an integer argument. For
> example, this is another related issue: #139268 --
https://github.com/AmrDeveloper created
https://github.com/llvm/llvm-project/pull/139304
This change adds a folder for the VecExtractOp
Issue https://github.com/llvm/llvm-project/issues/136487
>From 6a21dc2a983094f61a54755454d12c45cf074c9d Mon Sep 17 00:00:00 2001
From: AmrDeveloper
Date: Fri
https://github.com/AmrDeveloper updated
https://github.com/llvm/llvm-project/pull/139146
>From 11de7d363ae9f06e98f15fc5c492e74a660693f8 Mon Sep 17 00:00:00 2001
From: AmrDeveloper
Date: Thu, 8 May 2025 22:10:39 +0200
Subject: [PATCH 1/3] [CIR] Upstream insert op for VectorType
---
clang/inclu
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https://github.com/llvm/llvm-project/pull/139304
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@@ -1969,6 +1969,43 @@ def VecCreateOp : CIR_Op<"vec.create", [Pure]> {
let hasVerifier = 1;
}
+//===--===//
+// VecInsertOp
+//===--===//
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https://github.com/AmrDeveloper created
https://github.com/llvm/llvm-project/pull/139146
This change adds an insert op for VectorType
Issue https://github.com/llvm/llvm-project/issues/136487
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AmrDeveloper wrote:
> In addition to the collapse clause, the ordered clause also seems to have the
> same problem. For example, does your patch also fix the following crash? If
> so, you also need tests regarding the ordered clause.
> https://godbolt.org/z/96sa5jxff
>
> ```c++
> void f(void)
https://github.com/AmrDeveloper updated
https://github.com/llvm/llvm-project/pull/138592
>From af3e49f1290c61d5856a5ddf600cfd19ef485e25 Mon Sep 17 00:00:00 2001
From: AmrDeveloper
Date: Mon, 5 May 2025 23:01:02 +0200
Subject: [PATCH 1/3] [clang][OpenMP] Add error for large expr in collapse
---
https://github.com/AmrDeveloper updated
https://github.com/llvm/llvm-project/pull/138592
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AmrDeveloper wrote:
@bcardosolopes, I think we can finish this PR, and I will continue searching
for a test case for folding without blocking upstreaming other Vector Ops.
Also, I think the same idea can be applied to Arrays, what do you think?
https://github.com/llvm/llvm-project/pull/138413
AmrDeveloper wrote:
> > > Overall looks good. While here, can you please implement a folder for
> > > this operation? It should kick-in if both idx and input vector are
> > > constants.
> >
> >
> > @bcardosolopes I implement it like this snippet
> > ```
> > OpFoldResult cir::VecExtractOp::fol
https://github.com/AmrDeveloper updated
https://github.com/llvm/llvm-project/pull/138413
>From d0a6c4fa94d387d8c9afec10deae150d6bce54ee Mon Sep 17 00:00:00 2001
From: AmrDeveloper
Date: Sat, 3 May 2025 13:43:04 +0200
Subject: [PATCH 1/3] [CIR] Upstream extract op for VectorType
---
clang/incl
AmrDeveloper wrote:
> Overall looks good. While here, can you please implement a folder for this
> operation? It should kick-in if both idx and input vector are constants.
@bcardosolopes I implement it like this snippet
```
OpFoldResult cir::VecExtractOp::fold(FoldAdaptor adaptor) {
const au
https://github.com/AmrDeveloper edited
https://github.com/llvm/llvm-project/pull/138592
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https://github.com/AmrDeveloper edited
https://github.com/llvm/llvm-project/pull/138592
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https://github.com/AmrDeveloper updated
https://github.com/llvm/llvm-project/pull/138592
>From d39464b6a17dd1a2569ba8a899f59f2c577c7e82 Mon Sep 17 00:00:00 2001
From: AmrDeveloper
Date: Mon, 5 May 2025 23:01:02 +0200
Subject: [PATCH] [clang][OpenMP] Add error for large expr in collapse
---
cl
https://github.com/AmrDeveloper created
https://github.com/llvm/llvm-project/pull/138592
Report error when OpenMP SIMD collapse clause has an expression that can't be
represented in 64-bit
Issue #138445
>From 3f484ebd84597ce803b6c9c82650ab7bf88449dd Mon Sep 17 00:00:00 2001
From: AmrDeveloper
https://github.com/AmrDeveloper closed
https://github.com/llvm/llvm-project/pull/138346
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@@ -70,12 +72,15 @@ void foo() {
// CIR: %[[VEC_E:.*]] = cir.alloca !cir.vector<4 x !s32i>,
!cir.ptr>, ["e", init]
// CIR: %[[VEC_F:.*]] = cir.alloca !cir.vector<4 x !s32i>,
!cir.ptr>, ["f", init]
// CIR: %[[VEC_G:.*]] = cir.alloca !cir.vector<4 x !s32i>,
!cir.ptr>, ["g", in
https://github.com/AmrDeveloper updated
https://github.com/llvm/llvm-project/pull/138413
>From d0a6c4fa94d387d8c9afec10deae150d6bce54ee Mon Sep 17 00:00:00 2001
From: AmrDeveloper
Date: Sat, 3 May 2025 13:43:04 +0200
Subject: [PATCH 1/2] [CIR] Upstream extract op for VectorType
---
clang/incl
https://github.com/AmrDeveloper closed
https://github.com/llvm/llvm-project/pull/138415
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https://github.com/AmrDeveloper updated
https://github.com/llvm/llvm-project/pull/138413
>From d0a6c4fa94d387d8c9afec10deae150d6bce54ee Mon Sep 17 00:00:00 2001
From: AmrDeveloper
Date: Sat, 3 May 2025 13:43:04 +0200
Subject: [PATCH 1/2] [CIR] Upstream extract op for VectorType
---
clang/incl
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