https://github.com/Amichaxx edited
https://github.com/llvm/llvm-project/pull/165282
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https://github.com/llvm/llvm-project/pull/165282
>From 9004ff2f276a1c84043577a97721049343ae8bed Mon Sep 17 00:00:00 2001
From: Amichaxx
Date: Mon, 27 Oct 2025 16:49:03 +
Subject: [PATCH 1/4] Implement widening FMMLA intrinsics
- F16 to F32
- MF8 to F32
-
https://github.com/Amichaxx updated
https://github.com/llvm/llvm-project/pull/165282
>From 9004ff2f276a1c84043577a97721049343ae8bed Mon Sep 17 00:00:00 2001
From: Amichaxx
Date: Mon, 27 Oct 2025 16:49:03 +
Subject: [PATCH 1/5] Implement widening FMMLA intrinsics
- F16 to F32
- MF8 to F32
-
https://github.com/Amichaxx updated
https://github.com/llvm/llvm-project/pull/162679
>From e654aa7c7d051e355c391f16c5ff3e152fa5784f Mon Sep 17 00:00:00 2001
From: Amichaxx
Date: Mon, 6 Oct 2025 15:42:18 +
Subject: [PATCH 1/4] [LLVM] Fix clang to emit llvm-ir for fadd/fsub atomics
Currently
https://github.com/Amichaxx edited
https://github.com/llvm/llvm-project/pull/165282
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https://github.com/Amichaxx created
https://github.com/llvm/llvm-project/pull/165282
Proposed in [this ACLE
proposal](https://github.com/ARM-software/acle/pull/409), this PR implements
widening FMMLA intrinsics.
- F16 to F32
- MF8 to F32
- MF8 to F16
>From 9004ff2f276a1c84043577a97721049343a
https://github.com/Amichaxx updated
https://github.com/llvm/llvm-project/pull/162679
>From e654aa7c7d051e355c391f16c5ff3e152fa5784f Mon Sep 17 00:00:00 2001
From: Amichaxx
Date: Mon, 6 Oct 2025 15:42:18 +
Subject: [PATCH 1/3] [LLVM] Fix clang to emit llvm-ir for fadd/fsub atomics
Currently
https://github.com/Amichaxx updated
https://github.com/llvm/llvm-project/pull/162679
>From 9004ff2f276a1c84043577a97721049343ae8bed Mon Sep 17 00:00:00 2001
From: Amichaxx
Date: Mon, 27 Oct 2025 16:49:03 +
Subject: [PATCH] Implement widening FMMLA intrinsics
- F16 to F32
- MF8 to F32
- MF8
@@ -0,0 +1,61 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
UTC_ARGS: --version 6
+// RUN: %clang_cc1 %s -emit-llvm -o - -triple=aarch64-linux-gnu | FileCheck %s
--check-prefix=CHECK-LLVM
+
+_Atomic(float) f;
Amichaxx wrote:
@@ -3854,7 +3847,16 @@ LValue ScalarExprEmitter::EmitCompoundAssignLValue(
llvm::PHINode *atomicPHI = nullptr;
if (const AtomicType *atomicTy = LHSTy->getAs()) {
QualType type = atomicTy->getValueType();
-if (!type->isBooleanType() && type->isIntegerType() &&
+c
https://github.com/Amichaxx updated
https://github.com/llvm/llvm-project/pull/162679
>From e654aa7c7d051e355c391f16c5ff3e152fa5784f Mon Sep 17 00:00:00 2001
From: Amichaxx
Date: Mon, 6 Oct 2025 15:42:18 +
Subject: [PATCH 1/3] [LLVM] Fix clang to emit llvm-ir for fadd/fsub atomics
Currently
https://github.com/Amichaxx edited
https://github.com/llvm/llvm-project/pull/160330
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https://github.com/Amichaxx updated
https://github.com/llvm/llvm-project/pull/160330
>From a8043a7fd01823f05246b857f29b0957484b5222 Mon Sep 17 00:00:00 2001
From: Amichaxx
Date: Mon, 22 Sep 2025 15:55:57 +
Subject: [PATCH 1/2] [Clang] Add support for fp when using min_fetch/max_fetch
atomi
https://github.com/Amichaxx updated
https://github.com/llvm/llvm-project/pull/162679
>From e654aa7c7d051e355c391f16c5ff3e152fa5784f Mon Sep 17 00:00:00 2001
From: Amichaxx
Date: Mon, 6 Oct 2025 15:42:18 +
Subject: [PATCH 1/2] [LLVM] Fix clang to emit llvm-ir for fadd/fsub atomics
Currently
https://github.com/Amichaxx updated
https://github.com/llvm/llvm-project/pull/160330
>From a8043a7fd01823f05246b857f29b0957484b5222 Mon Sep 17 00:00:00 2001
From: Amichaxx
Date: Mon, 22 Sep 2025 15:55:57 +
Subject: [PATCH 1/5] [Clang] Add support for fp when using min_fetch/max_fetch
atomi
Amichaxx wrote:
@efriedma-quic Hi, I've since amended as per your review. Does it look okay?
Thanks.
https://github.com/llvm/llvm-project/pull/160330
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Amichaxx wrote:
@CarolineConcatto I don't have merge access. If you could merge for me, that
would be great! Thanks.
https://github.com/llvm/llvm-project/pull/160330
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https://github.com/Amichaxx created
https://github.com/llvm/llvm-project/pull/162679
Currently, Clang emits CAS loops for atomic fp compound assignments, instead of
atomicrmw instructions. The code in CGExprScalar.cpp now checks for both
integer and floating-point atomic types and emits atomic
https://github.com/Amichaxx edited
https://github.com/llvm/llvm-project/pull/162679
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https://github.com/Amichaxx updated
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>From a8043a7fd01823f05246b857f29b0957484b5222 Mon Sep 17 00:00:00 2001
From: Amichaxx
Date: Mon, 22 Sep 2025 15:55:57 +
Subject: [PATCH 1/3] [Clang] Add support for fp when using min_fetch/max_fetch
atomi
@@ -507,20 +507,35 @@ static llvm::Value *EmitPostAtomicMinMax(CGBuilderTy
&Builder,
bool IsSigned,
llvm::Value *OldVal,
llvm::Value *RHS) {
+ llvm::Type
https://github.com/Amichaxx updated
https://github.com/llvm/llvm-project/pull/160330
>From a8043a7fd01823f05246b857f29b0957484b5222 Mon Sep 17 00:00:00 2001
From: Amichaxx
Date: Mon, 22 Sep 2025 15:55:57 +
Subject: [PATCH 1/2] [Clang] Add support for fp when using min_fetch/max_fetch
atomi
https://github.com/Amichaxx updated
https://github.com/llvm/llvm-project/pull/160330
>From a8043a7fd01823f05246b857f29b0957484b5222 Mon Sep 17 00:00:00 2001
From: Amichaxx
Date: Mon, 22 Sep 2025 15:55:57 +
Subject: [PATCH 1/2] [Clang] Add support for fp when using min_fetch/max_fetch
atomi
Amichaxx wrote:
@CarolineConcatto Thanks for pointing that out, but I am a bit apprehensive to
add Tim as he hasn't contributed to the project in nearly 2 years. Otherwise, I
have added Sema tests in a separate file.
https://github.com/llvm/llvm-project/pull/160330
https://github.com/Amichaxx edited
https://github.com/llvm/llvm-project/pull/162679
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@@ -507,20 +507,35 @@ static llvm::Value *EmitPostAtomicMinMax(CGBuilderTy
&Builder,
bool IsSigned,
llvm::Value *OldVal,
llvm::Value *RHS) {
+ llvm::Type
Amichaxx wrote:
@CarolineConcatto Sorry, I've been working on it just forgot to revert.
https://github.com/llvm/llvm-project/pull/160330
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>From a8043a7fd01823f05246b857f29b0957484b5222 Mon Sep 17 00:00:00 2001
From: Amichaxx
Date: Mon, 22 Sep 2025 15:55:57 +
Subject: [PATCH 1/2] [Clang] Add support for fp when using min_fetch/max_fetch
atomi
@@ -107,17 +107,17 @@ void test(uint8_t u8, uint16_t u16, uint32_t u32,
uint64_t u64)
// expected-error@+2 {{'svbgrp_n_u64' needs target feature
(sve,sve2,sve-bitperm)|(sme,ssve-bitperm)}}
// overload-error@+1 {{'svbgrp' needs target feature
(sve,sve2,sve-bitperm)|(sme,ss
Amichaxx wrote:
Thank you for reviewing @Lukacma.
https://github.com/llvm/llvm-project/pull/153825
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https://github.com/Amichaxx edited
https://github.com/llvm/llvm-project/pull/153825
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@@ -1828,17 +1828,19 @@ let SVETargetGuard = "sve2,lut", SMETargetGuard =
"sme2,lut" in {
// SVE2 - Optional
-let SVETargetGuard = "sve2,sve-aes", SMETargetGuard = InvalidMode in {
-def SVAESD
@@ -1,8 +1,14 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
-// RUN: %clang_cc1 -triple aarch64 -target-feature +sve -target-feature +sve2
-target-feature +sve-aes -O1 -Werror -Wall -emit-llvm -o - %s | FileCheck %s
-// RUN: %clang_cc1 -triple
@@ -15,6 +20,19 @@
#define SVE_ACLE_FUNC(A1,A2,A3,A4) A1##A2##A3##A4
#endif
+#ifdef __ARM_FEATURE_SME
+#define STREAMING __arm_streaming
+#else
+#define STREAMING
+#endif
+
+
+//
+//
+// SME-CHECK-LABEL: @_Z22test_svpmullb_pair_u64u12__SVUint64_tS_(
Amichaxx w
https://github.com/Amichaxx updated
https://github.com/llvm/llvm-project/pull/153825
>From b5d852b0b78254b8bd2e60477f2f76e254cd1096 Mon Sep 17 00:00:00 2001
From: Amina Chabane
Date: Thu, 14 Aug 2025 16:04:17 +
Subject: [PATCH 1/3] [AArch64][Clang] Update predication of SVE-AES/PMULL Pair
https://github.com/Amichaxx updated
https://github.com/llvm/llvm-project/pull/153825
>From b5d852b0b78254b8bd2e60477f2f76e254cd1096 Mon Sep 17 00:00:00 2001
From: Amina Chabane
Date: Thu, 14 Aug 2025 16:04:17 +
Subject: [PATCH 1/2] [AArch64][Clang] Update predication of SVE-AES/PMULL Pair
@@ -1828,17 +1828,19 @@ let SVETargetGuard = "sve2,lut", SMETargetGuard =
"sme2,lut" in {
// SVE2 - Optional
-let SVETargetGuard = "sve2,sve-aes", SMETargetGuard = InvalidMode in {
-def SVAESD
@@ -6,6 +6,16 @@
// RUN: %clang_cc1 -fclang-abi-compat=latest -DSVE_OVERLOADED_FORMS -triple
aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve-aes -O1
-Werror -Wall -emit-llvm -o - %s | FileCheck %s
// RUN: %clang_cc1 -fclang-abi-compat=latest -DSVE_OVERL
https://github.com/Amichaxx edited
https://github.com/llvm/llvm-project/pull/153825
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@@ -6,6 +6,16 @@
// RUN: %clang_cc1 -fclang-abi-compat=latest -DSVE_OVERLOADED_FORMS -triple
aarch64 -target-feature +sve -target-feature +sve2 -target-feature +sve-aes -O1
-Werror -Wall -emit-llvm -o - %s | FileCheck %s
// RUN: %clang_cc1 -fclang-abi-compat=latest -DSVE_OVERL
@@ -1,8 +1,14 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
-// RUN: %clang_cc1 -triple aarch64 -target-feature +sve -target-feature +sve2
-target-feature +sve-aes -O1 -Werror -Wall -emit-llvm -o - %s | FileCheck %s
-// RUN: %clang_cc1 -triple
https://github.com/Amichaxx updated
https://github.com/llvm/llvm-project/pull/153825
>From b5d852b0b78254b8bd2e60477f2f76e254cd1096 Mon Sep 17 00:00:00 2001
From: Amina Chabane
Date: Thu, 14 Aug 2025 16:04:17 +
Subject: [PATCH 1/2] [AArch64][Clang] Update predication of SVE-AES/PMULL Pair
https://github.com/Amichaxx updated
https://github.com/llvm/llvm-project/pull/153825
>From b5d852b0b78254b8bd2e60477f2f76e254cd1096 Mon Sep 17 00:00:00 2001
From: Amina Chabane
Date: Thu, 14 Aug 2025 16:04:17 +
Subject: [PATCH 1/2] [AArch64][Clang] Update predication of SVE-AES/PMULL Pair
https://github.com/Amichaxx created
https://github.com/llvm/llvm-project/pull/153825
This patch updates the predication guards for SVE2 AES and PMULL Pair
intrinsics to support execution in streaming mode.
- Updated tablegen (arm_sve.td)
- Updated existing llvm/clang codegen tests to support s
https://github.com/Amichaxx updated
https://github.com/llvm/llvm-project/pull/151703
>From ca704a51308363d6f09047d4d0a1d6e88b667a5e Mon Sep 17 00:00:00 2001
From: Amina Chabane
Date: Fri, 1 Aug 2025 14:11:19 +
Subject: [PATCH] [AArch64] Updated predication of SVE Compact intrinsic to be
av
https://github.com/Amichaxx edited
https://github.com/llvm/llvm-project/pull/151703
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@@ -594,13 +602,29 @@ define @dupq_i64_range( %a) {
;
define dso_local @dupq_f32_repeat_complex(float %x, float
%y) {
-; CHECK-LABEL: dupq_f32_repeat_complex:
-; CHECK: // %bb.0:
-; CHECK-NEXT:// kill: def $s0 killed $s0 def $z0
-; CHECK-NEXT:// kill: def $s1
@@ -980,8 +980,8 @@ defm SVCLASTA_N : SVEPerm<"svclasta[_n_{d}]", "sPsd",
"aarch64_sve_clasta_n">;
defm SVCLASTB : SVEPerm<"svclastb[_{d}]", "dPdd", "aarch64_sve_clastb">;
defm SVCLASTB_N : SVEPerm<"svclastb[_n_{d}]", "sPsd", "aarch64_sve_clastb_n">;
-let SVETargetGuard =
https://github.com/Amichaxx updated
https://github.com/llvm/llvm-project/pull/151703
>From e01d9a3d97db46db77a75d2b9727b14b8d5731d5 Mon Sep 17 00:00:00 2001
From: Amina Chabane
Date: Fri, 1 Aug 2025 14:11:19 +
Subject: [PATCH] [AArch64] Updated predication of SVE Compact intrinsic to be
av
@@ -0,0 +1,12 @@
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu \
+// RUN: -target-feature +sve -target-feature +sme -target-feature +ssve
-target-feature +sme2p2 \
+// RUN: -fsyntax-only -verify %s
+// REQUIRES: aarch64-registered-target
+// expected-no-diagnostics
+
+
+
https://github.com/Amichaxx updated
https://github.com/llvm/llvm-project/pull/151703
>From 4ecc2bcf87e9edca8a831cd253401f56ab799af9 Mon Sep 17 00:00:00 2001
From: Amina Chabane
Date: Fri, 1 Aug 2025 14:11:19 +
Subject: [PATCH 1/2] [AArch64] Updated predication of SVE Compact intrinsic to
b
Amichaxx wrote:
@paulwalker-arm I asked about the byte and halfword variants just to be sure
and I believe they are still awaiting approval, so I will be just focusing on
the word and doubleword variants in this patch.
https://github.com/llvm/llvm-project/pull/151703
__
Amichaxx wrote:
> Can you confirm you're intentionally ignoring the byte and halfword variants
> of compact that are also available with +sme2p2? This works for me, I just
> want to make sure I'm reviewing the PR properly.
No, it was an error on my part. If it's okay with you, I want to make t
https://github.com/Amichaxx updated
https://github.com/llvm/llvm-project/pull/151703
>From 4ecc2bcf87e9edca8a831cd253401f56ab799af9 Mon Sep 17 00:00:00 2001
From: Amina Chabane
Date: Fri, 1 Aug 2025 14:11:19 +
Subject: [PATCH] [AArch64] Updated predication of SVE Compact intrinsic to be
av
https://github.com/Amichaxx created
https://github.com/llvm/llvm-project/pull/151703
When the target enables +sme2p2, the svcompact intrinsic is now available in
streaming SVE mode. Amended existing ll tests sve-intrinsics-perm-select.ll and
sve2p2-intrinsics.ll. Included Sema test acle_sve_co
Amichaxx wrote:
I don't have merge access. All checks have passed now.
https://github.com/llvm/llvm-project/pull/149329
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@@ -0,0 +1,247 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
Amichaxx wrote:
I've added the flag to tests I've found to use the intrinsics and deleted my
original c test.
https://github.com/llvm/llvm-project/pull/149329
_
https://github.com/Amichaxx updated
https://github.com/llvm/llvm-project/pull/149329
>From 2895e5e7b56c1c611b39a5c85de92d18f3aae71a Mon Sep 17 00:00:00 2001
From: Amina Chabane
Date: Tue, 15 Jul 2025 15:56:49 +
Subject: [PATCH 1/7] [AArch64][NEON] Fix poly lane intrinsics under
-fno-lax-ve
https://github.com/Amichaxx updated
https://github.com/llvm/llvm-project/pull/149329
>From 2895e5e7b56c1c611b39a5c85de92d18f3aae71a Mon Sep 17 00:00:00 2001
From: Amina Chabane
Date: Tue, 15 Jul 2025 15:56:49 +
Subject: [PATCH 1/6] [AArch64][NEON] Fix poly lane intrinsics under
-fno-lax-ve
https://github.com/Amichaxx updated
https://github.com/llvm/llvm-project/pull/149329
>From 2895e5e7b56c1c611b39a5c85de92d18f3aae71a Mon Sep 17 00:00:00 2001
From: Amina Chabane
Date: Tue, 15 Jul 2025 15:56:49 +
Subject: [PATCH 1/5] [AArch64][NEON] Fix poly lane intrinsics under
-fno-lax-ve
https://github.com/Amichaxx updated
https://github.com/llvm/llvm-project/pull/149329
>From 2895e5e7b56c1c611b39a5c85de92d18f3aae71a Mon Sep 17 00:00:00 2001
From: Amina Chabane
Date: Tue, 15 Jul 2025 15:56:49 +
Subject: [PATCH 1/5] [AArch64][NEON] Fix poly lane intrinsics under
-fno-lax-ve
https://github.com/Amichaxx updated
https://github.com/llvm/llvm-project/pull/149329
>From 2895e5e7b56c1c611b39a5c85de92d18f3aae71a Mon Sep 17 00:00:00 2001
From: Amina Chabane
Date: Tue, 15 Jul 2025 15:56:49 +
Subject: [PATCH 1/5] [AArch64][NEON] Fix poly lane intrinsics under
-fno-lax-ve
https://github.com/Amichaxx updated
https://github.com/llvm/llvm-project/pull/149329
>From 2895e5e7b56c1c611b39a5c85de92d18f3aae71a Mon Sep 17 00:00:00 2001
From: Amina Chabane
Date: Tue, 15 Jul 2025 15:56:49 +
Subject: [PATCH 1/5] [AArch64][NEON] Fix poly lane intrinsics under
-fno-lax-ve
https://github.com/Amichaxx updated
https://github.com/llvm/llvm-project/pull/149329
>From 2895e5e7b56c1c611b39a5c85de92d18f3aae71a Mon Sep 17 00:00:00 2001
From: Amina Chabane
Date: Tue, 15 Jul 2025 15:56:49 +
Subject: [PATCH 1/5] [AArch64][NEON] Fix poly lane intrinsics under
-fno-lax-ve
https://github.com/Amichaxx updated
https://github.com/llvm/llvm-project/pull/149329
>From 2895e5e7b56c1c611b39a5c85de92d18f3aae71a Mon Sep 17 00:00:00 2001
From: Amina Chabane
Date: Tue, 15 Jul 2025 15:56:49 +
Subject: [PATCH 1/5] [AArch64][NEON] Fix poly lane intrinsics under
-fno-lax-ve
https://github.com/Amichaxx updated
https://github.com/llvm/llvm-project/pull/149329
>From 2895e5e7b56c1c611b39a5c85de92d18f3aae71a Mon Sep 17 00:00:00 2001
From: Amina Chabane
Date: Tue, 15 Jul 2025 15:56:49 +
Subject: [PATCH 1/7] [AArch64][NEON] Fix poly lane intrinsics under
-fno-lax-ve
https://github.com/Amichaxx updated
https://github.com/llvm/llvm-project/pull/149329
>From 2895e5e7b56c1c611b39a5c85de92d18f3aae71a Mon Sep 17 00:00:00 2001
From: Amina Chabane
Date: Tue, 15 Jul 2025 15:56:49 +
Subject: [PATCH 1/7] [AArch64][NEON] Fix poly lane intrinsics under
-fno-lax-ve
https://github.com/Amichaxx updated
https://github.com/llvm/llvm-project/pull/149329
>From 2895e5e7b56c1c611b39a5c85de92d18f3aae71a Mon Sep 17 00:00:00 2001
From: Amina Chabane
Date: Tue, 15 Jul 2025 15:56:49 +
Subject: [PATCH 1/7] [AArch64][NEON] Fix poly lane intrinsics under
-fno-lax-ve
https://github.com/Amichaxx updated
https://github.com/llvm/llvm-project/pull/149329
>From 2895e5e7b56c1c611b39a5c85de92d18f3aae71a Mon Sep 17 00:00:00 2001
From: Amina Chabane
Date: Tue, 15 Jul 2025 15:56:49 +
Subject: [PATCH 1/6] [AArch64][NEON] Fix poly lane intrinsics under
-fno-lax-ve
https://github.com/Amichaxx updated
https://github.com/llvm/llvm-project/pull/149329
>From 2895e5e7b56c1c611b39a5c85de92d18f3aae71a Mon Sep 17 00:00:00 2001
From: Amina Chabane
Date: Tue, 15 Jul 2025 15:56:49 +
Subject: [PATCH 1/6] [AArch64][NEON] Fix poly lane intrinsics under
-fno-lax-ve
@@ -1401,14 +1401,18 @@ void Intrinsic::emitBodyAsBuiltinCall() {
if (LocalCK == ClassB || (T.isHalf() && !T.isScalarForMangling())) {
CastToType.makeInteger(8, true);
Arg = "__builtin_bit_cast(" + CastToType.str() + ", " + Arg + ")";
- } else if (Loc
@@ -0,0 +1,51 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
UTC_ARGS: --version 5
+; RUN: llc -mtriple=aarch64-linux-gnu -o - %s | FileCheck %s
+
+; This test verifies that NEON intrinsics using polynomial types (poly8/16/64)
emit correct AArc
https://github.com/Amichaxx updated
https://github.com/llvm/llvm-project/pull/149329
>From 2895e5e7b56c1c611b39a5c85de92d18f3aae71a Mon Sep 17 00:00:00 2001
From: Amina Chabane
Date: Tue, 15 Jul 2025 15:56:49 +
Subject: [PATCH 1/5] [AArch64][NEON] Fix poly lane intrinsics under
-fno-lax-ve
https://github.com/Amichaxx edited
https://github.com/llvm/llvm-project/pull/149329
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https://github.com/Amichaxx created
https://github.com/llvm/llvm-project/pull/149329
Issue originally raised in
https://github.com/llvm/llvm-project/issues/71362#issuecomment-3028515618.
Certain NEON intrinsics that operate on poly types (e.g. poly8x8_t) failed to
compile with the -fno-lax-ve
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