[clang] [llvm] [HIP][HIPSTDPAR][NFC] Re-order & adapt `hipstdpar` specific passes (PR #134753)

https://github.com/AlexVlx updated https://github.com/llvm/llvm-project/pull/134753 >From a988ecf63dc79d226c2f7aa1430f65d08256888b Mon Sep 17 00:00:00 2001 From: Alex Voicu Date: Tue, 8 Apr 2025 00:20:27 +0100 Subject: [PATCH 1/7] Re-order & adapt `hipstdpar` specific passes. --- clang/lib/Co

[clang] [llvm] [HIP][HIPSTDPAR][NFC] Re-order & adapt `hipstdpar` specific passes (PR #134753)

https://github.com/AlexVlx updated https://github.com/llvm/llvm-project/pull/134753 >From a988ecf63dc79d226c2f7aa1430f65d08256888b Mon Sep 17 00:00:00 2001 From: Alex Voicu Date: Tue, 8 Apr 2025 00:20:27 +0100 Subject: [PATCH 1/7] Re-order & adapt `hipstdpar` specific passes. --- clang/lib/Co

[clang] [llvm] [HIP][HIPSTDPAR][NFC] Re-order & adapt `hipstdpar` specific passes (PR #134753)

@@ -0,0 +1,21 @@ +// Test that the accelerator code selection pass only gets invoked after linking + +// Ensure Pass HipStdParAcceleratorCodeSelectionPass is not invoked in PreLink. +// RUN: %clang_cc1 -triple amdgcn-amd-amdhsa -mllvm -amdgpu-enable-hipstdpar -flto -emit-llvm-bc

[clang] [llvm] [HIP][HIPSTDPAR][NFC] Re-order & adapt `hipstdpar` specific passes (PR #134753)

@@ -0,0 +1,21 @@ +// Test that the accelerator code selection pass only gets invoked after linking + +// Ensure Pass HipStdParAcceleratorCodeSelectionPass is not invoked in PreLink. +// RUN: %clang_cc1 -triple amdgcn-amd-amdhsa -mllvm -amdgpu-enable-hipstdpar -flto -emit-llvm-bc

[clang] [llvm] [HIP][HIPSTDPAR][NFC] Re-order & adapt `hipstdpar` specific passes (PR #134753)

@@ -0,0 +1,11 @@ +// Check that if we are compiling with fgpu-rdc amdgpu-enable-hipstdpar is not +// passed to CC1, to avoid eager, per TU, removal of potentially accessible +// functions. + +// RUN: %clang -### --hipstdpar --offload-arch=gfx906 %s -nogpulib -nogpuinc \ +// RUN:

[clang] [llvm] [HIP][HIPSTDPAR][NFC] Re-order & adapt `hipstdpar` specific passes (PR #134753)

https://github.com/AlexVlx updated https://github.com/llvm/llvm-project/pull/134753 >From a988ecf63dc79d226c2f7aa1430f65d08256888b Mon Sep 17 00:00:00 2001 From: Alex Voicu Date: Tue, 8 Apr 2025 00:20:27 +0100 Subject: [PATCH 1/6] Re-order & adapt `hipstdpar` specific passes. --- clang/lib/Co

[clang] [llvm] [HIP][HIPSTDPAR][NFC] Re-order & adapt `hipstdpar` specific passes (PR #134753)

https://github.com/AlexVlx updated https://github.com/llvm/llvm-project/pull/134753 >From a988ecf63dc79d226c2f7aa1430f65d08256888b Mon Sep 17 00:00:00 2001 From: Alex Voicu Date: Tue, 8 Apr 2025 00:20:27 +0100 Subject: [PATCH 1/5] Re-order & adapt `hipstdpar` specific passes. --- clang/lib/Co

[clang] [llvm] [HIP][HIPSTDPAR][NFC] Re-order & adapt `hipstdpar` specific passes (PR #134753)

@@ -0,0 +1,11 @@ +// Check that if we are compiling with fgpu-rdc amdgpu-enable-hipstdpar is not +// passed to CC1, to avoid eager, per TU, removal of potentially accessible +// functions. + +// RUN: %clang -### --hipstdpar --offload-arch=gfx906 %s -nogpulib -nogpuinc \ +// RUN:

[clang] [llvm] [HIP][HIPSTDPAR][NFC] Re-order & adapt `hipstdpar` specific passes (PR #134753)

@@ -883,6 +883,12 @@ void AMDGPUTargetMachine::registerPassBuilderCallbacks(PassBuilder &PB) { PB.registerFullLinkTimeOptimizationLastEPCallback( [this](ModulePassManager &PM, OptimizationLevel Level) { +// When we are using -fgpu-rdc, we can onky run accelera

[clang] [llvm] [HIP][HIPSTDPAR][NFC] Re-order & adapt `hipstdpar` specific passes (PR #134753)

https://github.com/AlexVlx updated https://github.com/llvm/llvm-project/pull/134753 >From a988ecf63dc79d226c2f7aa1430f65d08256888b Mon Sep 17 00:00:00 2001 From: Alex Voicu Date: Tue, 8 Apr 2025 00:20:27 +0100 Subject: [PATCH 1/4] Re-order & adapt `hipstdpar` specific passes. --- clang/lib/Co

[clang] [llvm] [HIP][HIPSTDPAR][NFC] Re-order & adapt `hipstdpar` specific passes (PR #134753)

https://github.com/AlexVlx updated https://github.com/llvm/llvm-project/pull/134753 >From a988ecf63dc79d226c2f7aa1430f65d08256888b Mon Sep 17 00:00:00 2001 From: Alex Voicu Date: Tue, 8 Apr 2025 00:20:27 +0100 Subject: [PATCH 1/3] Re-order & adapt `hipstdpar` specific passes. --- clang/lib/Co

[clang] [llvm] [clang][OpenMP][SPIR-V] Fix addrspace of globals and global constants (PR #134399)

@@ -37,8 +37,8 @@ static const unsigned SPIRDefIsPrivMap[] = { 0, // cuda_device 0, // cuda_constant 0, // cuda_shared -// SYCL address space values for this map are dummy -0, // sycl_global +// Most SYCL address space values for this map are dummy -

[clang] [llvm] [clang][OpenMP][SPIR-V] Fix addrspace of globals and global constants (PR #134399)

@@ -5384,6 +5384,11 @@ LangAS CodeGenModule::GetGlobalVarAddressSpace(const VarDecl *D) { LangAS AS; if (OpenMPRuntime->hasAllocateAttributeForGlobalVar(D, AS)) return AS; +if (LangOpts.OpenMPIsTargetDevice && getTriple().isSPIRV()) AlexVlx w

[clang] [llvm] [clang][OpenMP][SPIR-V] Fix addrspace of globals and global constants (PR #134399)

@@ -5384,6 +5384,11 @@ LangAS CodeGenModule::GetGlobalVarAddressSpace(const VarDecl *D) { LangAS AS; if (OpenMPRuntime->hasAllocateAttributeForGlobalVar(D, AS)) return AS; +if (LangOpts.OpenMPIsTargetDevice && getTriple().isSPIRV()) AlexVlx w

[clang] [llvm] [clang][OpenMP][SPIR-V] Fix addrspace of globals and global constants (PR #134399)

@@ -37,8 +37,8 @@ static const unsigned SPIRDefIsPrivMap[] = { 0, // cuda_device 0, // cuda_constant 0, // cuda_shared -// SYCL address space values for this map are dummy -0, // sycl_global +// Most SYCL address space values for this map are dummy -

[clang] [llvm] [clang][OpenMP][SPIR-V] Fix addrspace of globals and global constants (PR #134399)

https://github.com/AlexVlx approved this pull request. LGTM, thanks! https://github.com/llvm/llvm-project/pull/134399 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [HIP][HIPSTDPAR][NFC] Re-order & adapt `hipstdpar` specific passes (PR #134753)

https://github.com/AlexVlx commented: > Needs test Done. https://github.com/llvm/llvm-project/pull/134753 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [HIP][HIPSTDPAR][NFC] Re-order & adapt `hipstdpar` specific passes (PR #134753)

https://github.com/AlexVlx updated https://github.com/llvm/llvm-project/pull/134753 >From a988ecf63dc79d226c2f7aa1430f65d08256888b Mon Sep 17 00:00:00 2001 From: Alex Voicu Date: Tue, 8 Apr 2025 00:20:27 +0100 Subject: [PATCH 1/3] Re-order & adapt `hipstdpar` specific passes. --- clang/lib/Co

[clang] [llvm] [HIP][HIPSTDPAR][NFC] Re-order & adapt `hipstdpar` specific passes (PR #134753)

https://github.com/AlexVlx edited https://github.com/llvm/llvm-project/pull/134753 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [clang][OpenMP][SPIR-V] Fix addrspace of globals and global constants (PR #134399)

@@ -37,8 +37,8 @@ static const unsigned SPIRDefIsPrivMap[] = { 0, // cuda_device 0, // cuda_constant 0, // cuda_shared -// SYCL address space values for this map are dummy -0, // sycl_global +// Most SYCL address space values for this map are dummy -

[clang] [llvm] [AMDGPU][clang][CodeGen][opt] Add late-resolved feature identifying predicates (PR #134016)

AlexVlx wrote: > > This change adds two semi-magical builtins for AMDGPU: > > ``` > > * `__builtin_amdgcn_processor_is`, which is similar in observable behaviour > > with `__builtin_cpu_is`, except that it is never "evaluated" at run time; > > > > * `__builtin_amdgcn_is_invocable`, which is beh

[clang] [llvm] [AMDGPU][clang][CodeGen][opt] Add late-resolved feature identifying predicates (PR #134016)

@@ -4920,6 +4920,116 @@ If no address spaces names are provided, all address spaces are fenced. __builtin_amdgcn_fence(__ATOMIC_SEQ_CST, "workgroup", "local") __builtin_amdgcn_fence(__ATOMIC_SEQ_CST, "workgroup", "local", "global") +__builtin_amdgcn_processor_is and __bui

[clang] [llvm] [AMDGPU][clang][CodeGen][opt] Add late-resolved feature identifying predicates (PR #134016)

@@ -15576,6 +15609,38 @@ static bool isOverflowingIntegerType(ASTContext &Ctx, QualType T) { return Ctx.getIntWidth(T) >= Ctx.getIntWidth(Ctx.IntTy); } +static Expr *ExpandAMDGPUPredicateBI(ASTContext &Ctx, CallExpr *CE) { + if (!CE->getBuiltinCallee()) +return CXXBool

[clang] [llvm] [AMDGPU][clang][CodeGen][opt] Add late-resolved feature identifying predicates (PR #134016)

@@ -0,0 +1,64 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --check-globals all --version 5 +// RUN: %clang_cc1 -triple amdgcn-amd-amdhsa -target-cpu gfx900 -emit-llvm %s -o - | FileCheck --check-prefix=AMDGCN-GFX900 %s +// RUN: %cla

[clang] [llvm] [AMDGPU][clang][CodeGen][opt] Add late-resolved feature identifying predicates (PR #134016)

https://github.com/AlexVlx updated https://github.com/llvm/llvm-project/pull/134016 >From 91eeaf02336e539f14dcb0a79ff15dbe8befe6f1 Mon Sep 17 00:00:00 2001 From: Alex Voicu Date: Wed, 2 Apr 2025 02:47:42 +0100 Subject: [PATCH 1/7] Add the functional identity and feature queries. --- clang/doc

[clang] [llvm] [clang][OpenMP][SPIR-V] Fix addrspace of globals and global constants (PR #134399)

@@ -5384,6 +5384,11 @@ LangAS CodeGenModule::GetGlobalVarAddressSpace(const VarDecl *D) { LangAS AS; if (OpenMPRuntime->hasAllocateAttributeForGlobalVar(D, AS)) return AS; +if (LangOpts.OpenMPIsTargetDevice && getTriple().isSPIRV()) AlexVlx w

[clang] [llvm] [clang][OpenMP][SPIR-V] Fix addrspace of globals and global constants (PR #134399)

@@ -5402,6 +5407,10 @@ LangAS CodeGenModule::GetGlobalConstantAddressSpace() const { // UniformConstant storage class is not viable as pointers to it may not be // casted to Generic pointers which are used to model HIP's "flat" pointers. return LangAS::cuda_device

[clang] [llvm] [AMDGPU][clang][CodeGen][opt] Add late-resolved feature identifying predicates (PR #134016)

AlexVlx wrote: > So in short: what you're trying to prevent is "this was stored in a variable, > then checked later when we are no longer on the device, thus the answer is > different". Not quite, although that is definitely an interesting consideration. What I am trying to address here is t

[clang] [llvm] [AMDGPU][clang][CodeGen][opt] Add late-resolved feature identifying predicates (PR #134016)

AlexVlx wrote: > > as a must have, it allows featureful AMDGCN flavoured SPIR-V to be > > produced, where target specific capability is guarded and chosen or > > discarded when finalising compilation for a concrete target. > > I understand the reasoning behind providing such mechanisms to guar

[clang] [llvm] [AMDGPU][clang][CodeGen][opt] Add late-resolved feature identifying predicates (PR #134016)

https://github.com/AlexVlx updated https://github.com/llvm/llvm-project/pull/134016 >From 91eeaf02336e539f14dcb0a79ff15dbe8befe6f1 Mon Sep 17 00:00:00 2001 From: Alex Voicu Date: Wed, 2 Apr 2025 02:47:42 +0100 Subject: [PATCH 01/10] Add the functional identity and feature queries. --- clang/d

[clang] [llvm] [AMDGPU][clang][CodeGen][opt] Add late-resolved feature identifying predicates (PR #134016)

https://github.com/AlexVlx updated https://github.com/llvm/llvm-project/pull/134016 >From 91eeaf02336e539f14dcb0a79ff15dbe8befe6f1 Mon Sep 17 00:00:00 2001 From: Alex Voicu Date: Wed, 2 Apr 2025 02:47:42 +0100 Subject: [PATCH 01/11] Add the functional identity and feature queries. --- clang/d

[clang] [llvm] [AMDGPU][clang][CodeGen][opt] Add late-resolved feature identifying predicates (PR #134016)

@@ -4920,6 +4920,116 @@ If no address spaces names are provided, all address spaces are fenced. __builtin_amdgcn_fence(__ATOMIC_SEQ_CST, "workgroup", "local") __builtin_amdgcn_fence(__ATOMIC_SEQ_CST, "workgroup", "local", "global") +__builtin_amdgcn_processor_is and __bui

[clang] [llvm] [AMDGPU][clang][CodeGen][opt] Add late-resolved feature identifying predicates (PR #134016)

@@ -4920,6 +4920,116 @@ If no address spaces names are provided, all address spaces are fenced. __builtin_amdgcn_fence(__ATOMIC_SEQ_CST, "workgroup", "local") __builtin_amdgcn_fence(__ATOMIC_SEQ_CST, "workgroup", "local", "global") +__builtin_amdgcn_processor_is and __bui

[clang] [llvm] [AMDGPU][clang][CodeGen][opt] Add late-resolved feature identifying predicates (PR #134016)

@@ -4920,6 +4920,116 @@ If no address spaces names are provided, all address spaces are fenced. __builtin_amdgcn_fence(__ATOMIC_SEQ_CST, "workgroup", "local") __builtin_amdgcn_fence(__ATOMIC_SEQ_CST, "workgroup", "local", "global") +__builtin_amdgcn_processor_is and __bui

[clang] [llvm] [AMDGPU][clang][CodeGen][opt] Add late-resolved feature identifying predicates (PR #134016)

@@ -585,6 +597,23 @@ Value *CodeGenFunction::EmitAMDGPUBuiltinExpr(unsigned BuiltinID, llvm::Value *Env = EmitScalarExpr(E->getArg(0)); return Builder.CreateCall(F, {Env}); } + case AMDGPU::BI__builtin_amdgcn_processor_is: { +assert(CGM.getTriple().isSPIRV() &&

[clang] [llvm] [AMDGPU][clang][CodeGen][opt] Add late-resolved feature identifying predicates (PR #134016)

@@ -0,0 +1,64 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --check-globals all --version 5 +// RUN: %clang_cc1 -triple amdgcn-amd-amdhsa -target-cpu gfx900 -emit-llvm %s -o - | FileCheck --check-prefix=AMDGCN-GFX900 %s +// RUN: %cla

[clang] [llvm] [AMDGPU][clang][CodeGen][opt] Add late-resolved feature identifying predicates (PR #134016)

https://github.com/AlexVlx updated https://github.com/llvm/llvm-project/pull/134016 >From 91eeaf02336e539f14dcb0a79ff15dbe8befe6f1 Mon Sep 17 00:00:00 2001 From: Alex Voicu Date: Wed, 2 Apr 2025 02:47:42 +0100 Subject: [PATCH 1/9] Add the functional identity and feature queries. --- clang/doc

[clang] [llvm] [AMDGPU][clang][CodeGen][opt] Add late-resolved feature identifying predicates (PR #134016)

https://github.com/AlexVlx updated https://github.com/llvm/llvm-project/pull/134016 >From 91eeaf02336e539f14dcb0a79ff15dbe8befe6f1 Mon Sep 17 00:00:00 2001 From: Alex Voicu Date: Wed, 2 Apr 2025 02:47:42 +0100 Subject: [PATCH 1/8] Add the functional identity and feature queries. --- clang/doc

[clang] [llvm] [AMDGPU][clang][CodeGen][opt] Add late-resolved feature identifying predicates (PR #134016)

@@ -284,6 +284,18 @@ void CodeGenFunction::AddAMDGPUFenceAddressSpaceMMRA(llvm::Instruction *Inst, Inst->setMetadata(LLVMContext::MD_mmra, MMRAMetadata::getMD(Ctx, MMRAs)); } +static Value *GetOrInsertAMDGPUPredicate(CodeGenFunction &CGF, Twine Name) { + auto PTy = Integer

[clang] [llvm] [AMDGPU][clang][CodeGen][opt] Add late-resolved feature identifying predicates (PR #134016)

@@ -15576,6 +15609,38 @@ static bool isOverflowingIntegerType(ASTContext &Ctx, QualType T) { return Ctx.getIntWidth(T) >= Ctx.getIntWidth(Ctx.IntTy); } +static Expr *ExpandAMDGPUPredicateBI(ASTContext &Ctx, CallExpr *CE) { + if (!CE->getBuiltinCallee()) +return CXXBool

[clang] [llvm] [AMDGPU][clang][CodeGen][opt] Add late-resolved feature identifying predicates (PR #134016)

@@ -585,6 +597,23 @@ Value *CodeGenFunction::EmitAMDGPUBuiltinExpr(unsigned BuiltinID, llvm::Value *Env = EmitScalarExpr(E->getArg(0)); return Builder.CreateCall(F, {Env}); } + case AMDGPU::BI__builtin_amdgcn_processor_is: { +assert(CGM.getTriple().isSPIRV() &&

[clang] [llvm] [AMDGPU][clang][CodeGen][opt] Add late-resolved feature identifying predicates (PR #134016)

@@ -4920,6 +4920,116 @@ If no address spaces names are provided, all address spaces are fenced. __builtin_amdgcn_fence(__ATOMIC_SEQ_CST, "workgroup", "local") __builtin_amdgcn_fence(__ATOMIC_SEQ_CST, "workgroup", "local", "global") +__builtin_amdgcn_processor_is and __bui

[clang] [llvm] [AMDGPU][clang][CodeGen][opt] Add late-resolved feature identifying predicates (PR #134016)

https://github.com/AlexVlx updated https://github.com/llvm/llvm-project/pull/134016 >From 91eeaf02336e539f14dcb0a79ff15dbe8befe6f1 Mon Sep 17 00:00:00 2001 From: Alex Voicu Date: Wed, 2 Apr 2025 02:47:42 +0100 Subject: [PATCH 1/5] Add the functional identity and feature queries. --- clang/doc

[clang] [llvm] [AMDGPU][clang][CodeGen][opt] Add late-resolved feature identifying predicates (PR #134016)

https://github.com/AlexVlx updated https://github.com/llvm/llvm-project/pull/134016 >From 91eeaf02336e539f14dcb0a79ff15dbe8befe6f1 Mon Sep 17 00:00:00 2001 From: Alex Voicu Date: Wed, 2 Apr 2025 02:47:42 +0100 Subject: [PATCH 1/6] Add the functional identity and feature queries. --- clang/doc

[clang] [llvm] [AMDGPU][clang][CodeGen][opt] Add late-resolved feature identifying predicates (PR #134016)

https://github.com/AlexVlx updated https://github.com/llvm/llvm-project/pull/134016 >From 91eeaf02336e539f14dcb0a79ff15dbe8befe6f1 Mon Sep 17 00:00:00 2001 From: Alex Voicu Date: Wed, 2 Apr 2025 02:47:42 +0100 Subject: [PATCH 1/4] Add the functional identity and feature queries. --- clang/doc

[clang] [llvm] [AMDGPU][clang][CodeGen][opt] Add late-resolved feature identifying predicates (PR #134016)

AlexVlx wrote: > This is worth a release note item. Indeed! I botched moving the changes from my internal scratchpad, and the rel notes got lost; fixing. https://github.com/llvm/llvm-project/pull/134016 ___ cfe-commits mailing list cfe-commits@lists.

[clang] [llvm] [AMDGPU][clang][CodeGen][opt] Add late-resolved feature identifying predicates (PR #134016)

@@ -0,0 +1,64 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --check-globals all --version 5 +// RUN: %clang_cc1 -triple amdgcn-amd-amdhsa -target-cpu gfx900 -emit-llvm %s -o - | FileCheck --check-prefix=AMDGCN-GFX900 %s +// RUN: %cla

[clang] [llvm] [AMDGPU][clang][CodeGen][opt] Add late-resolved feature identifying predicates (PR #134016)

https://github.com/AlexVlx updated https://github.com/llvm/llvm-project/pull/134016 >From 91eeaf02336e539f14dcb0a79ff15dbe8befe6f1 Mon Sep 17 00:00:00 2001 From: Alex Voicu Date: Wed, 2 Apr 2025 02:47:42 +0100 Subject: [PATCH 1/3] Add the functional identity and feature queries. --- clang/doc

[clang] [llvm] [AMDGPU][clang][CodeGen][opt] Add late-resolved feature identifying predicates (PR #134016)

https://github.com/AlexVlx updated https://github.com/llvm/llvm-project/pull/134016 >From 91eeaf02336e539f14dcb0a79ff15dbe8befe6f1 Mon Sep 17 00:00:00 2001 From: Alex Voicu Date: Wed, 2 Apr 2025 02:47:42 +0100 Subject: [PATCH 1/2] Add the functional identity and feature queries. --- clang/doc

[clang] [llvm] [AMDGPU][clang][CodeGen][opt] Add late-resolved feature identifying predicates (PR #134016)

https://github.com/AlexVlx created https://github.com/llvm/llvm-project/pull/134016 This change adds two semi-magical builtins for AMDGPU: - `__builtin_amdgcn_processor_is`, which is similar in observable behaviour with `__builtin_cpu_is`, except that it is never "evaluated" at run time; - `__

[clang] [NFC][Driver][HIP] Fix mixing `amdgcnspirv` and `gfxXXX` via `--offload-arch` (PR #133024)

https://github.com/AlexVlx closed https://github.com/llvm/llvm-project/pull/133024 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [NFC][Driver][HIP] Fix mixing `amdgcnspirv` and `gfxXXX` via `--offload-arch` (PR #133024)

https://github.com/AlexVlx created https://github.com/llvm/llvm-project/pull/133024 Due to `amdgcnspirv` piggybacking on the HIPAMDToolchain, it loses its immediately apparent SPIR-Vness, which makes the Driver want to go all the way to Assembly emmission. This was problematic as we were tryin

[clang] [llvm] [SPIRV] GPU intrinsics (PR #131190)

AlexVlx wrote: > > not everything should end up in Clang, even though it is individually > > "convenient" > > We should at least have some builtins for those SPIR-V intrinsics you listed. > I think right now we only have `reflect`. Probably, I think there's a sense that in general it's desira

[clang] [llvm] [SPIRV] GPU intrinsics (PR #131190)

AlexVlx wrote: I'm not convinced we should do this, as I have a bunch of concerns: - it's intrusive and duplicates work already done by [libclc](https://github.com/llvm/llvm-project/tree/main/libclc); - [SPIRV already has intrinsics](https://github.com/llvm/llvm-project/blob/main/llvm/include/

[clang] [clang][SPIR-V] Use the SPIR-V backend by default (PR #129545)

https://github.com/AlexVlx approved this pull request. https://github.com/llvm/llvm-project/pull/129545 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [clang][SPIR-V] Use the SPIR-V backend by default (PR #129545)

AlexVlx wrote: LGTM, thanks! In what regards the translator use in the HIP Toolchain, from the AMD side we're looking at transitioning to the BE as soon as possible, but it will probably be some time until we have fully validated it. https://github.com/llvm/llvm-project/pull/129545 ___

[clang] [Clang] Treat `ext_vector_type` as a regular type attribute (PR #130177)

AlexVlx wrote: > > I'm not super thrilled about NOT having to introduce a type name, I'm not > > looking forward to the exciting world of `void foo(int > > __attribute__((ext_vector_type(4))) x)` replacing `void foo(int4 x)`. > > This makes introducing a type name easier because you can use `u

[clang] [Clang] Treat `ext_vector_type` as a regular type attribute (PR #130177)

AlexVlx wrote: I'm not super thrilled about NOT having to introduce a type name, I'm not looking forward to the exciting world of `void foo(int __attribute__((ext_vector_type(4))) x)` replacing `void foo(int4 x)`. I am extremely not at ease with flipping this to be a C++ attribute. Back in th

[clang] clang: Do not implicitly addrspacecast in EmitAggExprToLValue (PR #129837)

https://github.com/AlexVlx requested changes to this pull request. I'm temporarily blocking this to go through a bit more than OCL - I just want to ensure that this doesn't break some C/C++ corner case. Otherwise LGTM. https://github.com/llvm/llvm-project/pull/129837 ___

[clang] [clang][HIP] Make some math not not work with AMDGCN SPIR-V (PR #128360)

AlexVlx wrote: > > This seems to break tests: http://45.33.8.238/linux/161683/step_6.txt > > Please take a look and revert for now if it takes a while to fix. > > Should be fixed within the next 30 mins or so, if not I'll revert, apologies > for the inconvenience. I've reverted this for now, e

[clang] [clang][CodeGen][OpenCL] Fix `alloca` handling (PR #113930)

https://github.com/AlexVlx edited https://github.com/llvm/llvm-project/pull/113930 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [clang][CodeGen][OpenCL] Fix `alloca` handling (PR #113930)

https://github.com/AlexVlx edited https://github.com/llvm/llvm-project/pull/113930 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [clang][CodeGen][OpenCL] Fix `alloca` handling when compiling for (PR #113930)

https://github.com/AlexVlx edited https://github.com/llvm/llvm-project/pull/113930 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] Reapply "[clang][HIP] Make some math not not work with AMDGCN SPIR-V #128360" (PR #129306)

https://github.com/AlexVlx closed https://github.com/llvm/llvm-project/pull/129306 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [NFC] Ensure the SPIRV target is enabled for test that uses AMDGCNSPIRV (PR #129298)

https://github.com/AlexVlx closed https://github.com/llvm/llvm-project/pull/129298 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] Revert "[clang][HIP] Make some math not not work with AMDGCN SPIR-V" (PR #129280)

https://github.com/AlexVlx closed https://github.com/llvm/llvm-project/pull/129280 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [clang][HIP] Make some math not not work with AMDGCN SPIR-V (PR #128360)

AlexVlx wrote: > This seems to break tests: http://45.33.8.238/linux/161683/step_6.txt > > Please take a look and revert for now if it takes a while to fix. Should be fixed within the next 30 mins or so, if not I'll revert, apologies for the inconvenience. https://github.com/llvm/llvm-project

[clang] [clang][HIP] Make some math not not work with AMDGCN SPIR-V (PR #128360)

https://github.com/AlexVlx closed https://github.com/llvm/llvm-project/pull/128360 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [NFC] Fix Sanitizer breakage introduced in #128166 (PR #128990)

https://github.com/AlexVlx closed https://github.com/llvm/llvm-project/pull/128990 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [clang][CodeGen] Additional fixes for #114062 (PR #128166)

https://github.com/AlexVlx updated https://github.com/llvm/llvm-project/pull/128166 >From 77db8a15d472e112be93cb7566cf56e26dc80501 Mon Sep 17 00:00:00 2001 From: Alex Voicu Date: Fri, 21 Feb 2025 13:47:42 +0200 Subject: [PATCH 1/5] Handle HLL casts on sret args, remove ill advised cast strip a

[clang] [clang][CodeGen] Additional fixes for #114062 (PR #128166)

https://github.com/AlexVlx updated https://github.com/llvm/llvm-project/pull/128166 >From 77db8a15d472e112be93cb7566cf56e26dc80501 Mon Sep 17 00:00:00 2001 From: Alex Voicu Date: Fri, 21 Feb 2025 13:47:42 +0200 Subject: [PATCH 1/5] Handle HLL casts on sret args, remove ill advised cast strip a

[clang] [clang][CodeGen] Additional fixes for #114062 (PR #128166)

@@ -2352,6 +2353,22 @@ Value *ScalarExprEmitter::VisitCastExpr(CastExpr *CE) { Value *Src = Visit(const_cast(E)); llvm::Type *SrcTy = Src->getType(); llvm::Type *DstTy = ConvertType(DestTy); + +// FIXME: this is a gross but seemingly necessary workaround for an

[clang] [spirv][amdgpu] Set atomic size in the clang target info (PR #128569)

https://github.com/AlexVlx approved this pull request. LGTM, thanks. FWIW we've only done HIP bring-up, so there will probably be a few of these lingering. https://github.com/llvm/llvm-project/pull/128569 ___ cfe-commits mailing list cfe-commits@lists

[clang] [clang][HIP] Make some math not not work with AMDGCN SPIR-V (PR #128360)

@@ -14,6 +14,12 @@ #include "hip/hip_version.h" #endif // __has_include("hip/hip_version.h") +#ifdef __SPIRV__ +#define __PRIVATE_AS __attribute__((address_space(0))) AlexVlx wrote: Acknowledged, but the header was already using numbered address spaces (ROCDL

[clang] [clang][CodeGen] Additional fixes for #114062 (PR #128166)

https://github.com/AlexVlx edited https://github.com/llvm/llvm-project/pull/128166 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [clang][CodeGen] Additional fixes for #114062 (PR #128166)

@@ -0,0 +1,32 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 5 +// RUN: %clang_cc1 -triple amdgcn-amd-amdhsa-gnu -target-cpu gfx900 -emit-llvm -o - %s | FileCheck %s + +struct X { int z[17]; }; + +// CHECK-LABEL: define dso_

[clang] [clang][CodeGen] Additional fixes for #114062 (PR #128166)

https://github.com/AlexVlx updated https://github.com/llvm/llvm-project/pull/128166 >From 77db8a15d472e112be93cb7566cf56e26dc80501 Mon Sep 17 00:00:00 2001 From: Alex Voicu Date: Fri, 21 Feb 2025 13:47:42 +0200 Subject: [PATCH 1/4] Handle HLL casts on sret args, remove ill advised cast strip a

[clang] [clang][CodeGen] Additional fixes for #114062 (PR #128166)

@@ -0,0 +1,38 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --include-generated-funcs --version 5 +// RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple amdgcn-amd-amdhsa -fopenmp-targets=amdgcn-amd-amdhsa -emit-llvm %s -fopenmp-is-t

[clang] [clang][CodeGen] Additional fixes for #114062 (PR #128166)

@@ -2352,6 +2353,22 @@ Value *ScalarExprEmitter::VisitCastExpr(CastExpr *CE) { Value *Src = Visit(const_cast(E)); llvm::Type *SrcTy = Src->getType(); llvm::Type *DstTy = ConvertType(DestTy); + +// FIXME: this is a gross but seemingly necessary workaround for an

[clang] [clang][CodeGen] Additional fixes for #114062 (PR #128166)

@@ -2352,6 +2353,22 @@ Value *ScalarExprEmitter::VisitCastExpr(CastExpr *CE) { Value *Src = Visit(const_cast(E)); llvm::Type *SrcTy = Src->getType(); llvm::Type *DstTy = ConvertType(DestTy); + +// FIXME: this is a gross but seemingly necessary workaround for an

[clang] [clang][CodeGen] Additional fixes for #114062 (PR #128166)

https://github.com/AlexVlx updated https://github.com/llvm/llvm-project/pull/128166 >From 77db8a15d472e112be93cb7566cf56e26dc80501 Mon Sep 17 00:00:00 2001 From: Alex Voicu Date: Fri, 21 Feb 2025 13:47:42 +0200 Subject: [PATCH 1/3] Handle HLL casts on sret args, remove ill advised cast strip a

[clang] [clang][CodeGen] Additional fixes for #114062 (PR #128166)

https://github.com/AlexVlx updated https://github.com/llvm/llvm-project/pull/128166 >From 77db8a15d472e112be93cb7566cf56e26dc80501 Mon Sep 17 00:00:00 2001 From: Alex Voicu Date: Fri, 21 Feb 2025 13:47:42 +0200 Subject: [PATCH 1/2] Handle HLL casts on sret args, remove ill advised cast strip a

[clang] [clang][CodeGen] Additional fixes for #114062 (PR #128166)

https://github.com/AlexVlx created https://github.com/llvm/llvm-project/pull/128166 This addresses two issues introduced by moving indirect args into an explicit AS (please see and

[clang] [clang][CodeGen] `sret` args should always point to the `alloca` AS, so use that (PR #114062)

AlexVlx wrote: > > seeing breaks in downstream build of rocPRIM > > Probably need to revert the downstream revert of the original problematic > patch It's not quite that, we have a problem with the following pattern: . `r` is a returned val so it will come

[clang] [NFC][Clang][CodeGen] Remove vestigial assertion (PR #127528)

https://github.com/AlexVlx closed https://github.com/llvm/llvm-project/pull/127528 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [clang][CodeGen] `sret` args should always point to the `alloca` AS, so use that (PR #114062)

AlexVlx wrote: > @AlexVlx I found this breaks my clang build, reduced the C++ source to the > following reproducer https://godbolt.org/z/jGnvKeqvr. Please verify that it > breaks for you as well and revert or fix. (The issue is the s() function call > not using AS(5)) > > ```c++ > #pragma omp

[clang] [NFC][Clang][CodeGen] Remove vestigial assertion (PR #127528)

https://github.com/AlexVlx created https://github.com/llvm/llvm-project/pull/127528 This removes a vestigial assertion, which would erroneously trigger even though we now correctly handle valid arg mismatches (

[clang] [clang][CodeGen] `sret` args should always point to the `alloca` AS, so use that (PR #114062)

https://github.com/AlexVlx closed https://github.com/llvm/llvm-project/pull/114062 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [clang][CodeGen] `sret` args should always point to the `alloca` AS, so use that (PR #114062)

https://github.com/AlexVlx commented: > We can't keep waiting for this to get in the release I'll merge later today once CI passes. https://github.com/llvm/llvm-project/pull/114062 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://list

[clang] [clang][CodeGen] `sret` args should always point to the `alloca` AS, so use that (PR #114062)

https://github.com/AlexVlx edited https://github.com/llvm/llvm-project/pull/114062 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [clang][CodeGen] `sret` args should always point to the `alloca` AS, so use that (PR #114062)

AlexVlx wrote: > ping, this really needs to be in the release branch. The device library build > is broken without this @rjmccall any additional issues / comments / suggestions / objections? https://github.com/llvm/llvm-project/pull/114062 ___ cfe-co

[clang] [CUDA] Precommit test for VTable codegen (PR #124983)

AlexVlx wrote: Could you please add another RUN line for SPIRV? That’d just use the spirv64-amd-amdhsa triple; you will need a different prefix as it has a different AS map. https://github.com/llvm/llvm-project/pull/124983 ___ cfe-commits mailing li

[clang] [NFC][docs][HIP] Update HIP docs around `hipstdpar` and SPIR-V (PR #124803)

https://github.com/AlexVlx closed https://github.com/llvm/llvm-project/pull/124803 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [NFC][docs][HIP] Update HIP docs around `hipstdpar` and SPIR-V (PR #124803)

AlexVlx wrote: > LLVM Buildbot has detected a new failure on builder > `openmp-offload-libc-amdgpu-runtime` running on `omp-vega20-1` while building > `clang` at step 7 "Add check check-offload". > > Full details are available at: > https://lab.llvm.org/buildbot/#/builders/73/builds/12605 >

[clang] [NFC][docs][HIP] Update HIP docs around `hipstdpar` and SPIR-V (PR #124803)

https://github.com/AlexVlx updated https://github.com/llvm/llvm-project/pull/124803 >From ed7ee56acc5434233191cfb1c556165f193c4005 Mon Sep 17 00:00:00 2001 From: Alex Voicu Date: Tue, 28 Jan 2025 17:45:07 + Subject: [PATCH 1/3] Add missing `hipstdpar` documentation; remove reference to tem

[clang] [NFC][docs][HIP] Update HIP docs around `hipstdpar` and SPIR-V (PR #124803)

https://github.com/AlexVlx updated https://github.com/llvm/llvm-project/pull/124803 >From ed7ee56acc5434233191cfb1c556165f193c4005 Mon Sep 17 00:00:00 2001 From: Alex Voicu Date: Tue, 28 Jan 2025 17:45:07 + Subject: [PATCH 1/2] Add missing `hipstdpar` documentation; remove reference to tem

[clang] [NFC][docs][HIP] Update HIP docs around `hipstdpar` and SPIR-V (PR #124803)

https://github.com/AlexVlx created https://github.com/llvm/llvm-project/pull/124803 This addresses an odd ommision from the 19 release cycle, wherein we upstreamed HIPSTDPAR support without adding the relevant documentation. As an added bonus, we also remove a reference to `amdgcnspirv` not mi

[clang] [clang][CodeGen] `sret` args should always point to the `alloca` AS, so use that (PR #114062)

https://github.com/AlexVlx commented: Gentle ping. https://github.com/llvm/llvm-project/pull/114062 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [clang][CodeGen] `sret` args should always point to the `alloca` AS, so use that (PR #114062)

https://github.com/AlexVlx edited https://github.com/llvm/llvm-project/pull/114062 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [AMDGPU] Use the AMDGPUToolChain when targeting C/C++ directly (PR #99687)

AlexVlx wrote: > > It is six months old, but it is relatively difficult to keep track of all > > the concurrent non-communicating swimlanes - I do apologise for not having > > done so though! It is possible that we are microfocusing on a potential use > > case, but there are other valid ones.

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