https://github.com/ahmednoursphinx created
https://github.com/llvm/llvm-project/pull/168757
Part of https://github.com/llvm/llvm-project/issues/167765
>From 2f02de39803ff7ebde3e52ac60dabbb3d062515c Mon Sep 17 00:00:00 2001
From: ahmed
Date: Wed, 19 Nov 2025 12:46:29 +0200
Subject: [PATCH 1/3]
https://github.com/ahmednoursphinx updated
https://github.com/llvm/llvm-project/pull/167683
>From e91be48deb3f895f88e9ab6a34ffd730e3fce47f Mon Sep 17 00:00:00 2001
From: ahmed
Date: Wed, 12 Nov 2025 13:01:46 +0200
Subject: [PATCH 1/8] [clang] Add _mm512_kunpackd and _mm512_kunpackw to
avx512fi
@@ -8383,24 +8383,30 @@ _mm512_maskz_moveldup_ps(__mmask16 __U, __m512 __A) {
(__v16sf)_mm512_setzero_ps());
}
-static __inline__ __m128 __DEFAULT_FN_ATTRS128_CONSTEXPR
-_mm_mask_move_ss(__m128 __W, __mmask8 __U, __m128 __A, __m128
@@ -9126,6 +9126,24 @@ __mmask16 test_mm512_kunpackb(__m512i __A, __m512i __B,
__m512i __C, __m512i __D
__E, __F);
}
+TEST_CONSTEXPR(_mm512_kunpackb(0xFF00, 0x00FF) == 0x00FF);
+TEST_CONSTEXPR(_mm512_kunpackb(0xABCD, 0x12
@@ -16287,6 +16287,42 @@ bool IntExprEvaluator::VisitBuiltinCallExpr(const
CallExpr *E,
return Success((A | B) == 0, E);
}
+ case clang::X86::BI__builtin_ia32_kunpckhi: {
+APSInt A, B;
+if (!EvaluateInteger(E->getArg(0), A, Info) ||
+!EvaluateInteger(E-
@@ -13373,6 +13373,35 @@ bool VectorExprEvaluator::VisitCallExpr(const CallExpr
*E) {
}
return Success(APValue(ResultElements.data(), ResultElements.size()), E);
}
+ case clang::X86::BI__builtin_ia32_addsubpd:
+ case clang::X86::BI__builtin_ia32_addsubps:
+ case c
https://github.com/ahmednoursphinx updated
https://github.com/llvm/llvm-project/pull/167683
>From e91be48deb3f895f88e9ab6a34ffd730e3fce47f Mon Sep 17 00:00:00 2001
From: ahmed
Date: Wed, 12 Nov 2025 13:01:46 +0200
Subject: [PATCH 1/4] [clang] Add _mm512_kunpackd and _mm512_kunpackw to
avx512fi
https://github.com/ahmednoursphinx updated
https://github.com/llvm/llvm-project/pull/167683
>From e91be48deb3f895f88e9ab6a34ffd730e3fce47f Mon Sep 17 00:00:00 2001
From: ahmed
Date: Wed, 12 Nov 2025 13:01:46 +0200
Subject: [PATCH 1/7] [clang] Add _mm512_kunpackd and _mm512_kunpackw to
avx512fi
https://github.com/ahmednoursphinx updated
https://github.com/llvm/llvm-project/pull/167512
>From f26a73529db09f1bc6c423f930945de56656e6fd Mon Sep 17 00:00:00 2001
From: ahmed
Date: Tue, 11 Nov 2025 15:10:28 +0200
Subject: [PATCH 1/9] [X86] Add constexpr support for addsub and select
intrinsic
https://github.com/ahmednoursphinx updated
https://github.com/llvm/llvm-project/pull/167683
>From e91be48deb3f895f88e9ab6a34ffd730e3fce47f Mon Sep 17 00:00:00 2001
From: ahmed
Date: Wed, 12 Nov 2025 13:01:46 +0200
Subject: [PATCH 1/9] [clang] Add _mm512_kunpackd and _mm512_kunpackw to
avx512fi
ahmednoursphinx wrote:
Hey @RKSimon PR is ready for review again when you have some time
https://github.com/llvm/llvm-project/pull/167512
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https://github.com/ahmednoursphinx updated
https://github.com/llvm/llvm-project/pull/167683
>From e91be48deb3f895f88e9ab6a34ffd730e3fce47f Mon Sep 17 00:00:00 2001
From: ahmed
Date: Wed, 12 Nov 2025 13:01:46 +0200
Subject: [PATCH 1/9] [clang] Add _mm512_kunpackd and _mm512_kunpackw to
avx512fi
https://github.com/ahmednoursphinx updated
https://github.com/llvm/llvm-project/pull/167512
>From f26a73529db09f1bc6c423f930945de56656e6fd Mon Sep 17 00:00:00 2001
From: ahmed
Date: Tue, 11 Nov 2025 15:10:28 +0200
Subject: [PATCH 1/8] [X86] Add constexpr support for addsub and select
intrinsic
@@ -546,11 +568,51 @@ mlir::Value CIRGenFunction::emitX86BuiltinExpr(unsigned
builtinID,
case X86::BI__builtin_ia32_kshiftliqi:
case X86::BI__builtin_ia32_kshiftlihi:
case X86::BI__builtin_ia32_kshiftlisi:
- case X86::BI__builtin_ia32_kshiftlidi:
+ case X86::BI__builti
https://github.com/ahmednoursphinx updated
https://github.com/llvm/llvm-project/pull/167512
>From f26a73529db09f1bc6c423f930945de56656e6fd Mon Sep 17 00:00:00 2001
From: ahmed
Date: Tue, 11 Nov 2025 15:10:28 +0200
Subject: [PATCH 1/9] [X86] Add constexpr support for addsub and select
intrinsic
https://github.com/ahmednoursphinx edited
https://github.com/llvm/llvm-project/pull/168591
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https://github.com/ahmednoursphinx edited
https://github.com/llvm/llvm-project/pull/167512
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https://github.com/ahmednoursphinx commented:
Great work, left some nits regarding naming
https://github.com/llvm/llvm-project/pull/168591
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https://github.com/ahmednoursphinx updated
https://github.com/llvm/llvm-project/pull/167683
>From e91be48deb3f895f88e9ab6a34ffd730e3fce47f Mon Sep 17 00:00:00 2001
From: ahmed
Date: Wed, 12 Nov 2025 13:01:46 +0200
Subject: [PATCH 1/5] [clang] Add _mm512_kunpackd and _mm512_kunpackw to
avx512fi
@@ -546,11 +568,51 @@ mlir::Value CIRGenFunction::emitX86BuiltinExpr(unsigned
builtinID,
case X86::BI__builtin_ia32_kshiftliqi:
case X86::BI__builtin_ia32_kshiftlihi:
case X86::BI__builtin_ia32_kshiftlisi:
- case X86::BI__builtin_ia32_kshiftlidi:
+ case X86::BI__builti
@@ -68,6 +68,28 @@ static mlir::Value emitVectorFCmp(CIRGenBuilderTy &builder,
return bitCast;
}
+static mlir::Value getMaskVecValue(CIRGenFunction &cgf, const CallExpr *e,
+ mlir::Value mask, unsigned numElts) {
ahmednoursp
https://github.com/ahmednoursphinx updated
https://github.com/llvm/llvm-project/pull/167512
>From f26a73529db09f1bc6c423f930945de56656e6fd Mon Sep 17 00:00:00 2001
From: ahmed
Date: Tue, 11 Nov 2025 15:10:28 +0200
Subject: [PATCH 1/8] [X86] Add constexpr support for addsub and select
intrinsic
@@ -0,0 +1,211 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512f | FileCheck %s
--check-prefixes=AVX512,AVX512F
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512f,+avx51
ahmednoursphinx wrote:
Hey @RKSimon addressed your feedback please check when you have time
https://github.com/llvm/llvm-project/pull/166178
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https://github.com/ahmednoursphinx updated
https://github.com/llvm/llvm-project/pull/166178
>From 3cdf74e3eee0e206a3588acb1b4e53fd66eb9517 Mon Sep 17 00:00:00 2001
From: ahmed
Date: Mon, 3 Nov 2025 17:16:29 +0200
Subject: [PATCH 01/12] fix: rematerialize smaller predicate masks
---
llvm/lib/T
https://github.com/ahmednoursphinx updated
https://github.com/llvm/llvm-project/pull/167512
>From f26a73529db09f1bc6c423f930945de56656e6fd Mon Sep 17 00:00:00 2001
From: ahmed
Date: Tue, 11 Nov 2025 15:10:28 +0200
Subject: [PATCH 1/3] [X86] Add constexpr support for addsub and select
intrinsic
ahmednoursphinx wrote:
Hey @RKSimon , @phoebewang can you please merge this PR
https://github.com/llvm/llvm-project/pull/166178
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https://github.com/ahmednoursphinx created
https://github.com/llvm/llvm-project/pull/167512
Recent commits (7fe069121b57a, 53ddeb493529a) marked several x86 intrinsics as
constexpr in headers without providing the necessary constant evaluation
support in the compiler backend. This caused compi
https://github.com/ahmednoursphinx updated
https://github.com/llvm/llvm-project/pull/166178
>From 3cdf74e3eee0e206a3588acb1b4e53fd66eb9517 Mon Sep 17 00:00:00 2001
From: ahmed
Date: Mon, 3 Nov 2025 17:16:29 +0200
Subject: [PATCH 01/11] fix: rematerialize smaller predicate masks
---
llvm/lib/T
@@ -0,0 +1,159 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512f | FileCheck %s
--check-prefixes=AVX512,AVX512F
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512f,+avx51
https://github.com/ahmednoursphinx updated
https://github.com/llvm/llvm-project/pull/166178
>From 3cdf74e3eee0e206a3588acb1b4e53fd66eb9517 Mon Sep 17 00:00:00 2001
From: ahmed
Date: Mon, 3 Nov 2025 17:16:29 +0200
Subject: [PATCH 01/11] fix: rematerialize smaller predicate masks
---
llvm/lib/T
@@ -0,0 +1,159 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512f | FileCheck %s
--check-prefixes=AVX512,AVX512F
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512f,+avx51
ahmednoursphinx wrote:
Hey @RKSimon @phoebewang can you merge this please?
https://github.com/llvm/llvm-project/pull/166615
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@@ -1,13 +1,15 @@
// RUN: %clang_cc1 -verify -triple x86_64-unknown-unknown -emit-llvm-only %s
+// RUN: %clang_cc1 -verify -triple x86_64-unknown-unknown -emit-llvm-only
-fopenmp %s
ahmednoursphinx wrote:
thanks, updated
https://github.com/llvm/llvm-project/p
https://github.com/ahmednoursphinx updated
https://github.com/llvm/llvm-project/pull/166615
>From 684e005c76d7db5500fb0925547b58327c993d84 Mon Sep 17 00:00:00 2001
From: ahmed
Date: Wed, 5 Nov 2025 20:52:13 +0200
Subject: [PATCH 01/15] [SelectionDAG] Fix assertion failure on inline asm
registe
https://github.com/ahmednoursphinx updated
https://github.com/llvm/llvm-project/pull/166615
>From 684e005c76d7db5500fb0925547b58327c993d84 Mon Sep 17 00:00:00 2001
From: ahmed
Date: Wed, 5 Nov 2025 20:52:13 +0200
Subject: [PATCH 01/13] [SelectionDAG] Fix assertion failure on inline asm
registe
https://github.com/ahmednoursphinx updated
https://github.com/llvm/llvm-project/pull/166615
>From 684e005c76d7db5500fb0925547b58327c993d84 Mon Sep 17 00:00:00 2001
From: ahmed
Date: Wed, 5 Nov 2025 20:52:13 +0200
Subject: [PATCH 01/10] [SelectionDAG] Fix assertion failure on inline asm
registe
https://github.com/ahmednoursphinx updated
https://github.com/llvm/llvm-project/pull/166615
>From 684e005c76d7db5500fb0925547b58327c993d84 Mon Sep 17 00:00:00 2001
From: ahmed
Date: Wed, 5 Nov 2025 20:52:13 +0200
Subject: [PATCH 1/9] [SelectionDAG] Fix assertion failure on inline asm
register
https://github.com/ahmednoursphinx updated
https://github.com/llvm/llvm-project/pull/166615
>From 684e005c76d7db5500fb0925547b58327c993d84 Mon Sep 17 00:00:00 2001
From: ahmed
Date: Wed, 5 Nov 2025 20:52:13 +0200
Subject: [PATCH 1/8] [SelectionDAG] Fix assertion failure on inline asm
register
https://github.com/ahmednoursphinx updated
https://github.com/llvm/llvm-project/pull/166615
>From 684e005c76d7db5500fb0925547b58327c993d84 Mon Sep 17 00:00:00 2001
From: ahmed
Date: Wed, 5 Nov 2025 20:52:13 +0200
Subject: [PATCH 1/7] [SelectionDAG] Fix assertion failure on inline asm
register
ahmednoursphinx wrote:
Hey @arsenm i have updated the code based on @phoebewang recommendations ,
please have a look again when you have time
https://github.com/llvm/llvm-project/pull/166615
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h
ahmednoursphinx wrote:
> This is not what I expected. We should do the check as early as in the front
> end. I assume we just need to add back
>
> ```
> bool IsMMXCons = llvm::StringSwitch(Constraint)
> .Cases("y", "&y", "^Ym", true)
> .Default(false)
https://github.com/ahmednoursphinx updated
https://github.com/llvm/llvm-project/pull/166615
>From 684e005c76d7db5500fb0925547b58327c993d84 Mon Sep 17 00:00:00 2001
From: ahmed
Date: Wed, 5 Nov 2025 20:52:13 +0200
Subject: [PATCH 1/5] [SelectionDAG] Fix assertion failure on inline asm
register
https://github.com/ahmednoursphinx updated
https://github.com/llvm/llvm-project/pull/166615
>From 684e005c76d7db5500fb0925547b58327c993d84 Mon Sep 17 00:00:00 2001
From: ahmed
Date: Wed, 5 Nov 2025 20:52:13 +0200
Subject: [PATCH 1/4] [SelectionDAG] Fix assertion failure on inline asm
register
ahmednoursphinx wrote:
Hey @RKSimon please check again when you have time
https://github.com/llvm/llvm-project/pull/166178
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https://github.com/ahmednoursphinx updated
https://github.com/llvm/llvm-project/pull/166178
>From 3cdf74e3eee0e206a3588acb1b4e53fd66eb9517 Mon Sep 17 00:00:00 2001
From: ahmed
Date: Mon, 3 Nov 2025 17:16:29 +0200
Subject: [PATCH 01/10] fix: rematerialize smaller predicate masks
---
llvm/lib/T
https://github.com/ahmednoursphinx updated
https://github.com/llvm/llvm-project/pull/166178
>From 3cdf74e3eee0e206a3588acb1b4e53fd66eb9517 Mon Sep 17 00:00:00 2001
From: ahmed
Date: Mon, 3 Nov 2025 17:16:29 +0200
Subject: [PATCH 1/9] fix: rematerialize smaller predicate masks
---
llvm/lib/Tar
@@ -3173,6 +3179,23 @@ let Predicates = [HasAVX512] in {
def : Pat<(v1i1 immAllOnesV), (COPY_TO_REGCLASS (KSET1W), VK1)>;
}
+// With AVX512DQ, use 8-bit operations for 8-bit masks to avoid setting upper
+// bits
+let Predicates = [HasDQI] in {
+ def : Pat<(v8i1 immAllZeros
ahmednoursphinx wrote:
Hey @RKSimon tests have been updated please check when you have time
https://github.com/llvm/llvm-project/pull/166178
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https://github.com/ahmednoursphinx updated
https://github.com/llvm/llvm-project/pull/166178
>From 3cdf74e3eee0e206a3588acb1b4e53fd66eb9517 Mon Sep 17 00:00:00 2001
From: ahmed
Date: Mon, 3 Nov 2025 17:16:29 +0200
Subject: [PATCH 1/8] fix: rematerialize smaller predicate masks
---
llvm/lib/Tar
ahmednoursphinx wrote:
Hey @RKSimon @phoebewang PR is ready for review again when you have time
https://github.com/llvm/llvm-project/pull/166178
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ahmednoursphinx wrote:
> still missing v32i1 / v64i1 sub mask test coverage
Sorry missed that , added in latest commit
https://github.com/llvm/llvm-project/pull/166178
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https://github.com/ahmednoursphinx updated
https://github.com/llvm/llvm-project/pull/166178
>From 3cdf74e3eee0e206a3588acb1b4e53fd66eb9517 Mon Sep 17 00:00:00 2001
From: ahmed
Date: Mon, 3 Nov 2025 17:16:29 +0200
Subject: [PATCH 1/7] fix: rematerialize smaller predicate masks
---
llvm/lib/Tar
ahmednoursphinx wrote:
`v32i1`/`v64i1` types are only **legal** with `HasBWI`. The pseudo instructions
(lines 3157-3158) inherit `HasAVX512` from the multiclass, but the explicit
bitconvert patterns (lines 3194-3197) need `HasBWI` to prevent matching on
non-B
@@ -3173,6 +3179,23 @@ let Predicates = [HasAVX512] in {
def : Pat<(v1i1 immAllOnesV), (COPY_TO_REGCLASS (KSET1W), VK1)>;
}
+// With AVX512DQ, use 8-bit operations for 8-bit masks to avoid setting upper
+// bits
+let Predicates = [HasDQI] in {
+ def : Pat<(v8i1 immAllZeros
@@ -3173,6 +3179,26 @@ let Predicates = [HasAVX512] in {
def : Pat<(v1i1 immAllOnesV), (COPY_TO_REGCLASS (KSET1W), VK1)>;
}
+// With AVX512DQ, use 8-bit operations for 8-bit masks to avoid setting upper
+// bits
+let Predicates = [HasDQI] in {
+ def : Pat<(v8i1 immAllZeros
https://github.com/ahmednoursphinx updated
https://github.com/llvm/llvm-project/pull/166178
>From 3cdf74e3eee0e206a3588acb1b4e53fd66eb9517 Mon Sep 17 00:00:00 2001
From: ahmed
Date: Mon, 3 Nov 2025 17:16:29 +0200
Subject: [PATCH 1/6] fix: rematerialize smaller predicate masks
---
llvm/lib/Tar
@@ -362,7 +362,7 @@ let Predicates = [HasVSX, IsISAFuture] in {
"lxvprll $XTp, $addr, $RB", IIC_LdStLFD, []>;
def LXVPB32X
: XForm_XTp5_RAB5<31, 877, (outs vsrprc:$XTp),
- (ins (memr $RA):$addr, g8rc:$RB),
-
@@ -8445,9 +8445,10 @@ def aligned_alloc_unavailable : Flag<["-"],
"faligned-alloc-unavailable">,
MarshallingInfoFlag>,
ShouldParseIf;
-def finitial_counter_value_EQ : Joined<["-"], "finitial-counter-value=">,
- HelpText<"Sets the initial value for __COUNTER__, defaults
@@ -90,13 +90,13 @@ def err_unterminated___pragma : Error<"missing terminating
')' character">;
def err_conflict_marker : Error<"version control conflict marker in file">;
-def err_counter_overflow : Error<
- "'__COUNTER__' value cannot exceed 2'147'483'647">;
-def ext_coun
ahmednoursphinx wrote:
Formatting change as well
https://github.com/llvm/llvm-project/pull/166178
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ahmednoursphinx wrote:
This file was modified due to running formatter
https://github.com/llvm/llvm-project/pull/166178
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ahmednoursphinx wrote:
saa
https://github.com/llvm/llvm-project/pull/166178
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https://github.com/ahmednoursphinx updated
https://github.com/llvm/llvm-project/pull/166178
>From 3cdf74e3eee0e206a3588acb1b4e53fd66eb9517 Mon Sep 17 00:00:00 2001
From: ahmed
Date: Mon, 3 Nov 2025 17:16:29 +0200
Subject: [PATCH 1/4] fix: rematerialize smaller predicate masks
---
llvm/lib/Tar
https://github.com/ahmednoursphinx updated
https://github.com/llvm/llvm-project/pull/165513
>From eca52c0e1d9e79911f79d7339926e295fcbcf84f Mon Sep 17 00:00:00 2001
From: ahmed
Date: Tue, 28 Oct 2025 23:49:56 +0300
Subject: [PATCH 1/5] feat: VectorExprEvaluator::VisitCallExpr /
InterpretBuiltin
https://github.com/ahmednoursphinx updated
https://github.com/llvm/llvm-project/pull/165513
>From eca52c0e1d9e79911f79d7339926e295fcbcf84f Mon Sep 17 00:00:00 2001
From: ahmed
Date: Tue, 28 Oct 2025 23:49:56 +0300
Subject: [PATCH 1/5] feat: VectorExprEvaluator::VisitCallExpr /
InterpretBuiltin
ahmednoursphinx wrote:
Hey @RKSimon, Thanks for the feedback
PR is ready for review again when you have time
https://github.com/llvm/llvm-project/pull/165513
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https://github.com/ahmednoursphinx updated
https://github.com/llvm/llvm-project/pull/165513
>From eca52c0e1d9e79911f79d7339926e295fcbcf84f Mon Sep 17 00:00:00 2001
From: ahmed
Date: Tue, 28 Oct 2025 23:49:56 +0300
Subject: [PATCH 1/4] feat: VectorExprEvaluator::VisitCallExpr /
InterpretBuiltin
https://github.com/ahmednoursphinx updated
https://github.com/llvm/llvm-project/pull/165513
>From eca52c0e1d9e79911f79d7339926e295fcbcf84f Mon Sep 17 00:00:00 2001
From: ahmed
Date: Tue, 28 Oct 2025 23:49:56 +0300
Subject: [PATCH 1/4] feat: VectorExprEvaluator::VisitCallExpr /
InterpretBuiltin
https://github.com/ahmednoursphinx updated
https://github.com/llvm/llvm-project/pull/165513
>From eca52c0e1d9e79911f79d7339926e295fcbcf84f Mon Sep 17 00:00:00 2001
From: ahmed
Date: Tue, 28 Oct 2025 23:49:56 +0300
Subject: [PATCH 1/4] feat: VectorExprEvaluator::VisitCallExpr /
InterpretBuiltin
https://github.com/ahmednoursphinx updated
https://github.com/llvm/llvm-project/pull/165513
>From eca52c0e1d9e79911f79d7339926e295fcbcf84f Mon Sep 17 00:00:00 2001
From: ahmed
Date: Tue, 28 Oct 2025 23:49:56 +0300
Subject: [PATCH 1/3] feat: VectorExprEvaluator::VisitCallExpr /
InterpretBuiltin
https://github.com/ahmednoursphinx updated
https://github.com/llvm/llvm-project/pull/165513
>From eca52c0e1d9e79911f79d7339926e295fcbcf84f Mon Sep 17 00:00:00 2001
From: ahmed
Date: Tue, 28 Oct 2025 23:49:56 +0300
Subject: [PATCH 1/2] feat: VectorExprEvaluator::VisitCallExpr /
InterpretBuiltin
https://github.com/ahmednoursphinx updated
https://github.com/llvm/llvm-project/pull/165513
>From eca52c0e1d9e79911f79d7339926e295fcbcf84f Mon Sep 17 00:00:00 2001
From: ahmed
Date: Tue, 28 Oct 2025 23:49:56 +0300
Subject: [PATCH] feat: VectorExprEvaluator::VisitCallExpr / InterpretBuiltin -
A
https://github.com/ahmednoursphinx created
https://github.com/llvm/llvm-project/pull/165513
This PR Resolves https://github.com/llvm/llvm-project/issues/165161
>From eca52c0e1d9e79911f79d7339926e295fcbcf84f Mon Sep 17 00:00:00 2001
From: ahmed
Date: Tue, 28 Oct 2025 23:49:56 +0300
Subject: [PA
ahmednour25689 wrote:
@RKSimon this is ready for review again when you have time
https://github.com/llvm/llvm-project/pull/162301
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ahmednour25689 wrote:
Hey @RKSimon i have addressed your feedback please review when you have some
time
https://github.com/llvm/llvm-project/pull/162301
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ahmednour25689 wrote:
@RKSimon the PR is ready for review again and all feedback addressed
please have a look when you have time
https://github.com/llvm/llvm-project/pull/162301
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