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https://github.com/llvm/llvm-project/pull/127152
apple-a18 is an alias of apple-m4.
apple-s6/s7/s8 are aliases of apple-a13.
apple-s9/s10 are aliases of apple-a16.
As with some other aliases today, this reflects identical ISA feature support,
but not ne
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ahmedbougacha wrote:
#106599 release/19.x: [AArch64] Make apple-m4 armv8.7-a again (from armv9.2-a).
https://github.com/llvm/llvm-project/pull/106312
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ahmedbougacha wrote:
/cherry-pick e5e38ddf1b8043324175868831da21e941c00aff
https://github.com/llvm/llvm-project/pull/106312
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>From c9b283760399f46cc4cb4a728069fb8c33e00e5f Mon Sep 17 00:00:00 2001
From: Ahmed Bougacha
Date: Tue, 27 Aug 2024 16:48:35 -0700
Subject: [PATCH 1/2] [AArch64] Add incorrect target(cpu=apple-m4) fn attr
ahmedbougacha wrote:
In the meantime, let's do #106312
https://github.com/llvm/llvm-project/pull/106304
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https://github.com/llvm/llvm-project/pull/106312
This is a partial revert of c66e1d6f3429. Even though that
allowed us to declare v9.2-a support without picking up SVE2
in both the backend and the driver, the frontend itself still
enabled SVE via the arc
https://github.com/ahmedbougacha created
https://github.com/llvm/llvm-project/pull/106304
In the tablegen definitions, we have now split the lists of extensions enabled
by default for an arch version from the features that are required.
However, the frontend (in `AArch64TargetInfo::setFeatureE
ahmedbougacha wrote:
> > * Calling a function marked interrupt from a function marked interrupt is
> > still UB isn't it? Should there be another warning to cover that scenario
> > as well?
>
> Correct. I can create a separate issue to describe such a warning. Calling an
> interrupt handler f
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https://github.com/llvm/llvm-project/pull/104435
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@@ -892,7 +905,7 @@ def ProcessorFeatures {
FeatureComplxNum, FeatureCRC, FeatureJS,
FeatureLSE, FeaturePAuth, FeatureFPAC,
FeatureRAS, FeatureRCPC, FeatureRDM,
-
@@ -845,7 +857,8 @@ def ProcessorFeatures {
list AppleA12 = [HasV8_3aOps, FeatureSHA2, FeatureAES,
FeatureFPARMv8,
FeatureNEON, FeaturePerfMon,
FeatureFullFP16,
FeatureComplxNum, FeatureCRC, FeatureJS
https://github.com/ahmedbougacha commented:
A couple small issues inline, LGTM otherwise, thanks!
>> FEAT_SSBS is not mandatory for any architecture.
>
> https://reviews.llvm.org/D54629 says it is mandatory for 8.5-a but I can't
> see that in the Arm ARM.
It was indeed originally mandatory (se
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>From 241ecf478c0cc0e929ffef3532cc2cb625781a71 Mon Sep 17 00:00:00 2001
From: Ahmed Bougacha
Date: Fri, 9 Aug 2024 12:26:20 -0700
Subject: [PATCH] [clang] Enable pointer authentication auth-failure traps.
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ahmedbougacha wrote:
> @ahmedbougacha Non-blocking nit: you might want to add a test in
> clang/test/CodeGen/ptrauth-function-attributes.c (like you have for auth
> traps in https://github.com/llvm/llvm-project/pull/102417)
Oh yeah that's certainly required; I think I dropped it accidentally
https://github.com/ahmedbougacha updated
https://github.com/llvm/llvm-project/pull/102416
>From 41061b347b7d0fa862f65896d4fc155cb0b791ba Mon Sep 17 00:00:00 2001
From: Ahmed Bougacha
Date: Fri, 24 May 2024 20:24:26 -0700
Subject: [PATCH 1/3] [clang] Wire -fptrauth-returns to "ptrauth-returns" f
https://github.com/ahmedbougacha updated
https://github.com/llvm/llvm-project/pull/102416
>From 41061b347b7d0fa862f65896d4fc155cb0b791ba Mon Sep 17 00:00:00 2001
From: Ahmed Bougacha
Date: Fri, 24 May 2024 20:24:26 -0700
Subject: [PATCH 1/2] [clang] Wire -fptrauth-returns to "ptrauth-returns" f
https://github.com/ahmedbougacha ready_for_review
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https://github.com/ahmedbougacha created
https://github.com/llvm/llvm-project/pull/102417
This provides -fptrauth-auth-traps, which at the frontend level only controls
the addition of the "ptrauth-auth-traps" function attribute. The attribute in
turn controls various aspects of backend codege
https://github.com/ahmedbougacha created
https://github.com/llvm/llvm-project/pull/102416
We already ended up with -fptrauth-returns, the feature macro, the lang opt,
and the actual backend lowering.
The only part left is threading it all through PointerAuthOptions, to drive the
addition of t
@@ -1056,12 +1056,18 @@ class ConstantPtrAuth final : public Constant {
return !getAddrDiscriminator()->isNullValue();
}
- /// A constant value for the address discriminator which has special
- /// significance to ctors/dtors lowering. Regular address discrimination
c
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https://github.com/llvm/llvm-project/pull/99726
>From f46421f8e0349f65f07ab3bd822e179bf983439f Mon Sep 17 00:00:00 2001
From: Ahmed Bougacha
Date: Wed, 17 Jul 2024 16:18:41 -0700
Subject: [PATCH 1/2] [clang] Implement type/address discrimination of
type
https://github.com/ahmedbougacha updated
https://github.com/llvm/llvm-project/pull/97647
>From 519570896c82887a5dd878fcc16f884857d4fce3 Mon Sep 17 00:00:00 2001
From: Ahmed Bougacha
Date: Tue, 12 Mar 2024 14:40:17 -0700
Subject: [PATCH 1/5] [AArch64][PAC] Sign block addresses used in indirectbr
@@ -1789,6 +1789,9 @@ void Clang::AddAArch64TargetArgs(const ArgList &Args,
options::OPT_fno_ptrauth_vtable_pointer_type_discrimination);
Args.addOptInFlag(CmdArgs, options::OPT_fptrauth_init_fini,
options::OPT_fno_ptrauth_init_fini);
+
-
@@ -412,6 +412,15 @@ class AArch64Subtarget final : public
AArch64GenSubtargetInfo {
/// Choose a method of checking LR before performing a tail call.
AArch64PAuth::AuthCheckMethod getAuthenticatedLRCheckMethod() const;
+ /// Compute the integer discriminator for a given
@@ -10685,6 +10689,26 @@ SDValue AArch64TargetLowering::LowerBR_JT(SDValue Op,
return DAG.getNode(ISD::BRIND, DL, MVT::Other, JTInfo, SDValue(Dest, 0));
}
+SDValue AArch64TargetLowering::LowerBRIND(SDValue Op, SelectionDAG &DAG) const
{
+ MachineFunction &MF = DAG.getMachi
@@ -0,0 +1,106 @@
+; RUN: llc -mtriple arm64e-apple-darwin \
ahmedbougacha wrote:
It's not too bad; switched
https://github.com/llvm/llvm-project/pull/97647
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>From 519570896c82887a5dd878fcc16f884857d4fce3 Mon Sep 17 00:00:00 2001
From: Ahmed Bougacha
Date: Tue, 12 Mar 2024 14:40:17 -0700
Subject: [PATCH 1/3] [AArch64][PAC] Sign block addresses used in indirectbr
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https://github.com/llvm/llvm-project/pull/99726
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https://github.com/llvm/llvm-project/pull/99726
We want to be able to support full type and address discrimination of type_info
on targets that don't have existing ABI compatibility constraints.
This patch does not enable such behavior on any platform,
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ahmedbougacha wrote:
> The difference should be not be signed IMO as stated above.
We discussed this in the sync-up, but for the record I don't think we can get
away with not signing and nothing else. It defeats the purpose of signing
these in the first place: an arbitrary write becomes a br
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ahmedbougacha wrote:
> Please make sure you have a testcase for computing the difference between two
> blockaddresses (void g(int*); int f() { static int x = &&A-&&B;
> A:g(&x);B:return x; }). Not sure how you should handle that case.
Oh yeah, we can't handle that at all, I don't think! The b
https://github.com/ahmedbougacha updated
https://github.com/llvm/llvm-project/pull/97647
>From 519570896c82887a5dd878fcc16f884857d4fce3 Mon Sep 17 00:00:00 2001
From: Ahmed Bougacha
Date: Tue, 12 Mar 2024 14:40:17 -0700
Subject: [PATCH] [AArch64][PAC] Sign block addresses used in indirectbr.
E
https://github.com/ahmedbougacha created
https://github.com/llvm/llvm-project/pull/97647
Enabled in clang using:
-fptrauth-indirect-gotos
and at the IR level using function attribute:
"ptrauth-indirect-gotos"
Signing uses IA and a per-function integer discriminator. The discriminator
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ahmedbougacha wrote:
>> Do we want a lot of -fptrauth-xxx instead of -fptrauth-something=xxx,yyy,zzz?
>
> I would lean towards a single flag.
Comma-separated flags generally seem less user-friendly (for, e.g., grepping,
modifying, reading). To some extent we can mitigate that with the obvious
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https://github.com/llvm/llvm-project/pull/93906
>From 016baec5833f0fba4280e67ba24caed48e8a1017 Mon Sep 17 00:00:00 2001
From: Akira Hatanaka
Date: Fri, 24 May 2024 20:23:36 -0700
Subject: [PATCH 1/6] [clang] Implement function pointer signing.
Co-Author
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>From 2767407e2970d6fb8b0e651d80162d9481129258 Mon Sep 17 00:00:00 2001
From: Ahmed Bougacha
Date: Thu, 30 May 2024 17:33:04 -0700
Subject: [PATCH 1/6] [clang] Define ptrauth_sign_constant builtin.
This is
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@@ -328,6 +328,21 @@ be done in a single instruction with an immediate integer.
``pointer`` must have pointer type, and ``integer`` must have integer type. The
result has type ``ptrauth_extra_data_t``.
+``ptrauth_string_discriminator``
+
+
+.. c
https://github.com/ahmedbougacha updated
https://github.com/llvm/llvm-project/pull/93903
>From 607592e7071a604fc63252cb3686545ed1f1b0b8 Mon Sep 17 00:00:00 2001
From: Ahmed Bougacha
Date: Thu, 30 May 2024 17:22:29 -0700
Subject: [PATCH 1/6] [clang] Define ptrauth_string_discriminator builtin.
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https://github.com/llvm/llvm-project/pull/93903
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@@ -983,50 +1007,58 @@ def : ProcessorModel<"thunderx3t110", ThunderX3T110Model,
def : ProcessorModel<"tsv110", TSV110Model, ProcessorFeatures.TSV110,
[TuneTSV110]>;
+// iPhone, iPad, Mac and Watch CPUs
ahmedbougacha wrote:
Certainly mino
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https://github.com/llvm/llvm-project/pull/95579
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@@ -718,12 +718,16 @@ def ProcessorFeatures {
list AppleA13 = [HasV8_4aOps, FeatureCrypto,
FeatureFPARMv8,
FeatureNEON, FeaturePerfMon,
FeatureFullFP16,
FeatureFP16FML, FeatureSHA3];
+ // Apple A14 a
ahmedbougacha wrote:
> The overall idea is that system registers ought be available everywhere
> without the need to explicitly enable them with a command line option.
Interesting, that's kind of what I'm getting at: longer term, are you saying
you folks are considering removing the feature pr
ahmedbougacha wrote:
> > Correct, apple-m1 does not have BTI, but BTI is required for v8.5. My
> > mistake.
>
> Not sure if you are involved in writing the optimization guide itself at
> Apple, but the way the chip is described as having 8.5 minus BTI is a bit
> confusing since that would tec
@@ -718,12 +718,16 @@ def ProcessorFeatures {
list AppleA13 = [HasV8_4aOps, FeatureCrypto,
FeatureFPARMv8,
FeatureNEON, FeaturePerfMon,
FeatureFullFP16,
FeatureFP16FML, FeatureSHA3];
+ // Apple A14 a
https://github.com/ahmedbougacha updated
https://github.com/llvm/llvm-project/pull/93902
>From fc8f76b404b25951dc10ecaaa760b4b4c3d4f858 Mon Sep 17 00:00:00 2001
From: Ahmed Bougacha
Date: Thu, 30 May 2024 17:07:04 -0700
Subject: [PATCH 1/2] [clang] Add arm64e ABI-defined key assignments to
ptr
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@@ -15,6 +15,29 @@ typedef enum {
ptrauth_key_asib = 1,
ptrauth_key_asda = 2,
ptrauth_key_asdb = 3,
+
+#ifdef __APPLE__
ahmedbougacha wrote:
Great, let's do that; I also removed the comments that talk about enablement
policy, that seems like a separate
https://github.com/ahmedbougacha updated
https://github.com/llvm/llvm-project/pull/93901
>From fc8f76b404b25951dc10ecaaa760b4b4c3d4f858 Mon Sep 17 00:00:00 2001
From: Ahmed Bougacha
Date: Thu, 30 May 2024 17:07:04 -0700
Subject: [PATCH 1/2] [clang] Add arm64e ABI-defined key assignments to
ptr
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https://github.com/llvm/llvm-project/pull/93901
These are currently gated by __APPLE__; we can figure out a way to define these
on ELF targets as well, and maybe have them be defined by clang itself,
depending on ABI modes.
>From fc8f76b404b25951dc10ec
ahmedbougacha wrote:
> This patch removes FEAT_FPMR from list of available of architecture features,
> instead enabling FMPR register by default.
Can you expand a little bit on the reasoning? It doesn't seem all that
problematic but is still eyebrow-raising.
https://github.com/llvm/llvm-proj
@@ -718,12 +718,16 @@ def ProcessorFeatures {
list AppleA13 = [HasV8_4aOps, FeatureCrypto,
FeatureFPARMv8,
FeatureNEON, FeaturePerfMon,
FeatureFullFP16,
FeatureFP16FML, FeatureSHA3];
+ // Apple A14 a
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@@ -2085,6 +2099,37 @@ void
AArch64AsmPrinter::emitMachOIFuncStubHelperBody(Module &M,
.addImm(2),
*STI);
+ if (TM.getTargetTriple().isArm64e()) {
+// autibsp
ahmedbougacha wrote:
There
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https://github.com/llvm/llvm-project/pull/65996
>From 1492d6362a1a4f6d65fb7001bdefb5250f30754e Mon Sep 17 00:00:00 2001
From: Ahmed Bougacha
Date: Wed, 16 Aug 2023 09:17:12 -0700
Subject: [PATCH] [AArch64][PAC] Support and document ptrauth builtins and
@@ -2085,6 +2099,37 @@ void
AArch64AsmPrinter::emitMachOIFuncStubHelperBody(Module &M,
.addImm(2),
*STI);
+ if (TM.getTargetTriple().isArm64e()) {
+// autibsp
ahmedbougacha wrote:
Leave
ahmedbougacha wrote:
Updated, tried to address all the comments; let me know if I missed something!
https://github.com/llvm/llvm-project/pull/65996
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@@ -0,0 +1,265 @@
+Pointer Authentication
+==
+
+.. contents::
+ :local:
+
+Introduction
+
+
+Pointer authentication is a technology which offers strong probabilistic
protection against exploiting a broad class of memory bugs to take control of
@@ -0,0 +1,265 @@
+Pointer Authentication
+==
+
+.. contents::
+ :local:
+
+Introduction
+
+
+Pointer authentication is a technology which offers strong probabilistic
protection against exploiting a broad class of memory bugs to take control of
@@ -0,0 +1,265 @@
+Pointer Authentication
+==
+
+.. contents::
+ :local:
+
+Introduction
+
+
+Pointer authentication is a technology which offers strong probabilistic
protection against exploiting a broad class of memory bugs to take control of
https://github.com/ahmedbougacha updated
https://github.com/llvm/llvm-project/pull/65996
>From c5cde09a5ea4a4cfcf3287f7462c38335493c02d Mon Sep 17 00:00:00 2001
From: Ahmed Bougacha
Date: Wed, 16 Aug 2023 09:17:12 -0700
Subject: [PATCH] [AArch64][PAC] Support and document ptrauth builtins and
https://github.com/ahmedbougacha updated
https://github.com/llvm/llvm-project/pull/65996
>From c4e7c86eb967b4313e19587e33fdc6b50c8cd6a7 Mon Sep 17 00:00:00 2001
From: Ahmed Bougacha
Date: Wed, 16 Aug 2023 09:17:12 -0700
Subject: [PATCH] [AArch64][PAC] Support and document ptrauth builtins and
https://github.com/ahmedbougacha approved this pull request.
Neat, ty!
https://github.com/llvm/llvm-project/pull/73686
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@@ -2169,8 +2169,11 @@ void AsmPrinter::emitGlobalIFunc(Module &M, const
GlobalIFunc &GI) {
MCSymbol *LocalAlias = getSymbolPreferLocal(GI);
if (LocalAlias != Name)
OutStreamer->emitAssignment(LocalAlias, Expr);
- } else if (TM.getTargetTriple().isOSBinFormatMac
@@ -2147,24 +2148,80 @@ void AsmPrinter::emitGlobalIFunc(Module &M, const
GlobalIFunc &GI) {
assert(!TM.getTargetTriple().isOSBinFormatXCOFF() &&
"IFunc is not supported on AIX.");
- MCSymbol *Name = getSymbol(&GI);
+ auto EmitLinkage = [&](MCSymbol *Sym) {
+
@@ -599,6 +599,26 @@ class AsmPrinter : public MachineFunctionPass {
/// instructions in verbose mode.
virtual void emitImplicitDef(const MachineInstr *MI) const;
+ /// getSubtargetInfo() cannot be used where this is needed because we don't
+ /// have a MachineFunction w
https://github.com/ahmedbougacha edited
https://github.com/llvm/llvm-project/pull/73686
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https://github.com/ahmedbougacha commented:
Only a couple minor comments, LG otherwise, thanks! The Subtarget weirdness is
unfortunate but I can't say I have a better alternative
https://github.com/llvm/llvm-project/pull/73686
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https://github.com/ahmedbougacha edited
https://github.com/llvm/llvm-project/pull/73686
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@@ -1809,6 +1814,255 @@ void AArch64AsmPrinter::emitInstruction(const
MachineInstr *MI) {
EmitToStreamer(*OutStreamer, TmpInst);
}
+void AArch64AsmPrinter::emitGlobalIFunc(Module &M, const GlobalIFunc &GI) {
+ if (!TM.getTargetTriple().isOSBinFormatMachO())
+return Asm
@@ -144,7 +144,12 @@ bool CallLowering::lowerCall(MachineIRBuilder &MIRBuilder,
const CallBase &CB,
// Try looking through a bitcast from one function type to another.
// Commonly happens with calls to objc_msgSend().
const Value *CalleeV = CB.getCalledOperand()->stripPo
@@ -882,8 +882,11 @@ class AsmPrinter : public MachineFunctionPass {
GCMetadataPrinter *getOrCreateGCPrinter(GCStrategy &S);
void emitGlobalAlias(Module &M, const GlobalAlias &GA);
- void emitGlobalIFunc(Module &M, const GlobalIFunc &GI);
+protected:
+ virtual void emi
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