target variable expansion with included make files

first makefile not to use the variables defined in the second makefile in its target names. This causes the targets defined in the first makefile to always run the associated rules on every evocation of make. Is this proper behavior? Is there a better approach? Thanks Brad Kemp =Mak

Re: target variable expansion with included make files

>-- Original Message -- >To: [EMAIL PROTECTED] >From: Boris Kolpackov <[EMAIL PROTECTED]> >Date: Thu, 5 Aug 2004 14:49:06 + (UTC) >Subject: Re: target variable expansion with included make files > > >"Brad Kemp" <[EMAIL PROTECTED]> writes: >