Yup, that's why the eq macro one is better:
make -f and.mk A=22 B=44
> Crude AND Demo:
> TRUE: A is 2, B is 4
> Macro-based AND Demo:
> FALSE: A is 22, B is 44
>
The crude one fails because as you noticed, it considers 2, 22 and 222 to
all be the same.
That's why the macro also reverses the sub
Try make -f and.mk A=22 B=44.
From: [EMAIL PROTECTED]
[mailto:[EMAIL PROTECTED] On Behalf Of Tim
Murphy
Sent: Tuesday, June 17, 2008 09:31
To: bug-make@gnu.org
Subject: Re: Help : how to use $(or condition ) & $(and condition )
inmakefile
Hi,
I have amended an
Hi,
I have amended an example of how to use $(and) that I posted earlier for
Rakesh. I have tested this on Linux with make 3.81.
It shows a crude way and a slightly more sophisticated way to use $(and) in
an if statement to determine if two variables have equal values:
A=2
> B=4
>
> # do "equal
On Tue, Jun 17, 2008 at 04:00:22PM +0530, A, Sravanthi wrote:
> Team,
>
> Can any one of you help to resolve this issue.
> My file structure will have root make file which will call makefiles in
> each subfolder. Some of the CC files which are dependant on other folder
> object files are getting
On Tue, 2008-06-17 at 16:00 +0530, A, Sravanthi wrote:
> 3. b.o is dependant on a.o
>
> If any changes are done to a.cc file, b.o should get rebuilt.
This is an extremely unusual situation. In what way is b.o depending on
a.cc or a.o? Generally, .o files depend on the single .c or .cc or
whate
Team,
Can any one of you help to resolve this issue.
My file structure will have root make file which will call makefiles in
each subfolder. Some of the CC files which are dependant on other folder
object files are getting recompiled.
For example
1. Folder d1 will have a.o which is compiled fro
