[PATCH v2 hurd] rumpnet: Add device translator for (Intel) NICs

2025-07-19 Thread Damien Zammit
This adds a working rump driver for /dev/wmX cards, which are Intel i8254x Gigabit Ethernet devices. (See man.netbsd.org for "wm(4)") This should be easily extended to support other NICs by contributing some makefile foo to netbsd/rump. TESTED: - On UP+apic it works 100% with hurd-i386. - On S

Re: [PATCH v2 gnumach] interrupt.S: Change interrupt EOI strategy

2025-07-19 Thread Samuel Thibault
Samuel Thibault, le ven. 18 juil. 2025 21:53:29 +0200, a ecrit: > > TODO: We still need to work out a strategy to have interrupts enabled > > during the handler, so that nested interrupts that occur via code that > > is executed inside the irq handler to make the device raise a new > > interrupt, a

Re: [PATCH v3 1/2 gnumach] ioapic: Introduce irqinfo helper struct

2025-07-19 Thread Samuel Thibault
Applied, thanks! Damien Zammit, le sam. 19 juil. 2025 06:41:44 +, a ecrit: > Avoid reading the ioapic registers for vector and trigger mode, > by introducing an O(1) memory lookup for these properties. > --- > i386/i386/apic.h | 6 ++ > i386/i386/pic.c | 5 + > i386/i386/pi

[PATCH v3 2/2 gnumach] interrupt.S: Change interrupt EOI strategy

2025-07-19 Thread Damien Zammit
We now have a different strategy for EOI depending on trigger mode: For edge triggered, the behaviour is unchanged; the eoi comes before the handler so we don't miss interrupts. For level triggered, the eoi comes after the handler since a high interrupt line doesn't keep triggering until it has bee

[PATCH v3 0/2 gnumach] irq end of interrupt strategy

2025-07-19 Thread Damien Zammit
I think we want level triggered interrupts to be handled before EOI because we may want to set IF during the service routine to capture nested ones and I'm not sure if the current handling of level triggered interrupts will allow that (?) I have split this patch in half so that the irqinfo struct

[PATCH v3 1/2 gnumach] ioapic: Introduce irqinfo helper struct

2025-07-19 Thread Damien Zammit
Avoid reading the ioapic registers for vector and trigger mode, by introducing an O(1) memory lookup for these properties. --- i386/i386/apic.h | 6 ++ i386/i386/pic.c | 5 + i386/i386/pic.h | 6 ++ i386/i386at/ioapic.c | 27 +-- 4 files changed