On Sun, Dec 22, 2024 at 6:11 AM Diego Nieto Cid wrote:
> I just didn't understand the hard/soft limits. It's better described
> by the structure members and not the comments:
>
> struct rlimit {
> rlim_t rlim_cur; /* Soft limit */
> rlim_t rlim_max; /* Hard limit (ceiling for
Hi,
On Sun, Dec 22, 2024 at 02:35:08AM +0100, Samuel Thibault wrote:
>
> What do you refer to by hard/soft?
>
I just didn't understand the hard/soft limits. It's better described
by the structure members and not the comments:
struct rlimit {
rlim_t rlim_cur; /* Soft limit */
Applied, thanks!
Damien Zammit via Bug reports for the GNU Hurd, le dim. 22 déc. 2024 01:43:44
+, a ecrit:
> Add workaround for broken systems that advertise 8 bit APIC ids
> but only match IPIs on 4 bits of the APIC id.
> ---
> i386/i386/apic.c | 28 +++-
Applied, thanks!
Damien Zammit via Bug reports for the GNU Hurd, le dim. 22 déc. 2024 01:43:36
+, a ecrit:
> Fixes ESR==0x8 error on AMD fam15h. Fixed timings.
>
> Cannot locate documentation on correct mode for STARTUP IPI,
> but this patch works on AMD hw and qemu.
> ---
> i386/i386/smp.c
Applied, thanks!
Damien Zammit via Bug reports for the GNU Hurd, le dim. 22 déc. 2024 01:43:28
+, a ecrit:
> Now that things are in place, we switch to parallel init.
> The key to this change is that the INIT/STARTUP sequence
> is done in one step, and all cpus wake up at the same time.
> Syn
Hi,
I addressed the comments in v3. This is v4.
I was unable to locate documentation for correct STARTUP IPI mode,
but I tested this series on both AMD fam15h and qemu and it boots.
Damien
Now that things are in place, we switch to parallel init.
The key to this change is that the INIT/STARTUP sequence
is done in one step, and all cpus wake up at the same time.
Synchronisation is done via waiting for individual flags stored
in separate memory locations.
---
i386/i386/apic.h| 4
Add workaround for broken systems that advertise 8 bit APIC ids
but only match IPIs on 4 bits of the APIC id.
---
i386/i386/apic.c | 28 +++-
i386/i386/apic.h | 15 ++-
i386/i386/cpu_number.h| 3 +++
i386/i386/cpuboot.S
Fixes ESR==0x8 error on AMD fam15h. Fixed timings.
Cannot locate documentation on correct mode for STARTUP IPI,
but this patch works on AMD hw and qemu.
---
i386/i386/smp.c | 62 +++--
1 file changed, 40 insertions(+), 22 deletions(-)
diff --git a/i386
Zhaoming Luo, le sam. 21 déc. 2024 12:34:58 +0800, a ecrit:
> On 12/19/24 6:31 PM, Samuel Thibault wrote:
> > Zhaoming Luo, le jeu. 19 déc. 2024 09:23:57 +0800, a ecrit:
> > > On 12/19/24 4:18 AM, Luca wrote:
> > > To be honest I came across /dev/time several times but I'm still quite
> > > confuse
Hello,
Diego Nieto Cid, le mar. 17 déc. 2024 23:02:01 -0300, a ecrit:
> El mar, 17 dic 2024 a las 22:21, Zhaoming Luo () escribió:
> >
> > The precision of this implmentation is 10ms. Not sure how to do with the
> > possible data race.
> >
> > Signed-off-by: Zhaoming Luo
> > ---
> > include/mach
Hello,
Diego Nieto Cid, le jeu. 19 déc. 2024 12:47:50 -0300, a ecrit:
> After playing a bit with the setrlimit calls in Linux to see how the
> resource RLIMIT_AS actually works, it seems to be limiting the amount
> of virtual memory available to the process (and not the available
> virtual address
Damien Zammit via Bug reports for the GNU Hurd, le dim. 22 déc. 2024 00:48:12
+, a ecrit:
> On 12/22/24 11:35 AM, Samuel Thibault wrote:
> > This is quite verbose. Could you check that the attached patch on top of
> > it still works?
> >
> > Samuel
>
> Your patch works and is much more readab
Diego Nieto Cid, le sam. 21 déc. 2024 21:27:55 -0300, a ecrit:
> On Sun, Dec 22, 2024 at 12:32:19AM +0100, Samuel Thibault wrote:
> > Samuel Thibault, le dim. 22 déc. 2024 00:31:11 +0100, a ecrit:
> >
> > Note however https://github.com/jackaudio/jack2/pull/993
>
> Oh, great :) Thanks for working
Does deassert work for other models / qemu / etc. Perhaps we have a
reference for this? This code seems to be receiving back&forth changes,
better make sure we are going the right way.
Samuel
Damien Zammit via Bug reports for the GNU Hurd, le sam. 21 déc. 2024 23:55:32
+, a ecrit:
> Fixes ES
On 12/22/24 11:35 AM, Samuel Thibault wrote:
> This is quite verbose. Could you check that the attached patch on top of
> it still works?
>
> Samuel
Your patch works and is much more readable.
Thanks, Damien
Hello,
Damien Zammit via Bug reports for the GNU Hurd, le sam. 21 déc. 2024 23:55:25
+, a ecrit:
> @@ -341,12 +312,16 @@ start_other_cpus(void)
> lapic_disable();
>
> bspdone = 0;
> +
> + /* This is set once for all APs to use */
> + pmap_make_temporary_mapping();
> +
>
Hello,
Damien Zammit via Bug reports for the GNU Hurd, le sam. 21 déc. 2024 23:55:17
+, a ecrit:
> + movl%eax, %ebx
> +
> + /* Make eax hold offset to my cpus gdt */
> + movl$((GDT_DESCR_M32 + GDT_TABLE_M32) * 4), %eax
> + mul %ebp
> +
> + /* Patch only our own
On Sun, Dec 22, 2024 at 12:32:19AM +0100, Samuel Thibault wrote:
> Samuel Thibault, le dim. 22 déc. 2024 00:31:11 +0100, a ecrit:
>
> Note however https://github.com/jackaudio/jack2/pull/993
>
Oh, great :) Thanks for working on it!
Do you need help with anything else? Or is it just a matter
of ti
This allocates a constant space for percpu gdts
and copies the first entry to the nth entry on each cpu,
then patches its own copy of the gdt so it can function
independently.
---
i386/i386/cpuboot.S | 63 ++---
1 file changed, 53 insertions(+), 10 deletions
Add workaround for broken systems that advertise 8 bit APIC ids
but only match IPIs on 4 bits of the APIC id.
---
i386/i386/apic.c | 28 +++-
i386/i386/apic.h | 15 ++-
i386/i386/cpu_number.h| 3 +++
i386/i386/cpuboot.S
Hi,
The first two patches are exactly v2, but I have added two more
that make SMP functional on my AMD fam15h processor.
Thanks,
Damien
Fixes ESR==0x8 error on AMD fam15h. Fixed timings.
---
i386/i386/smp.c | 62 +++--
1 file changed, 40 insertions(+), 22 deletions(-)
diff --git a/i386/i386/smp.c b/i386/i386/smp.c
index befa0510..e3e4cc82 100644
--- a/i386/i386/smp.c
+++ b/i386/i386/smp
Now that things are in place, we switch to parallel init.
The key to this change is that the INIT/STARTUP sequence
is done in one step, and all cpus wake up at the same time.
Synchronisation is done to complete each cpu setup individually.
---
i386/i386/mp_desc.c | 51 +++--
Samuel Thibault, le dim. 22 déc. 2024 00:31:11 +0100, a ecrit:
> Diego Nieto Cid, le sam. 21 déc. 2024 20:01:00 -0300, a ecrit:
> > On Sat, Aug 03, 2024 at 12:23:07AM +0200, Samuel Thibault wrote:
> > >
> > > I also notice that jackd2 is failing for some time (on hurd-i386 too),
> > > we'll need i
Diego Nieto Cid, le sam. 21 déc. 2024 20:01:00 -0300, a ecrit:
> On Sat, Aug 03, 2024 at 12:23:07AM +0200, Samuel Thibault wrote:
> >
> > I also notice that jackd2 is failing for some time (on hurd-i386 too),
> > we'll need it quite badly, any taker?
> >
>
> After hardcoding a PATH_MAX to see wh
Hi,
On Sat, Aug 03, 2024 at 12:23:07AM +0200, Samuel Thibault wrote:
>
> I also notice that jackd2 is failing for some time (on hurd-i386 too),
> we'll need it quite badly, any taker?
>
After hardcoding a PATH_MAX to see where it takes us, it failed at:
../linux/JackLinuxFutex.cpp:31:10: f
Applied, thanks!
Damien Zammit via Bug reports for the GNU Hurd, le sam. 21 déc. 2024 02:39:48
+, a ecrit:
> Previously, we were ignoring cpus that were not enabled
> but online-capable.
> ---
> i386/i386at/acpi_parse_apic.c | 2 +-
> i386/i386at/acpi_parse_apic.h | 2 ++
> 2 files changed,
Hi,
On Sat, Dec 21, 2024 at 10:06:10PM +0300, Sergey Bugaev wrote:
>
> In case you don't realize, there's more than one kernel map.
> kernel_map is the main one, but there are also ipc_kernel_map and
> device_io_map, which are submaps of kernel_map, and others could
> potentially be added.
>
> T
On Fri, Dec 20, 2024 at 5:17 PM Diego Nieto Cid wrote:
> >Also make sure to avoid limiting the kernel's own maps.
>
> Oh right, I need to check for the kernel map, even though the default
> means no limit it may be nice to check at the enforcing point whether
> the allocation happens against the k
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