We have recently updated the interface for raising exceptions to use
long [1] and updated mach_port_t to be "unsigned int". This patches fixes
those problems and will help us port GDB to Hurd x86_64.
Tested on Hurd i686 and x86_64.
[1]
https://git.savannah.gnu.org/cgit/hurd/gnumach.git/tree/incl
TODO: Don't hardcode 0x3000 as the starting eip.
TESTED: works in qemu
TESTED: works hardware with AMD cpu
---
i386/i386/mp_desc.c | 15 +++--
i386/i386/smp.c | 125 +---
i386/i386/smp.h | 5 +-
i386/i386at/cram.h | 5 ++
i386/i386
TESTED: This works in qemu correctly
TESTED: This works on an AMD board with ACPI v2.0 correctly
---
i386/i386/apic.c | 89 +++
i386/i386/apic.h | 5 ++
i386/i386at/acpi_parse_apic.c | 35 ++
i386/i386at/acpi_parse_apic.h | 23
NB: Every x86 board that uses ACPI most likely has a HPET since 2005.
We can roll back to PIT in the cases where its not present,
but the PIT one shot code is definitely currently broken.
---
i386/i386/smp.c | 7 +++
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/i386/i386/smp.c
This initializes the lapic without
turning on the IOAPIC interrupts during SMP init.
---
i386/i386/apic.c | 15 +--
i386/i386/apic.h | 2 ++
i386/i386/mp_desc.c | 18 +++---
i386/i386at/ioapic.c | 1 +
4 files changed, 31 insertions(+), 5 deletions(-)
diff --gi
Hi,
I addressed all the points in review 2.
Here is version 3.
It still boots!
Thanks,
Damien
Damien Zammit, le mar. 06 févr. 2024 03:06:28 +, a ecrit:
> +printf("Sending IPIs to APIC ID %u...\n", apic_id);
> +err = smp_send_ipi_init(apic_id);
> +hpet_mdelay(10);
> +err = smp_send_ipi_startup(apic_id, start_eip / PAGE_SIZE);
> +hpet_udelay(200);
> +err = smp_send
Damien Zammit, le mar. 06 févr. 2024 03:06:20 +, a ecrit:
> +us = (us * NSEC_PER_USEC) / hpet_period_nsec;
> +
> +start = HPET32(HPET_COUNTER);
> +
> +while (1) {
> +now = HPET32(HPET_COUNTER);
> +
> +if (now < start) {
> +/* handle timer overflow within
Damien Zammit, le mar. 06 févr. 2024 03:06:17 +, a ecrit:
> splhigh();
>
> + /* Disable IOAPIC interrupts (IPIs not affected).
> + * Clearing this flag is similar to masking all
> + * IOAPIC interrupts individually */
This is not saying _why_ we do this. Why IOAPIC would