[Bug gas/27065] New: [ARM] If-Then instruction and .align directive

Component: gas Assignee: unassigned at sourceware dot org Reporter: kordalski.wojciech at gmail dot com Target Milestone: --- Created attachment 13048 --> https://sourceware.org/bugzilla/attachment.cgi?id=13048&action=edit The minimal example During research of ARM Co

[Bug gas/27066] New: [ARM] Unaligned LDRD instruction

Assignee: unassigned at sourceware dot org Reporter: kordalski.wojciech at gmail dot com Target Milestone: --- Created attachment 13049 --> https://sourceware.org/bugzilla/attachment.cgi?id=13049&action=edit The minimal example During research of ARM Cortex-M3-based pr

[Bug gas/27066] [ARM] Unaligned LDRD instruction

https://sourceware.org/bugzilla/show_bug.cgi?id=27066 Wojciech Kordalski changed: What|Removed |Added Severity|normal |minor -- You are receiving this

[Bug gas/27066] [ARM] Unaligned LDRD instruction

https://sourceware.org/bugzilla/show_bug.cgi?id=27066 --- Comment #1 from Wojciech Kordalski --- To make this bug report clear: The problem is that the LDRD instruction is not word-aligned (32-bit aligned). The manual states that if the LDRD instruction is not word-aligned, it is UNPREDICTABLE.

[Bug gas/27096] New: [ARM] If-Then instruction and AL condition

Component: gas Assignee: unassigned at sourceware dot org Reporter: kordalski.wojciech at gmail dot com Target Milestone: --- Created attachment 13063 --> https://sourceware.org/bugzilla/attachment.cgi?id=13063&action=edit The minimal example During research of ARM Co

[Bug gas/27099] New: [ARM] ISB instruction inside an IT block

: gas Assignee: unassigned at sourceware dot org Reporter: kordalski.wojciech at gmail dot com Target Milestone: --- Created attachment 13068 --> https://sourceware.org/bugzilla/attachment.cgi?id=13068&action=edit The minimal example During research of ARM Cortex-M

[Bug gas/27099] [ARM] ISB instruction inside an IT block

https://sourceware.org/bugzilla/show_bug.cgi?id=27099 --- Comment #1 from Wojciech Kordalski --- By accident, I did a mistake in the reference to the ARMv7-M Architecture Reference Manual. The note that "ISB instruction inside an IT block is unpredictable" is in Section A7.7.37 ISB, page A7-235.

[Bug gas/27411] New: [ARM] Wrong error message when assembler cannot honor width suffix ("lo register required")

Status: UNCONFIRMED Severity: minor Priority: P2 Component: gas Assignee: unassigned at sourceware dot org Reporter: kordalski.wojciech at gmail dot com Target Milestone: --- Created attachment 13223 --> https://sourceware.org/bugzilla/attachment