https://sourceware.org/bugzilla/show_bug.cgi?id=25599
--- Comment #9 from John Buddery ---
Thanks very much for the analysis - I agree, this is about slot numbers not
offsets and the comment is inaccurate.
I too found the HP behaviour odd, when considering the instruction as using
slots 1 and 2.
https://sourceware.org/bugzilla/show_bug.cgi?id=27837
--- Comment #3 from Nick Clifton ---
Unfortunately I have discovered a problem with the patch: The PowerPC target
does allow -r and --relax to be combined. So it is not correct to just
globally disable the combination. (There may be other ar
https://sourceware.org/bugzilla/show_bug.cgi?id=25599
--- Comment #10 from dave.anglin at bell dot net ---
I think the test is wrong. The brl instruction is comprised of two
instruction slots (L+X). For brl, the
imm39 field and a 2-bit Ignored field occupy the L instruction slot. The
actual br
https://sourceware.org/bugzilla/show_bug.cgi?id=25599
--- Comment #11 from John Buddery ---
I will test movl, break.x and nop.x. They have operands of 64, 62 and 62 bits,
with very different layout to brl, so PCREL60 won't apply. One potential
candidate is PCREL64 against a movl, I'll see if I ca
https://sourceware.org/bugzilla/show_bug.cgi?id=25599
--- Comment #12 from dave.anglin at bell dot net ---
On 2021-05-21 12:15 p.m., jvb at cyberscience dot com wrote:
> Specifying a slot value for a 2 slot instruction + immediate is clearly
> ambiguous without further clarification. HP interprets
https://sourceware.org/bugzilla/show_bug.cgi?id=27897
Bug ID: 27897
Summary: gold generates wrong TLS relocation for IE access
model
Product: binutils
Version: 2.36
Status: UNCONFIRMED
Severity: normal
https://sourceware.org/bugzilla/show_bug.cgi?id=27897
--- Comment #1 from Luo Bo ---
> Further investigation suggests that gold is somehow confused by
> `_ZL6value1@tlsgd(%rip)` generated by GCC (for accessing `value`).
Oops, sorry, I meant "for accessing `value1`".
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https://sourceware.org/bugzilla/show_bug.cgi?id=25599
--- Comment #13 from dave.anglin at bell dot net ---
On 2021-05-21 12:15 p.m., jvb at cyberscience dot com wrote:
> I will test movl, break.x and nop.x. They have operands of 64, 62 and 62 bits,
> with very different layout to brl, so PCREL60 w
Updates:
Labels: -restrict-view-commit -deadline-approaching Deadline-Exceeded
Comment #6 on issue 31168 by sheriffbot: binutils:fuzz_readelf: Timeout in
fuzz_readelf
https://bugs.chromium.org/p/oss-fuzz/issues/detail?id=31168#c6
This bug has exceeded our disclosure deadline. It has been
