[Bug binutils/25202] objcopy --verilog-data-width doesn't respect target's endianness

2022-11-29 Thread sourceware.org at aydos dot de
https://sourceware.org/bugzilla/show_bug.cgi?id=25202 --- Comment #22 from Gökçe Aydos --- I browsed LRM section 21.4 about `$readmemh`, but could not find any info about maximum width (for a memory line that is read by `$readmemh`). I think the range is limited by the maximum width of a vector (

[Bug binutils/25202] objcopy --verilog-data-width doesn't respect target's endianness

2022-11-24 Thread sourceware.org at aydos dot de
https://sourceware.org/bugzilla/show_bug.cgi?id=25202 --- Comment #19 from Gökçe Aydos --- Thanks 🎈 The address generation for data-width>1 looks fine in general. I found the following issues: 1) Output is wrong if data-width>16. Test cases: data-width=1: ``` @8000 B7 C0 ED FE 93 80 D0 EA

[Bug binutils/25202] objcopy --verilog-data-width doesn't respect target's endianness

2022-11-09 Thread sourceware.org at aydos dot de
https://sourceware.org/bugzilla/show_bug.cgi?id=25202 --- Comment #14 from Gökçe Aydos --- (In reply to Olof Kindgren from comment #13) > ... we are dealing with word addresses, but are we taking that into > consideration when we're calculating the base address? > > I.e. compiling an asm program

[Bug binutils/25202] objcopy --verilog-data-width doesn't respect target's endianness

2022-11-08 Thread sourceware.org at aydos dot de
https://sourceware.org/bugzilla/show_bug.cgi?id=25202 --- Comment #12 from Gökçe Aydos --- (In reply to Nick Clifton from comment #10) > >> As the file is read, each number encountered is assigned to a successive > >> word element of the memory. > > In that sentence, what exactly is meant by "

[Bug binutils/25202] objcopy --verilog-data-width doesn't respect target's endianness

2022-11-06 Thread sourceware.org at aydos dot de
https://sourceware.org/bugzilla/show_bug.cgi?id=25202 --- Comment #9 from Gökçe Aydos --- I tested the patch (without the test). My remarks: 1) AFAIK memory addresses are byte addresses in gcc. If --verilog-data-width is greater than 1, then each word in the pattern file becomes something else t

[Bug binutils/25202] objcopy --verilog-data-width doesn't respect target's endianness

2022-11-05 Thread sourceware.org at aydos dot de
https://sourceware.org/bugzilla/show_bug.cgi?id=25202 --- Comment #8 from gökçe --- Thanks for the fast response :) ``` --- /dev/null 2022-11-03 08:18:45.269001160 + +++ 2022-11-03 13:29:21.965562457 + ``` I suppose the testname is missing Nick. -- You are receiving this mail be

[Bug binutils/25202] objcopy --verilog-data-width doesn't respect target's endianness

2022-11-02 Thread sourceware.org at aydos dot de
https://sourceware.org/bugzilla/show_bug.cgi?id=25202 gökçe changed: What|Removed |Added CC||sourceware.org at aydos dot de --- Comment

[Bug gas/24738] New: .value directive undocumented

2019-06-26 Thread sourceware.org at aydos dot de
Assignee: unassigned at sourceware dot org Reporter: sourceware.org at aydos dot de Target Milestone: --- Created attachment 11868 --> https://sourceware.org/bugzilla/attachment.cgi?id=11868&action=edit C code *main.c* is compiled to *main.s*. *main.s* contains a directive

[Bug gas/24737] New: Typo in manual

2019-06-26 Thread sourceware.org at aydos dot de
: unassigned at sourceware dot org Reporter: sourceware.org at aydos dot de Target Milestone: --- In https://www.sourceware.org/binutils/docs/as/Align.html : ... advances the location counter until it a multiple of 8. ... should be: ... advances the location counter until it is a

[Bug gas/24735] New: Typo in manual

2019-06-25 Thread sourceware.org at aydos dot de
: unassigned at sourceware dot org Reporter: sourceware.org at aydos dot de Target Milestone: --- https://sourceware.org/binutils/docs-2.32/as/Zero.html states: ... so in can take an optional second argument ... should be ... so it can take an optional second argument ... -- You are