[Bug gas/24129] [RISCV] .align with fill only partially fills

2019-01-24 Thread asb at lowrisc dot org
https://sourceware.org/bugzilla/show_bug.cgi?id=24129 --- Comment #2 from Alex Bradbury --- Apologies, should have analysed further. Sorry for the noise. -- You are receiving this mail because: You are on the CC list for the bug. ___ bug-binutils mail

[Bug gas/24129] New: [RISCV] .align with fill only partially fills

2019-01-24 Thread asb at lowrisc dot org
Component: gas Assignee: unassigned at sourceware dot org Reporter: asb at lowrisc dot org Target Milestone: --- $ ./riscv32-unknown-elf-as --version | head -n 1 GNU assembler (GNU Binutils) 2.32.51.20190124 $ cat t.s slli s1, s1, 0x14 .align 3, 2 slli s1, s1, 0x14

[Bug gas/23219] New: [RISCV] Internal error with .align and .option norelax

2018-05-23 Thread asb at lowrisc dot org
Component: gas Assignee: unassigned at sourceware dot org Reporter: asb at lowrisc dot org Target Milestone: --- The following test program results in an internal error in the assembler. This is not present if using .align 3, removing a nop, or assembling with

[Bug gas/22598] [RISCV] No way to disable two-instruction sequences for branch or relocation for jal instructions

2018-01-10 Thread asb at lowrisc dot org
https://sourceware.org/bugzilla/show_bug.cgi?id=22598 --- Comment #10 from Alex Bradbury --- Actually I was too quick to respond, it doesn't seem that GNU as is treating immediate arguments to branches in MIPS as absolute addresses: $ cat test.s lab: beq $6, $7, 128 bne $4, $5, 64 beq $6, $7, 12

[Bug gas/22598] [RISCV] No way to disable two-instruction sequences for branch or relocation for jal instructions

2018-01-10 Thread asb at lowrisc dot org
https://sourceware.org/bugzilla/show_bug.cgi?id=22598 --- Comment #9 from Alex Bradbury --- I certainly agree that treating immediate arguments to branch/jump instructions as absolute is consistent with the handling of labels. It seems that at least in the case of Mips, this behaviour is inconsi

[Bug gas/22598] [RISCV] No way to disable two-instruction sequences for branch or relocation for jal instructions

2018-01-09 Thread asb at lowrisc dot org
https://sourceware.org/bugzilla/show_bug.cgi?id=22598 --- Comment #7 from Alex Bradbury --- I would have personally expected jal to take a multiple of two bytes in the range [-1048576, 1048574], branches to take multiple of two bytes in [-4096, 4094] and so on. That would seem consistent with th

[Bug gas/22599] [RISCV] fsrmi and fsflagsi pseudoinstructions aren't recognised

2017-12-13 Thread asb at lowrisc dot org
||asb at lowrisc dot org -- You are receiving this mail because: You are on the CC list for the bug. ___ bug-binutils mailing list bug-binutils@gnu.org https://lists.gnu.org/mailman/listinfo/bug-binutils

[Bug gas/22599] New: [RISCV] fsrmi and fsflagsi pseudoinstructions aren't recognised

2017-12-13 Thread asb at lowrisc dot org
erity: normal Priority: P2 Component: gas Assignee: unassigned at sourceware dot org Reporter: asb at lowrisc dot org Target Milestone: --- Version 2.2 of the RISC-V user level ISA manual defines the fsrmi and fsflagsi pseudoinstructions (table 20.3, page 111)

[Bug gas/22598] [RISCV] No way to disable two-instruction sequences for branch or relocation for jal instructions

2017-12-13 Thread asb at lowrisc dot org
||asb at lowrisc dot org -- You are receiving this mail because: You are on the CC list for the bug. ___ bug-binutils mailing list bug-binutils@gnu.org https://lists.gnu.org/mailman/listinfo/bug-binutils

[Bug gas/22598] New: [RISCV] No way to disable two-instruction sequences for branch or relocation for jal instructions

2017-12-13 Thread asb at lowrisc dot org
: UNCONFIRMED Severity: normal Priority: P2 Component: gas Assignee: unassigned at sourceware dot org Reporter: asb at lowrisc dot org Target Milestone: --- The GNU assembler will always assemble a branch with a numeric offset to branch+jal (with

[Bug gas/22179] New: [RISCV] fmv.w.x and fmv.x.w opcodes are not recognised

2017-09-21 Thread asb at lowrisc dot org
Component: gas Assignee: unassigned at sourceware dot org Reporter: asb at lowrisc dot org Target Milestone: --- The RISC-V 2.2 user-level ISA specification renamed fmv.s.x and fmv.x.s to fmv.w.x and fmv.x.w respectively. gas doesn't recognise these mnem