: binutils
Assignee: unassigned at sourceware dot org
Reporter: anatolymik at gmail dot com
Target Milestone: ---
FF /4 (JMP Ev) is affected by operand size prefix in 64 bit mode. It's wrong.
In 64-bit mode operand size prefix is ignored for this opcode and forced to
64-bit.
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: binutils
Assignee: unassigned at sourceware dot org
Reporter: anatolymik at gmail dot com
Target Milestone: ---
FF /2 (CALL Ev) is affected by operand size prefix in 64 bit mode. It's wrong.
In 64-bit mode operand size prefix is ignored for this opcode.
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Assignee: unassigned at sourceware dot org
Reporter: anatolymik at gmail dot com
Target Milestone: ---
e9 opcode is disassembled wrong for 64-bit mode. 66 prefix affects on
instruction, but for this opcode all operand prefixes are ignored and operand
size is forced to 64-bit
Assignee: unassigned at sourceware dot org
Reporter: anatolymik at gmail dot com
Target Milestone: ---
e8 opcode is disassembled wrong for 64-bit mode. 66 prefix affects on
instruction, but for this opcode all operand prefixes are ignored and operand
size is forced to 64-bit
Assignee: unassigned at sourceware dot org
Reporter: anatolymik at gmail dot com
Target Milestone: ---
from Intel specification de f8-ff is fdivp but not fdivrp
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Assignee: unassigned at sourceware dot org
Reporter: anatolymik at gmail dot com
Target Milestone: ---
from Intel specification de f0-f7 is fdivrp but not fdivp
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Assignee: unassigned at sourceware dot org
Reporter: anatolymik at gmail dot com
Target Milestone: ---
from Intel specification de e8-ef is fsubp but not fsubrp
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Assignee: unassigned at sourceware dot org
Reporter: anatolymik at gmail dot com
Target Milestone: ---
from Intel specification de e0-e7 is fsubrp but no fsubp
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Assignee: unassigned at sourceware dot org
Reporter: anatolymik at gmail dot com
Target Milestone: ---
dd f0 is disassebled as fnop, but this is invalid opcode
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Assignee: unassigned at sourceware dot org
Reporter: anatolymik at gmail dot com
Target Milestone: ---
from Intel specification DC F8-FF is fdiv but not fdivr
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Assignee: unassigned at sourceware dot org
Reporter: anatolymik at gmail dot com
Target Milestone: ---
from Intel specification DC F0-F7 is fdivr but not fdiv
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Assignee: unassigned at sourceware dot org
Reporter: anatolymik at gmail dot com
Target Milestone: ---
from Intel documentation DC E8-EF is fsub but not fsubr
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https://sourceware.org/bugzilla/show_bug.cgi?id=20771
anatoly changed:
What|Removed |Added
Summary|DC E0 wrong opcode name |DC E0-E7 wrong opcode name
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Assignee: unassigned at sourceware dot org
Reporter: anatolymik at gmail dot com
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from Intel specification DC E0 is fsubr but not fsub
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bug
Assignee: unassigned at sourceware dot org
Reporter: anatolymik at gmail dot com
Target Milestone: ---
8e opcode(mov Sw, Ew) is disassembled wrong for source register operand.
There is example for 16-bit mode here:
66 8e c0:mov es, eax
but must be:
66 8e c0:mov es, ax
: binutils
Assignee: unassigned at sourceware dot org
Reporter: anatolymik at gmail dot com
Target Milestone: ---
82 opcode (add Eb, Ib) wrong disassembling for 16 and 32 bit modes
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