Yep, I commented the base version (uint32_t result=0;).
Because it was offending the GNU assembler with:
- strexh r0, r0, [r1]
- strexb r0, r0, [r1]
Then I replaced it by:
- register uint32_t result asm ("r2");
According to ARM documentation, for STREX, Rd must be different from both Rt
and Rn
To solve this problem with ARM cortex m3 I changed the supplied CMSIS file
core_cm3.c
I'm now using:
uint32_t __STREXH(uint16_t value, uint16_t *addr)
{
//uint32_t result=0;
register uint32_t result asm ("r2");
__ASM volatile ("strexh %0, %2, [%1]" : "=r" (result) : "r" (addr), "r"
(valu
