To solve this problem with ARM cortex m3 I changed the supplied CMSIS file
core_cm3.c
I'm now using:
uint32_t __STREXH(uint16_t value, uint16_t *addr)
{
//uint32_t result=0;
register uint32_t result asm ("r2");
__ASM volatile ("strexh %0, %2, [%1]" : "=r" (result) : "r" (addr), "r"
(valu
http://sourceware.org/bugzilla/show_bug.cgi?id=13449
--- Comment #13 from Alexander Graf 2011-12-20 15:04:07
UTC ---
This patch fixes the test case for me:
Index: config/tc-arm.c
===
RCS file: /cvs/src/src/gas/config/tc-arm.c,v
ret
http://sourceware.org/bugzilla/show_bug.cgi?id=13449
--- Comment #12 from Alexander Graf 2011-12-20 14:55:20
UTC ---
Hi Nick,
Sorry for the late reply. I fetched today's CVS and realized that you already
applied patch 3. I now get the following output when compiling on panda1:
Unwind table ind
http://sourceware.org/bugzilla/show_bug.cgi?id=13362
Jonathan Nieder changed:
What|Removed |Added
Status|ASSIGNED|RESOLVED
Resolution|
