Re: [Beowulf] Intel combines Xeon and FPGA in a single socket

> There is only a limited surface area per die and Xeon's are not small. Read the article again :- "By sticking an FPGA on top of a Xeon and linking it via Quick Path Interconnect tech, Intel reckons it has a compelling product for large customers.” So the FPGA is a separate die which happens

Re: [Beowulf] Intel combines Xeon and FPGA in a single socket

but not more than that. Maybe this has changed significantly in the last decade, but I doubt it. There is only a limited surface area per die and Xeon's are not small. if not area, then power. but maybe these are going to be somewhat exotic chips, to which commodity constraints apply more l

Re: [Beowulf] Intel combines Xeon and FPGA in a single socket

On 06/19/2014 10:52 PM, Adam DeConinck wrote: -BEGIN PGP SIGNED MESSAGE- Hash: SHA512 This is interesting... http://www.theregister.co.uk/2014/06/18/intel_fpga_custom_chip/ This is what tensilica did previously though. The issue that we had found playing with it (about a decade ag

[Beowulf] Intel combines Xeon and FPGA in a single socket

-BEGIN PGP SIGNED MESSAGE- Hash: SHA512 This is interesting... http://www.theregister.co.uk/2014/06/18/intel_fpga_custom_chip/ - From the article: "The chip company announced on Wednesday at GigaOm Structure in San Francisco that it is preparing to sell a Xeon E5-FPGA hybrid chip to som