I think what you've got here is basically the idea that "things that are
closer, consume less power and cost less because you don't have the
"interface cost".
A FPU sitting on the bus with the integer ALU inside the chip has minimum
overhead.. No going on and off chip and the associated level shif
Apparently, now that we finally received our own Phi's, this blog has
been taken down? I read through it as content was being added but did
not copy down anything. Did I miss an announcement of a move?
Bill
On 02/12/2013 10:02 AM, Dr Stuart Midgley wrote:
> I've started a blog to document the
On Mar 12, 2013, at 5:45 AM, Mark Hahn wrote:
> trinity a10-5700 has 384 radeon 69xx cores running at 760 MHz,
> delivering 584 SP gflops - 65W iirc. but only 30 GB/s for it and
> the CPU.
>
> let's compare that to a 6930 card: 1280 cores, 154 GB/s, 1920 Gflops.
> about 1/3 the cores, flops,
On Mar 12, 2013, at 5:45 AM, Mark Hahn wrote:
>
>>> I think HSA is potentially interesting for HPC, too.
>>> I really expect
>>> AMD and/or Intel to ship products this year that have a C/GPU chip
>>> mounted on
>>> the same interposer as some high-bandwidth ram.
>>
>> How can an integrated gpu o
On Mar 12, 2013, at 5:45 AM, Mark Hahn wrote:
>>> I don't think it is a useful distinction: both are basiclly
>>> independent
>>> computers. obviously, the programming model of Phi is dramatically
>>> more
>>> like a conventional processor than Nvidia.
>>>
>>
>> Mark, that's the marketing talk a
hi Amjad,
I would like to point to 1 really important practical difference.
co-processors can have magnificent latency from the co-processor to
the cpu. In the nano-seconds.
Accelerators i'd argue typically go via pci-e or similar, so have
horrible latency, in the microseconds or slower.
Acc
