013 11:29 AM
> To: Sun, Yi; Yang, Rong R
> Cc: beignet@lists.freedesktop.org
> Subject: RE: [Beignet] [PATCH] Fix a read64/write64 schedule bug.
>
> Yi,
>
> Could you disable the instruction scheduling and do the regression test again?
>
> export OC
=linux.intel@lists.freedesktop.org
[mailto:beignet-bounces+zhigang.gong=linux.intel@lists.freedesktop.org]
On Behalf Of Sun, Yi
Sent: Thursday, October 17, 2013 8:15 PM
To: Zhigang Gong; Yang, Rong R
Cc: beignet@lists.freedesktop.org
Subject: Re: [Beignet] [PATCH] Fix a read64/write64 schedule bug
Sent: Thursday, October 17, 2013 5:19 PM
> To: Yang, Rong R
> Cc: beignet@lists.freedesktop.org
> Subject: Re: [Beignet] [PATCH] Fix a read64/write64 schedule bug.
>
> LGTM, pushed, thanks.
>
> On Tue, Oct 15, 2013 at 06:36:03PM +0800, Yang Rong wrote:
> > Set the read64
LGTM, pushed, thanks.
On Tue, Oct 15, 2013 at 06:36:03PM +0800, Yang Rong wrote:
> Set the read64/write64 correct data type, otherwise, the dependency will
> wrong.
>
> Signed-off-by: Yang Rong
> ---
> backend/src/backend/gen_insn_selection.cpp | 4 ++--
> 1 file changed, 2 insertions(+), 2 de
Set the read64/write64 correct data type, otherwise, the dependency will wrong.
Signed-off-by: Yang Rong
---
backend/src/backend/gen_insn_selection.cpp | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/backend/src/backend/gen_insn_selection.cpp
b/backend/src/backend/gen_in
