Hi Alex,
With this change the expectation from userspace will be to provide
offset starting the doorbell range received over INFO_IOCTL.
Change looks good to me, we will have INFO_IOCTL to share doorbell info
userspace
Reviewed-by: Saleemkhan Jamadar
Regards,
Saleem
On 09/10/25 00:4
1. Added enum amd_sriov_crit_region_version to support multi versions
2. Added logic in SRIOV mailbox to regonize crit_region version during
req_gpu_init_data
Signed-off-by: Ellen Pan
---
drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c| 3 ++-
drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h| 4 ++
Currently SRIOV runtime will use kiq to write HDP_MEM_FLUSH_CNTL for
hdp flush. This register need to be write from CPU for nbif to aware,
otherwise it will not work.
Implement amdgpu_kiq_hdp_flush and use kiq to do gpu hdp flush during
sriov runtime.
Signed-off-by: Victor Zhao
---
drivers/gpu/
Add kiq hdp flush callbacks for gfx ips to support gpu hdp flush when no
ring presents
Signed-off-by: Victor Zhao
---
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 1 +
drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 5 +++--
drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c | 1 +
drivers/gpu/drm/amd/amdgpu/gfx_v8
From: Dominik Kaszewski
[Why]
dc_check_update_surfaces_for_stream should not have access to entire
DC, especially not a mutable one. Concurrent checks should be able
to run independently of one another, without risk of changing state.
[How]
* Remove access to dc state other than debug and capaci
On 2025-09-26 14:01, Timur Kristóf wrote:
> This series adds support for analog connectors to DC for DCE6-10.
> There are two reasons to add this support:
>
> 1. GPUs that already use DC by default and have analog connectors.
> Some Tonga and Hawaii graphics cards in fact have DVI-I connectors,
>
On Wed, Oct 8, 2025 at 4:12 PM Kim, Jonathan wrote:
>
> [Public]
>
> > -Original Message-
> > From: Alex Deucher
> > Sent: Wednesday, October 8, 2025 1:46 PM
> > To: Kim, Jonathan
> > Cc: amd-gfx@lists.freedesktop.org; Liu, Shaoyun
> > Subject: Re: [PATCH] drm/amdgpu: fix gfx12 mes pack
When passed around internally the upper 8 bits of power limit include
the limit type. This is non-obvious without digging into the nuances
of each function. Instead pass the limit type as an argument to all
applicable layers.
Reviewed-by: Lijo Lazar
Signed-off-by: Mario Limonciello
---
drivers/
A few changes have more whitespace than needed. Clean them up.
Reviewed-by: Lijo Lazar
Signed-off-by: Mario Limonciello
---
drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c | 12 +---
1 file changed, 5 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/vango
Add some extra logs to better help triage blackscreen issues.
* Dump all the links to see if they have sinks associated.
* Print the edid manufacturer & product id associated with a stream that
was just created.
Reviewed-by: Jerry Zuo
Signed-off-by: Aurabindo Pillai
---
.../gpu/drm/amd/displ
From: Wenjing Liu
[why]
Current hdcp trace only tracks hdcp errors. We need to expand the trace
structure for more tracing information.
[how]
Add following traces for hdcp1:
- attempt_count
- downstream_device_count
Add following traces for hdcp2:
- attempt_count
- downstream_device_count
- hdcp
schedule_dc_vmin_vmax() is called by dm_crtc_high_irq(). Hence, we
cannot have the former sleep. Use GFP_NOWAIT for allocation in this
function.
Fixes: 288ec2b5d06d5 ("drm/amd/display: fix dmub access race condition")
Reviewed-by: Sun peng (Leo) Li
Signed-off-by: Aurabindo Pillai
---
drivers/g
From: Wenjing Liu
[how]
The commit update interfaces for dchubbub perfmon meansurement to better
reflect our requirements.
Reviewed-by: Alvin Lee
Signed-off-by: Wenjing Liu
Signed-off-by: Aurabindo Pillai
---
.../gpu/drm/amd/display/dc/inc/hw/dchubbub.h | 36 +++
1 file chan
From: Alvin Lee
[Description]
The DCN401 cursor offload path needs to take into account
use_mall_for_cursor, and also need to ensure the dcn32
function assigns the cursor cache fields (DCN401 uses the
dcn32 implementation).
Reviewed-by: Nicholas Kazlauskas
Signed-off-by: Alvin Lee
Signed-off-b
From: Yihan Zhu
[WHY & HOW]
dppclk rcg power down will flip the poweron flag in the cache to cause dppclk
rcg will never
run the rcg ungate sequence in some condition. Wait 10us to let dpp dto fully
ramp.
Reviewed-by: Ovidiu (Ovi) Bunea
Reviewed-by: Nicholas Kazlauskas
Signed-off-by: Yihan Z
Display Core v3.2.354 release highlights:
* DCN35 dispclk, dppclk & other fixes
* DCN401 cursor offload fix
* Add new block seqeunce-building/executing functions
* null ptr fixes
* DPIA hpd fix
* debug improvements
* Fix performance regression from full updates
On 08/10/2025 09:53, Tvrtko Ursulin wrote:
> Remove member no longer used by the scheduler core.
>
> Signed-off-by: Tvrtko Ursulin
> Cc: Boris Brezillon
> Cc: Rob Herring
> Cc: dri-de...@lists.freedesktop.org
Reviewed-by: Steven Price
> ---
> drivers/gpu/drm/panfrost/panfrost_job.c | 1 -
>
On Tue, 07 Oct 2025 20:40:43 +0100 Mario Limonciello
wrote ---
> On 10/7/25 2:31 PM, Bob Beckett wrote:
> > --- quoted message ---
> >> From: Robert Beckett
> >>> Lijo pointed out to me that
> >>> commit ed4efe426a49 ("drm/amd: Restore cached power limit during resume")
> >>> com
[Public]
> -Original Message-
> From: Alex Deucher
> Sent: Wednesday, October 8, 2025 1:12 PM
> To: Kim, Jonathan
> Cc: amd-gfx@lists.freedesktop.org; Liu, Shaoyun
> Subject: Re: [PATCH] drm/amdgpu: fix gfx12 mes packet submission status check
>
> On Wed, Oct 8, 2025 at 12:51 PM Jonatha
On 10/2/25 12:42 PM, Mario Limonciello wrote:
The shutdown() callback doesn't use the same code as suspend()
callbacks. This series unifies them and then also improves error
handling for all suspend flows.
Mario Limonciello (7):
drm/amd: Unify shutdown() callback behavior
drm/amd: Stop exp
Am 08.10.25 um 15:11 schrieb Maxime Ripard:
The state pointer found in the struct drm_atomic_state internals for
most object is a bit ambiguous, and confusing when those internals also
have old state and new state.
After the recent cleanups, the state pointer only use is to point to the
state
Multiple consecutive boolean function arguments are usually not very
readable.
Replace the ones in ttm_device_init() with flags with the additional
benefit of soon being able to pass in more data with just a one off
code base churning cost.
Signed-off-by: Tvrtko Ursulin
Cc: Alex Deucher
Cc: Chr
From: Will Aitken
The amd-smi tool relies on extended peer link information to report xgmi
link metrics. The necessary xgmi ta command, GET_EXTEND_PEER_LINKS, has
been enabled in the host driver and this change is necessary for the
guest to make use of it. To handle the case where the host driver
To implement fair scheduling we will need as accurate as possible view
into per entity GPU time utilisation. Because sched fence execution time
are only adjusted for accuracy in the free worker we need to process
completed jobs as soon as possible so the metric is most up to date when
view from the
The atomic variable vm_fault_info_updated is used to synchronize access to
adev->gmc.vm_fault_info between the interrupt handler and
get_vm_fault_info().
The default atomic functions like atomic_set() and atomic_read() do not
provide memory barriers. This allows for CPU instruction reordering,
mea
Initialize the return variable "r" to 0 in dm_cache_state() to fix
a potential use of uninitialized variable warning.
The return value for this function might not be a PTR_ERR, in casse if
condition fails. In that case we ensure predictable reutrn.
Signed-off-by: Eslam Khafagy
---
drivers/gpu/d
e/drm/drm_atomic.h | 15 +-
include/drm/drm_atomic_state_helper.h | 3 +
18 files changed, 473 insertions(+), 205 deletions(-)
---
base-commit: aa1c2b073ad23847dd2e7bdc7d30009f34ed7f59
change-id: 20251008-drm-private-obj-reset-ae1e2741027a
Best regards,
--
Maxime Ripard
No functional change but to allow easier refactoring in the future.
Signed-off-by: Tvrtko Ursulin
Cc: Christian König
Cc: Thomas Hellström
---
drivers/gpu/drm/ttm/ttm_pool.c | 29 +
drivers/gpu/drm/ttm/ttm_pool_internal.h | 19
drivers/gpu/drm/
GPUs typically benefit from contiguous memory via reduced TLB pressure and
improved caching performance, where the maximum size of contiguous block
which adds a performance benefit is related to hardware design.
TTM pool allocator by default tries (hard) to allocate up to the system
MAX_PAGE_ORDER
Disclaimer:
Please note that as this series includes a patch which touches a good number of
drivers I will only copy everyone in the cover letter and the respective patch.
Assumption is people are subscribed to dri-devel so can look at the whole series
there. I know someone is bound to complain for
Remove member no longer used by the scheduler core.
Signed-off-by: Tvrtko Ursulin
Cc: Christian König
Cc: Danilo Krummrich
Cc: Matthew Brost
Cc: Philipp Stanner
---
include/drm/gpu_scheduler.h | 3 ---
1 file changed, 3 deletions(-)
diff --git a/include/drm/gpu_scheduler.h b/include/drm/gpu
Remove member no longer used by the scheduler core.
Signed-off-by: Tvrtko Ursulin
Cc: Lyude Paul
Cc: Danilo Krummrich
Cc: nouv...@lists.freedesktop.org
---
drivers/gpu/drm/nouveau/nouveau_sched.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/gpu/drm/nouveau/nouveau_sched.c
b/driv
Remove member no longer used by the scheduler core.
Signed-off-by: Tvrtko Ursulin
Cc: Rob Clark
Cc: linux-arm-...@vger.kernel.org
Cc: freedr...@lists.freedesktop.org
---
drivers/gpu/drm/msm/msm_gem_vma.c| 1 -
drivers/gpu/drm/msm/msm_ringbuffer.c | 1 -
2 files changed, 2 deletions(-)
diff
To make evaluating different scheduling policies easier (no need for
external benchmarks) and perfectly repeatable, lets add some synthetic
workloads built upon mock scheduler unit test infrastructure.
Focus is on two parallel clients (two threads) submitting different job
patterns and logging the
Move the code dealing with entities entering and exiting run queues to
helpers to logically separate it from jobs entering and exiting entities.
Signed-off-by: Tvrtko Ursulin
Cc: Christian König
Cc: Danilo Krummrich
Cc: Matthew Brost
Cc: Philipp Stanner
---
drivers/gpu/drm/scheduler/sched_en
35 matches
Mail list logo
