[Public]
The change here in smu_restore_dpm_user_profile will need a revision of patch 3
also 😊
Thanks,
Lijo
-Original Message-
From: amd-gfx On Behalf Of Mario
Limonciello
Sent: Monday, October 6, 2025 10:11 PM
To: open list:RADEON and AMDGPU DRM DRIVERS
Subject: Re: [PATCH v2 2/5] d
Pass drm_connector to prepare_writeback_job since
drm_writeback_connector now resides within drm_connector.
It also makes it uniform with params passed to other
drm_connector_helper_funcs.
Signed-off-by: Suraj Kandpal
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_wb.c | 2 +-
drivers/gpu/d
Some drivers cannot work with the current design where the connector
is embedded within the drm_writeback_connector such as Intel and
some drivers that can get it working end up adding a lot of checks
all around the code to check if it's a writeback conenctor or not,
this is due to the limitation o
[Public]
Reviewed-by: Lijo Lazar
Thanks,
Lijo
-Original Message-
From: Jesse.Zhang
Sent: Sunday, October 5, 2025 7:04 AM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Koenig, Christian
; Lazar, Lijo ; Zhang, Jesse(Jie)
; Zhang, Jesse(Jie)
Subject: [PATCH] drm/amd/pm: Dis
The firmware limits the max vmid, but align the
settings with the hw limits as well just to be safe.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
b/drivers/
On 02.10.25 23:00, Ard Biesheuvel wrote:
> From: Ard Biesheuvel
>
> The point of isolating code that uses kernel mode FPU in separate
> compilation units is to ensure that even implicit uses of, e.g., SIMD
> registers for spilling occur only in a context where this is permitted,
> i.e., from insi
On Wed, Aug 6, 2025 at 8:19 PM Ellen Pan wrote:
>
> 1. Updated previous layout offsets and sizes to _V1.
> 2. Added v2 layout offset enums for dynamic pf-vf critical region handling.
> 3. Added crit_region version in VF's msg[2] during REQ_INIT_DATA.
> 4. Added support to init critical region v2 d
On 10/6/2025 11:31 AM, Mario Limonciello wrote:
When passed around internally the upper 8 bits of power limit include the limit
type.
This is non-obvious without digging into the nuances of each function.
Instead pass the limit type as an argument to all applicable layers.
Signed-off-by: Mar
User requested power limits and clock settings are already restored as
part of smu_restore_dpm_user_profile(). It's unnecessary to call the
same restore as part of smu_resume().
Revert the following commits to drop that extra restore:
commit ed4efe426a49 ("drm/amd: Restore cached power limit durin
MMIO_REMAP (HDP flush page) exposes a hardware MMIO register window via
a PCI BAR; there are no struct pages backing it (not normal RAM). But
when one device shares memory with another through dma-buf, the receiver
still expects a delivery route—a list of DMA-able chunks—called an
sg_table. For th
This is a note to let you know that I've just added the patch titled
minmax.h: add whitespace around operators and after commas
to the 6.1-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary
The filename of the patch is:
This is a note to let you know that I've just added the patch titled
minmax: simplify min()/max()/clamp() implementation
to the 6.1-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary
The filename of the patch is:
min
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