Replace the freelist (O(n)) used for free block management with a
red-black tree, providing more efficient O(log n) search, insert,
and delete operations. This improves scalability and performance
when managing large numbers of free blocks per order (e.g., hundreds
or thousands).
In the VK-CTS mem
[AMD Official Use Only - AMD Internal Distribution Only]
-Original Message-
From: Alex Deucher
Sent: Wednesday, September 10, 2025 5:07 AM
To: Zhang, Jesse(Jie)
Cc: amd-gfx@lists.freedesktop.org; Deucher, Alexander
; Koenig, Christian
Subject: Re: [PATCH 3/3] drm/amdgpu: Implement user
Avoid constant register reloads while emitting IBs by using a local write
pointer and only updating the size at the end of each helper.
Signed-off-by: Tvrtko Ursulin
---
drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c | 106 +++--
1 file changed, 64 insertions(+), 42 deletions(-)
dif
MMIO_REMAP (HDP flush page) exposes a hardware MMIO register window via a PCI
BAR.
Handle it as fixed I/O:
- map(): if MMIO_REMAP, require P2P, compute the BAR address (bus_addr + page
offset), and build a 1-entry sg_table with dma_map_resource().
- unmap(): if MMIO_REMAP, call dma_unmap_resour
On Mon, Sep 8, 2025 at 4:49 AM Prike Liang wrote:
>
> Add the userq object virtual address get(),mapped() and put()
> helpers for tracking the userq obj va address usage.
This adds too much queue specific info to the user queue structure.
Just set the bo_va flag when you validate the VAs in patch
Functionally now looks good to me but adding more comments for the
changes as Alex pointed would be good to accommodate.
Reviewed-by: Sunil Khatri
On 9/5/2025 4:56 PM, Christian König wrote:
That was actually complete nonsense and not validating the BOs
at all. The code just cleared all VM are
In the lack of better place to put it, Resizable BAR code has been
placed inside pci.c and setup-res.c that do not use it for anything.
Upcoming changes are going to add more Resizable BAR related API
functions to PCI core increasing the Resizable BAR code size from the
current.
As pci.c is huge f
Use `atomic_commit_setup` to change the DC stream state. It's a
preparation to remove from `atomic_check` changes in CRTC color
components of DC stream state and prevent DC to commit TEST_ONLY
changes.
Link: https://gitlab.freedesktop.org/drm/amd/-/issues/
Reviewed-by: Harry Wentland
Signed-o
This reverts commit cab1cec78c8fd52e014546739875a81150f11080.
migrate_vma_pages can fail if a CPU thread faults on the same page.
However, the page table is locked and only one of the new pages will
be inserted. The device driver will see that the MIGRATE_PFN_MIGRATE
bit is cleared if it loses the
This commit adds the pixel_clock field to the display config
struct so that power management (DPM) can use it.
We currently don't have a proper bandwidth calculation on old
GPUs with DCE 6-10 because dce_calcs only supports DCE 11+.
So the power management (DPM) on these GPUs may need to make
ad-h
Track the userq obj for its life time, and reference and
dereference the buffer flag at its creating and destroying
period.
Suggested-by: Alex Deucher
Signed-off-by: Prike Liang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c | 18 ++
drivers/gpu/drm/amd/amdgpu/amdgpu_userq.h | 2
On 10.09.25 10:02, Christian König wrote:
> On 09.09.25 18:21, Alex Deucher wrote:
>> On Tue, Sep 9, 2025 at 12:17 PM Borislav Petkov wrote:
>>>
>>> On Tue, Sep 09, 2025 at 10:43:47AM +0200, Michel Dänzer wrote:
Then the developer needs to tell the user how to enable the debugging
outpu
PCI core provides pci_rebar_size_supported() that helps in checking if
a BAR Size is supported for the BAR or not. Use it in
i915_resize_lmem_bar() to simplify code.
Signed-off-by: Ilpo Järvinen
---
drivers/gpu/drm/i915/gt/intel_region_lmem.c | 10 +++---
1 file changed, 3 insertions(+), 7 d
Extend the userq state for identifying the
userq invalid cases.
Signed-off-by: Prike Liang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c | 2 ++
drivers/gpu/drm/amd/amdgpu/amdgpu_userq.h | 1 +
2 files changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c
b/drivers/gp
Add the userq flag to identify the invalid userq cases.
Signed-off-by: Prike Liang
---
include/uapi/drm/amdgpu_drm.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h
index ff183d239b21..69ebe7784885 100644
--- a/include/uapi/drm/
Keeping waiting the userq fence infinitely untill
hang detection, and then suspend the hang queue and
set the fence error.
Signed-off-by: Prike Liang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c | 11 ---
1 file changed, 8 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/
It requires validating the userq VA whether is mapped before
trying to resume the queue.
Signed-off-by: Prike Liang
Reviewed-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c | 24 +++
drivers/gpu/drm/amd/amdgpu/amdgpu_userq.h | 1 +
2 files changed, 25 inse
Add the userq object virtual address get(),mapped() and put()
helpers for tracking the userq obj va address usage.
Signed-off-by: Prike Liang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_object.h | 1 +
drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c | 73 --
drivers/gpu/drm/amd/amdgpu/
From: Alex Deucher
Add an API to query queue status such as whether the
queue is hung or whether vram is lost.
Reviewed-by: Christian König
Reviewed-by: Sunil Khatri
Signed-off-by: Alex Deucher
Reviewed-by: Prike Liang
---
include/uapi/drm/amdgpu_drm.h | 14 ++
1 file changed, 1
When an user unmaps a userq VA, the driver must ensure
the queue has no in-flight jobs. If there is pending work,
the kernel should wait for the attached eviction (bookkeeping)
fence to signal before deleting the mapping.
Suggested-by: Christian König
Signed-off-by: Prike Liang
---
drivers/gpu/
Query the status of the user queue, currently whether
the queue is hung and whether or not VRAM is lost.
v2: Misc cleanups
Reviewed-by: Sunil Khatri
Signed-off-by: Alex Deucher
Reviewed-by: Prike Liang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c | 35 ++-
drivers/gpu/drm
Optimize the handling of reserved time candidates by replacing the
custom bubble sort with the kernel's standard sort() and rewriting
duplicate removal with a linear-time fast/slow pointer method. The
changes improve sorting from O(N^2) to O(N log N) and duplicate removal
from O(N^2) to O(N), reduc
> > Now with drm_writeback_connector moved to drm_connector it makes more
> > sense use drm_connector as an argument rather than drm_connector.
>
> than drm_writeback_connector
Sure will fix this.
>
> > The writeback connector can easily be derived from drm_connector.
> >
> > Signed-off-by: Sur
Move pci_rebar_bytes_to_size() from include/linux/pci.h into rebar.c as
it does not look very trivial and is not expected to be performance
critical.
Convert literals to use a newly added PCI_REBAR_MIN_SIZE define.
Also add kernel doc for the function as the function is exported.
Signed-off-by:
On 2025-09-08 12:15, James Zhu wrote:
This reverts commit cab1cec78c8fd52e014546739875a81150f11080.
migrate_vma_pages can fail if a CPU thread faults on the same page.
However, the page table is locked and only one of the new pages will
be inserted. The device driver will see that the MIGRATE_
On 2025-06-18 11:19, Melissa Wen wrote:
> From: Rodrigo Siqueira
>
> Since DC is a shared code, this commit introduces a new file to work as
> a mid-layer in DC for the edid manipulation.
>
> Signed-off-by: Rodrigo Siqueira
> Co-developed-by: Melissa Wen
> Signed-off-by: Melissa Wen
>
> -
Mario,
> When the ACPI core uses hibernation callbacks for shutdown drivers
> will receive PM_EVENT_POWEROFF and should handle it the same as
> PM_EVENT_HIBERNATE would have been used.
No objections from me wrt. the SCSI changes.
Reviewed-by: Martin K. Petersen
--
Martin K. Petersen
On Thu, Sep 11, 2025 at 10:46 AM Alex Deucher wrote:
>
> On Wed, Sep 10, 2025 at 2:38 PM Timur Kristóf wrote:
> >
> > On Wed, 2025-09-10 at 11:10 -0400, Marek Olšák wrote:
> > > I added the comment into Mesa that 0x3fff00 is the limit. I did
> > > research on that bug separately from PAL, but I d
A variety of issues both in function and in power consumption have been
raised as a result of devices not being put into a low power state when
the system is powered off.
There have been some localized changes[1] to PCI core to help these issues,
but they have had various downsides.
This series i
On Tue, Sep 9, 2025 at 9:16 PM Mario Limonciello (AMD)
wrote:
>
> In order to unify suspend and hibernate codepaths without code duplication
> the common code should be in common helpers. Move it from
> pci_pm_suspend_noirq() into a helper. No intended functional changes.
You should say why you
Avoid constant register reloads while emitting IBs by using a local write
pointer and only updating the size at the end of each helper.
Signed-off-by: Tvrtko Ursulin
---
drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c | 66 +++
1 file changed, 36 insertions(+), 30 deletions(-)
dif
[Public]
The purpose is to keep thermal related interfaces separate going forward. It's
not about this one alone.
Thanks,
Lijo
From: amd-gfx on behalf of Yang Wang
Sent: Tuesday, September 9, 2025 7:51:10 AM
To: amd-gfx@lists.freedesktop.org
Cc: Kamal, Asad
Enable the cleaner shader for additional GFX11.5.2/11.5.3 series GPUs to
ensure data isolation among GPU tasks. The cleaner shader is tasked with
clearing the Local Data Store (LDS), Vector General Purpose Registers
(VGPRs), and Scalar General Purpose Registers (SGPRs), which helps avoid
data leaka
Avoid constant register reloads while emitting IBs by using a local write
pointer and only updating the size at the end of each helper.
Signed-off-by: Tvrtko Ursulin
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 101 +---
1 file changed, 55 insertions(+), 46 deletions(-)
dif
@alexh...@amd.com@Wentland, Harry
Were you planning to pick this up for this week's promotion or should
I grab it?
Thanks,
Alex
On Wed, Sep 3, 2025 at 11:27 AM Timur Kristóf wrote:
>
> On Tue, 2025-08-26 at 10:06 -0400, Alex Deucher wrote:
> > On Mon, Aug 25, 2025 at 5:33 PM Timur Kristóf
> >
On 8/25/25 02:52, Xi Ruoyao wrote:
dml21_map_dc_state_into_dml_display_cfg calls (the call is usually
inlined by the compiler) populate_dml21_surface_config_from_plane_state
and populate_dml21_plane_config_from_plane_state which may use FPU. In
a x86-64 build:
$ objdump --disassemble=dm
[Public]
Regards,
Prike
> -Original Message-
> From: amd-gfx On Behalf Of Alex
> Deucher
> Sent: Friday, September 12, 2025 3:02 AM
> To: Liang, Prike
> Cc: amd-gfx@lists.freedesktop.org; Deucher, Alexander
> ; Koenig, Christian
> Subject: Re: [PATCH 5/9] drm/amdgpu: add userq ob
[Public]
Regards,
Prike
> -Original Message-
> From: Alex Deucher
> Sent: Friday, September 12, 2025 2:55 AM
> To: Liang, Prike
> Cc: amd-gfx@lists.freedesktop.org; Deucher, Alexander
> ; Koenig, Christian ;
> Khatri, Sunil
> Subject: Re: [PATCH 1/9] drm/amdgpu: add UAPI for user
On 9/11/25 12:48 PM, Matthew Schwartz wrote:
On clients that utilize AMD_PRIVATE_COLOR properties for HDR support,
brightness sliders can include a hardware controlled portion and a
gamma-based portion. This is the case on the Steam Deck OLED when using
gamescope with Steam as a client.
When a u
Use memset32 instead of open coding it, just because it is
that bit nicer.
Signed-off-by: Tvrtko Ursulin
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c | 12 ++--
1 file changed, 10 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
b/drivers/gpu/drm/amd/
Avoid constant register reloads while emitting IBs by using a local write
pointer and only updating the size at the end of each helper.
Signed-off-by: Tvrtko Ursulin
---
drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 109 +++--
1 file changed, 65 insertions(+), 44 deletions(-)
dif
On Wed, Sep 10, 2025 at 7:44 AM Prike Liang wrote:
>
> When a user unmaps a userq VA, the driver must ensure
> the queue has no in-flight jobs. If there is pending work,
> the kernel should wait for the attached eviction (bookkeeping)
> fence to signal before deleting the mapping.
>
Seems reasona
On Wed, Sep 10, 2025 at 4:24 AM Jesse.Zhang wrote:
>
> This patch adds robust reset handling for user queues (userq) to improve
> recovery from queue failures. The key components include:
>
> 1. Queue detection and reset logic:
>- amdgpu_userq_detect_and_reset_queues() identifies failed queues
On Wed, Sep 10, 2025 at 8:14 AM Prike Liang wrote:
>
> Keeping waiting the userq fence infinitely untill
> hang detection, and then suspend the hang queue and
> set the fence error.
>
> Signed-off-by: Prike Liang
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c | 11 ---
> 1 file change
On Wed, Sep 10, 2025 at 7:54 AM Prike Liang wrote:
>
> Add the userq object virtual address get(),mapped() and put()
> helpers for tracking the userq obj va address usage.
>
> Signed-off-by: Prike Liang
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_object.h | 1 +
> drivers/gpu/drm/amd/amdgpu/amdgp
In short, this series mostly does a lot of replacing of this pattern:
ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
ib->ptr[ib->length_dw++] = lower_32_bits(pe);
ib->ptr[ib->length_dw++] = upper_3
On 11/09/2025 15:32, Philipp Stanner wrote:
On Wed, 2025-09-03 at 11:18 +0100, Tvrtko Ursulin wrote:
There is no need to keep entities with no jobs in the tree so lets remove
it once the last job is consumed. This keeps the tree smaller which is
nicer and more efficient as entities are removed
On Thu, Sep 11, 2025 at 1:25 PM Alex Deucher wrote:
>
> SDMA 5.2.x has increased transfer limits.
>
> v2: fix harder, use shifts to make it more obvious
>
> Signed-off-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
>
On 10/09/2025 16:54, Harry Wentland wrote:
On 2025-06-18 11:19, Melissa Wen wrote:
From: Rodrigo Siqueira
As part of the effort of stopping using raw edid, this commit move the
copy of the edid in DC to a dedicated function that will allow the usage
of drm_edid in the next steps.
Signed-o
On 10/09/2025 16:52, Harry Wentland wrote:
On 2025-06-18 11:19, Melissa Wen wrote:
From: Rodrigo Siqueira
Since DC is a shared code, this commit introduces a new file to work as
a mid-layer in DC for the edid manipulation.
Signed-off-by: Rodrigo Siqueira
Co-developed-by: Melissa Wen
Sig
Don't update DC stream color components during atomic check. The driver
will continue validating the new CRTC color state but will not change DC
stream color components. The DC stream color state will only be
programmed at commit time in the `atomic_setup_commit` stage.
It fixes gamma LUT loss rep
On Thu, Sep 11, 2025 at 1:14 PM Shaoyun Liu wrote:
>
> MES pipe0 will do VM invalidation with engine set 5 when assign VMID to a
> process,
> driver will submit inv_tlb package to mes pipe1. It might run into race
> condition
> if both pipes use the same invalidate engine set. From MES version 0
SDMA 7.0 has increased transfer limits.
v2: fix harder, use shifts to make it more obvious
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c
b/drivers/gpu/drm/amd
>-Original Message-
>From: dri-devel On Behalf Of Ilpo
>Järvinen
>Sent: Thursday, September 11, 2025 3:56 AM
>To: linux-...@vger.kernel.org; Bjorn Helgaas ;
>Krzysztof Wilczyński ; Christian König
>; Winiarski, Michal ;
>Alex Deucher ; amd-gfx@lists.freedesktop.org;
>David Airlie ; dri-de.
SDMA 4.4.x has increased transfer limits.
v2: fix harder, use shifts to make it more obvious
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 19 ---
1 file changed, 16 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
b/
SDMA 5.2.x has increased transfer limits.
v2: fix harder, use shifts to make it more obvious
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
b/drivers/gpu/drm/a
On Thu, Sep 11, 2025 at 8:09 AM Christian König
wrote:
>
> That was actually complete nonsense and not validating the BOs
> at all. The code just cleared all VM areas were it couldn't grab the
> lock for a BO.
>
> Try to fix this. Only compile tested at the moment.
>
> v2: fix fence slot reservati
SDMA 4.4.x has increased transfer limits.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 15 ++-
1 file changed, 14 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
index f38004e6064e
On 11/09/2025 15:20, Philipp Stanner wrote:
On Wed, 2025-09-03 at 11:18 +0100, Tvrtko Ursulin wrote:
Move the code dealing with entities entering and exiting run queues to
helpers to logically separate it from jobs entering and exiting entities.
Sorry if I've asked this before, but does this
On 11.09.25 16:38, Srinivasan Shanmugam wrote:
> The HDP flush page (AMDGPU_PL_MMIO_REMAP) is an MMIO window, not RAM.
> It must not be migrated to GTT/VRAM by dma-buf paths.
>
> This change makes pin/unpin no-ops for MMIO_REMAP and skips CPU-access
> migration, keeping the object fixed.
Just use
On Wed, Sep 10, 2025 at 2:38 PM Timur Kristóf wrote:
>
> On Wed, 2025-09-10 at 11:10 -0400, Marek Olšák wrote:
> > I added the comment into Mesa that 0x3fff00 is the limit. I did
> > research on that bug separately from PAL, but I don't remember the
> > details.
> >
> > There is no performance to
SDMA 6.x has increased transfer limits.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c
b/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c
index db6e41967f126..fbaeecb5f52
SDMA 4.4.x has increased transfer limits.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c
b/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c
index 36b1ca73c2ed3..35b
On 11.09.25 16:38, Srinivasan Shanmugam wrote:
> This keeps MMIO_REMAP fixed for its whole lifetime.
> Other buffers (VRAM/GTT) are unchanged.
>
> This change pins it when we export the dma-buf.
> If the export fails, we undo the pin.
> When the dma-buf is released, we unpin it.
>
> MMIO_REMAP (H
This series makes the amdgpu dma-buf exporter handle
AMDGPU_PL_MMIO_REMAP (the HDP flush page) as a BAR-mapped register
window (MMIO)
* Only compilation tested so far (x86_64, defconfig + amdgpu enabled).
Cc: Christian König
Cc: Alex Deucher
Srinivasan Shanmugam (4):
drm/amdgpu/dma-buf: Add
Acked-by: Sunil Khatri
On 9/11/2025 5:39 PM, Christian König wrote:
It turned out that protecting the status of each bo_va with a
spinlock was just hiding problems instead of solving them.
Revert the whole approach, add a separate stats_lock and lockdep
assertions that the correct reservation
Reviewed-by: Sunil Khatri
Rest later i will try to improve the definition of each list with more
details for clarity.
On 9/11/2025 5:39 PM, Christian König wrote:
Re-order fields in the VM structure and try to improve the
documentation a bit.
Signed-off-by: Christian König
---
drivers/gpu
PCIe r6.2 section 7.8.6 defines resizable BAR sizes beyond the
currently supported maximum of 128TB which will require more than u32
to store the entire bitmask.
Convert Resizable BAR related functions to use u64 bitmask for BAR
sizes to make the typing more future-proof.
The support for the larg
Avoid constant register reloads while emitting IBs by using a local write
pointer and only updating the size at the end of each helper.
Signed-off-by: Tvrtko Ursulin
---
drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c | 110 +++--
1 file changed, 66 insertions(+), 44 deletions(-)
dif
Avoid constant register reloads while emitting IBs by using a local write
pointer and only updating the size at the end of each helper.
Signed-off-by: Tvrtko Ursulin
---
drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.c | 46 +
1 file changed, 24 insertions(+), 22 deletions(-)
dif
Re-order fields in the VM structure and try to improve the
documentation a bit.
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h | 30 --
1 file changed, 24 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
b/driv
It turned out that protecting the status of each bo_va with a
spinlock was just hiding problems instead of solving them.
Revert the whole approach, add a separate stats_lock and lockdep
assertions that the correct reservation lock is held all over the place.
This not only allows for better checks
We should leave such checks to lockdep and not implement something
manually.
Signed-off-by: Christian König
Acked-by: Sunil Khatri
Reviewed-by: Prike Liang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 13 +
1 file changed, 1 insertion(+), 12 deletions(-)
diff --git a/drivers/gpu/d
Avoid constant register reloads while emitting IBs by using a local write
pointer and only updating the size at the end of each helper.
Signed-off-by: Tvrtko Ursulin
---
drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c | 119 +++--
1 file changed, 70 insertions(+), 49 deletions(-)
dif
Avoid constant register reloads while emitting IBs by using a local write
pointer and only updating the size at the end of each helper.
Signed-off-by: Tvrtko Ursulin
---
drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c | 108 +++--
1 file changed, 65 insertions(+), 43 deletions(-)
dif
Avoid constant register reloads while emitting IBs by using a local write
pointer and only updating the size at the end of each helper.
Signed-off-by: Tvrtko Ursulin
---
drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c | 108 +++--
1 file changed, 65 insertions(+), 43 deletions(-)
dif
Avoid constant register reloads while emitting IBs by using a local write
pointer and only updating the size at the end of each helper.
Signed-off-by: Tvrtko Ursulin
---
drivers/gpu/drm/amd/amdgpu/cik_sdma.c | 105 +++---
1 file changed, 63 insertions(+), 42 deletions(-)
dif
Avoid constant register reloads while emitting IBs by using a local write
pointer and only updating the size at the end of each helper.
Signed-off-by: Tvrtko Ursulin
---
drivers/gpu/drm/amd/amdgpu/si_dma.c | 84 +
1 file changed, 51 insertions(+), 33 deletions(-)
diff
Avoid constant register reloads while emitting IBs by using a local write
pointer and only updating the size at the end of each helper.
Signed-off-by: Tvrtko Ursulin
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c | 90 +
1 file changed, 48 insertions(+), 42 deletions(-)
dif
Also i would recomment to split the change into two
a. Revert the status locks in one
b. Rest of the changes in another one.
Agree to what Alex has proposed as its not more the same revert anymore.
Regards
Sunil Khatri
On 9/5/2025 10:19 PM, Alex Deucher wrote:
+ Philip
On Fri, Sep 5, 2025 at
On 11.09.25 10:59, Ilpo Järvinen wrote:
> On Thu, 11 Sep 2025, Christian König wrote:
>
>> On 11.09.25 09:55, Ilpo Järvinen wrote:
>>> Fix the copy-pasted errors in the Resizable BAR handling functions
>>> kernel doc and generally improve wording choices.
>>>
>>> Fix the formatting errors of the R
On 11.09.25 09:55, Ilpo Järvinen wrote:
> Fix the copy-pasted errors in the Resizable BAR handling functions
> kernel doc and generally improve wording choices.
>
> Fix the formatting errors of the Return: line.
>
> Signed-off-by: Ilpo Järvinen
> ---
> drivers/pci/rebar.c | 29 +
On 9/10/25 2:32 PM, Mario Limonciello wrote:
> On 9/10/25 4:27 PM, Matthew Schwartz wrote:
>> On clients that utilize AMD_PRIVATE_COLOR properties for HDR support,
>> brightness sliders can include a hardware controlled portion and a
>> gamma-based portion. This is the case on the Steam Deck OLED w
On clients that utilize AMD_PRIVATE_COLOR properties for HDR support,
brightness sliders can include a hardware controlled portion and a
gamma-based portion. This is the case on the Steam Deck OLED when using
gamescope with Steam as a client.
When a user sets a brightness level while HDR is active
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