Re: [Intel-gfx] [PATCH 2/2] drm/i915/edp/jsl: Update vswing table for HBR and HBR2

On Mon, Sep 28, 2020 at 04:43:11PM +0300, Jani Nikula wrote: > On Mon, 28 Sep 2020, Tejas Upadhyay > wrote: > > JSL has update in vswing table for eDP > > I've thought the TLA for Jasper Lake is JSP, not JSL. At least we have > PCH_JSP for Jasper Lake PCH. JSP == Point (the PCH), JSL == Lake -

Re: [Intel-gfx] [PATCH 2/2] drm/i915/edp/jsl: Update vswing table for HBR and HBR2

On Mon, Sep 28, 2020 at 04:43:11PM +0300, Jani Nikula wrote: > On Mon, 28 Sep 2020, Tejas Upadhyay > wrote: > > JSL has update in vswing table for eDP > > I've thought the TLA for Jasper Lake is JSP, not JSL. At least we have > PCH_JSP for Jasper Lake PCH. JSP == Point (the PCH), JSL == Lake -

Re: [Intel-gfx] [PATCH 2/2] drm/i915/edp/jsl: Update vswing table for HBR and HBR2

On Mon, Sep 28, 2020 at 04:43:11PM +0300, Jani Nikula wrote: > On Mon, 28 Sep 2020, Tejas Upadhyay > wrote: > > JSL has update in vswing table for eDP > > I've thought the TLA for Jasper Lake is JSP, not JSL. At least we have > PCH_JSP for Jasper Lake PCH. JSP == Point (the PCH), JSL == Lake -

Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/gt: Implement WA_1406941453 (rev2)

On Thu, Aug 06, 2020 at 12:09:53AM +, Patchwork wrote: > == Series Details == > > Series: drm/i915/gt: Implement WA_1406941453 (rev2) > URL : https://patchwork.freedesktop.org/series/78243/ > State : failure > > == Summary == > > CI Bug Log - changes from CI_DRM_8846 -> Patchwork_18312 > =

Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/gt: Implement WA_1406941453

On Fri, Jun 12, 2020 at 12:04:35AM +, Patchwork wrote: > == Series Details == > > Series: drm/i915/gt: Implement WA_1406941453 > URL : https://patchwork.freedesktop.org/series/78243/ > State : failure > > == Summary == > > CI Bug Log - changes from CI_DRM_8618 -> Patchwork_17931 >

Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [1/5] drm: Add __drm_atomic_helper_crtc_state_reset() & co. (rev3)

(+Lakshmi) On Tue, Dec 17, 2019 at 06:33:58PM +, Souza, Jose wrote: > On Tue, 2019-12-17 at 18:10 +, Patchwork wrote: > > == Series Details == > > > > Series: series starting with [1/5] drm: Add > > __drm_atomic_helper_crtc_state_reset() & co. (rev3) > > URL : https://patchwork.freedesk

Re: [Intel-gfx] [PATCH 3/4] drm/i915/dp: Fix MST disable sequences

On Tue, Dec 10, 2019 at 11:38:50PM +0200, Ville Syrjälä wrote: > On Fri, Dec 06, 2019 at 05:18:31PM -0800, José Roberto de Souza wrote: > > The disable sequence after wait for transcoder off was not correctly > > implemented. > > The MST disable sequence is basically the same for HSW, SKL, ICL and

[Bug 1727662]

Johan - can you re-run on drm-tip, and see if the issue persists? If it does, please provide the dmesg log output -- You received this bug notification because you are a member of Ubuntu Bugs, which is subscribed to Ubuntu. https://bugs.launchpad.net/bugs/1727662 Title: [Lenovo ThinkPad T450s]

[Kernel-packages] [Bug 1727662]

Johan - can you re-run on drm-tip, and see if the issue persists? If it does, please provide the dmesg log output -- You received this bug notification because you are a member of Kernel Packages, which is subscribed to linux in Ubuntu. https://bugs.launchpad.net/bugs/1727662 Title: [Lenovo Th

Re: [Intel-gfx] [PATCH] drm/i915/tgl: Add second TGL PCH ID

On Wed, Nov 06, 2019 at 04:25:27PM -0800, Lucas De Marchi wrote: > On Tue, Nov 05, 2019 at 05:13:29PM -0800, Jose Souza wrote: > >On Tue, 2019-11-05 at 16:55 -0800, James Ausmus wrote: > >> Another TGP ID has shown up, so let's add it to avoid South Display > >> br

Re: [Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/tgl: Add second TGL PCH ID

On Wed, Nov 06, 2019 at 10:26:10PM +, Patchwork wrote: > == Series Details == > > Series: drm/i915/tgl: Add second TGL PCH ID > URL : https://patchwork.freedesktop.org/series/69023/ > State : success > > == Summary == > > CI Bug Log - changes from CI_DRM_7264_full -> Patchwork_15140_full >

[Intel-gfx] [PATCH] drm/i915/tgl: Add second TGL PCH ID

Another TGP ID has shown up, so let's add it to avoid South Display breakage on systems that have this ID. Cc: Lucas De Marchi Cc: José Roberto de Souza Signed-off-by: James Ausmus --- drivers/gpu/drm/i915/intel_pch.c | 1 + drivers/gpu/drm/i915/intel_pch.h | 1 + 2 files chang

Re: [Intel-gfx] [PATCH v9 2/2] drm/i915: Restrict qgv points which don't have enough bandwidth.

> to prevent commit being applied out of order in case of > nonblocking and/or nomodeset commits. > > v4: > - Minor code refactoring, fixed few typos(thanks to James Ausmus) > - Change the naming of qgv point > masking/unmasking functions(James Ausmus). &g

Re: [Intel-gfx] [PATCH v8 2/2] drm/i915: Restrict qgv points which don't have enough bandwidth.

> to prevent commit being applied out of order in case of > nonblocking and/or nomodeset commits. > > v4: > - Minor code refactoring, fixed few typos(thanks to James Ausmus) > - Change the naming of qgv point > masking/unmasking functions(James Ausmus). &g

Re: [Intel-gfx] [PATCH v4] drm/i915/cml: Remove unsupport PCI ID

On Sat, Oct 26, 2019 at 04:32:25AM +0800, Lee Shawn C wrote: > commit 'a7b4deeb02b9 ("drm/i915/cml: Add CML PCI IDS)' > introduced new PCI ID that CML support. But some sku > is not support yet so remove them. A better description would be that some PCI IDs were removed from the CML IDs in BSpec.

Re: [Intel-gfx] [PATCH v6 1/2] drm/i915: Refactor intel_can_enable_sagv

ates. > if that fails rollback to usual Level 0 > latency and disable SAGV. > - Remove unneeded tabs(James Ausmus) > > v3: Rebased the patch > > Signed-off-by: Stanislav Lisovskiy > Cc: Ville Syrjälä > Cc: James Ausmus > --- > .../drm/i915/dis

Re: [Intel-gfx] [PATCH v4 1/2] drm/i915: Refactor intel_can_enable_sagv

On Fri, Oct 18, 2019 at 01:34:35AM -0700, Lisovskiy, Stanislav wrote: > On Thu, 2019-10-17 at 14:53 -0700, James Ausmus wrote: > > On Tue, Oct 15, 2019 at 04:50:12PM +0300, Stanislav Lisovskiy wrote: > > > Currently intel_can_enable_sagv function contains > > > a mix o

Re: [Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/aml: Allow SPT PCH for all AML devices (rev2)

On Fri, Oct 18, 2019 at 08:20:44AM +, Patchwork wrote: > == Series Details == > > Series: drm/i915/aml: Allow SPT PCH for all AML devices (rev2) > URL : https://patchwork.freedesktop.org/series/68176/ > State : success > > == Summary == > > CI Bug Log - changes from CI_DRM_7125_full -> Pat

Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/aml: Allow SPT PCH for all AML devices

On Fri, Oct 18, 2019 at 01:00:59AM +, Patchwork wrote: > == Series Details == > > Series: drm/i915/aml: Allow SPT PCH for all AML devices > URL : https://patchwork.freedesktop.org/series/68176/ > State : failure > > == Summary == > > CI Bug Log - changes from CI_DRM_7125 -> Patchwork_14867

Re: [Intel-gfx] [PATCH v4 2/2] drm/i915: Restrict qgv points which don't have enough bandwidth.

> to prevent commit being applied out of order in case of > nonblocking and/or nomodeset commits. > > v4: > - Minor code refactoring, fixed few typos(thanks to James Ausmus) > - Change the naming of qgv point > masking/unmasking functions(James Ausmus). &g

Re: [Intel-gfx] [PATCH v4 1/2] drm/i915: Refactor intel_can_enable_sagv

ned-off-by: Stanislav Lisovskiy > Cc: Ville Syrjälä > Cc: James Ausmus > --- > drivers/gpu/drm/i915/intel_pm.c | 73 +++-- > 1 file changed, 70 insertions(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/int

[Intel-gfx] [PATCH] drm/i915/aml: Allow SPT PCH for all AML devices

Even the AML devices that behave like CFLs can be paired with an SPT PCH. Allow this to happen without blowing up dmesg. BSpec: 33665 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=112013 Cc: Quanxian Wang Cc: Rodrigo Vivi Signed-off-by: James Ausmus --- drivers/gpu/drm/i915

Re: [Intel-gfx] [PATCH v3] drm/i915: Restrict qgv points which don't have enough bandwidth.

On Mon, Oct 14, 2019 at 05:50:18PM +0300, Ville Syrjälä wrote: > On Mon, Oct 14, 2019 at 02:13:31PM +0300, Lisovskiy, Stanislav wrote: > > On Fri, 2019-10-11 at 16:49 -0700, James Ausmus wrote: > > > > + new_qgv_points

Re: [Intel-gfx] [PATCH v3] drm/i915: Restrict qgv points which don't have enough bandwidth.

On Mon, Oct 14, 2019 at 04:13:31AM -0700, Lisovskiy, Stanislav wrote: > On Fri, 2019-10-11 at 16:49 -0700, James Ausmus wrote: > > On Wed, Sep 25, 2019 at 03:17:37PM +0300, Stanislav Lisovskiy wrote: > > > According to BSpec 53998, we should try to > > > restrict qgv

Re: [Intel-gfx] [PATCH v3] drm/i915: Restrict qgv points which don't have enough bandwidth.

> to prevent commit being applied out of order in case of > nonblocking and/or nomodeset commits. > > Signed-off-by: Stanislav Lisovskiy > Cc: Ville Syrjälä > Cc: James Ausmus > --- > drivers/gpu/drm/i915/display/intel_atomic.c | 16 > drivers/gpu/d

Re: [Intel-gfx] [PATCH] drm/i915/cml: Add second PCH ID for CMP

On Wed, Oct 09, 2019 at 01:00:07PM -0700, Rodrigo Vivi wrote: > On Wed, Oct 09, 2019 at 10:29:43AM -0700, Matt Roper wrote: > > On Wed, Oct 09, 2019 at 10:03:31AM +0300, Timo Aaltonen wrote: > > > On 17.9.2019 2.32, Matt Roper wrote: > > > > The CMP PCH ID we have in the driver is correct for the C

Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [CI,1/2] drm/i915: Move SAGV block time to dev_priv

On Wed, Oct 09, 2019 at 06:15:26PM +, Patchwork wrote: > == Series Details == > > Series: series starting with [CI,1/2] drm/i915: Move SAGV block time to > dev_priv > URL : https://patchwork.freedesktop.org/series/67799/ > State : failure > > == Summary == > > CI Bug Log - changes from CI

[Intel-gfx] [CI v3 2/2] drm/i915/tgl: Read SAGV block time from PCODE

Starting from TGL, we now need to read the SAGV block time via a PCODE mailbox, rather than having a static value. BSpec: 49326 v2: Fix up pcode val data type (Ville), tighten variable scope (Ville) Cc: Ville Syrjälä Cc: Stanislav Lisovskiy Cc: Lucas De Marchi Signed-off-by: James Ausmus

[Intel-gfx] [CI v3 1/2] drm/i915: Move SAGV block time to dev_priv

jälä Cc: Stanislav Lisovskiy Cc: Lucas De Marchi Signed-off-by: James Ausmus Reviewed-by: Ville Syrjälä --- drivers/gpu/drm/i915/i915_drv.h | 2 ++ drivers/gpu/drm/i915/intel_pm.c | 33 - 2 files changed, 26 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/

Re: [Intel-gfx] [PATCH v2 2/2] drm/i915/tgl: Read SAGV block time from PCODE

On Mon, Oct 07, 2019 at 01:15:24PM +0300, Ville Syrjälä wrote: > On Fri, Oct 04, 2019 at 02:51:34PM -0700, James Ausmus wrote: > > On Fri, Oct 04, 2019 at 01:55:46PM -0700, Lucas De Marchi wrote: > > > On Fri, Sep 27, 2019 at 03:24:27PM -0700, James Ausmus wrote: > > >

[Intel-gfx] [PATCH v3 2/2] drm/i915/tgl: Read SAGV block time from PCODE

Starting from TGL, we now need to read the SAGV block time via a PCODE mailbox, rather than having a static value. BSpec: 49326 v2: Fix up pcode val data type (Ville), tighten variable scope (Ville) Cc: Ville Syrjälä Cc: Stanislav Lisovskiy Cc: Lucas De Marchi Signed-off-by: James Ausmus

[Intel-gfx] [PATCH v3 1/2] drm/i915: Move SAGV block time to dev_priv

jälä Cc: Stanislav Lisovskiy Cc: Lucas De Marchi Signed-off-by: James Ausmus --- drivers/gpu/drm/i915/i915_drv.h | 2 ++ drivers/gpu/drm/i915/intel_pm.c | 33 - 2 files changed, 26 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers

Re: [Intel-gfx] [PATCH v2 1/2] drm/i915: Move SAGV block time to dev_priv

On Fri, Oct 04, 2019 at 01:53:57PM -0700, Lucas De Marchi wrote: > On Fri, Sep 27, 2019 at 03:24:26PM -0700, James Ausmus wrote: > >In prep for newer platforms having more complicated ways to determine > >the SAGV block time, move the variable to dev_priv, and extract the > >

Re: [Intel-gfx] [PATCH v2 2/2] drm/i915/tgl: Read SAGV block time from PCODE

On Fri, Oct 04, 2019 at 01:55:46PM -0700, Lucas De Marchi wrote: > On Fri, Sep 27, 2019 at 03:24:27PM -0700, James Ausmus wrote: > >Starting from TGL, we now need to read the SAGV block time via a PCODE > >mailbox, rather than having a static value. > > > >BSpec: 49326

Re: [Intel-gfx] [PATCH v2 1/2] drm/i915: Move SAGV block time to dev_priv

On Fri, Sep 27, 2019 at 03:24:26PM -0700, James Ausmus wrote: > In prep for newer platforms having more complicated ways to determine > the SAGV block time, move the variable to dev_priv, and extract the > setting to an initial setup function. While we're at it, update the if >

[Intel-gfx] [PATCH v2 2/2] drm/i915/tgl: Read SAGV block time from PCODE

Starting from TGL, we now need to read the SAGV block time via a PCODE mailbox, rather than having a static value. BSpec: 49326 v2: Fix up pcode val data type (Ville), tighten variable scope (Ville) Cc: Ville Syrjälä Cc: Stanislav Lisovskiy Cc: Lucas De Marchi Signed-off-by: James Ausmus

[Intel-gfx] [CI v2 1/2] drm/i915: Move SAGV block time to dev_priv

pecified gen. v2: Shorten the function name (Ville), return directly (Ville), move sagv_block_time_us value to dev_priv (Ville) Cc: Ville Syrjälä Cc: Stanislav Lisovskiy Cc: Lucas De Marchi Signed-off-by: James Ausmus --- Resending for CI, as I evidently confused Patchwork... drivers/gpu/

[Intel-gfx] [PATCH v2 1/2] drm/i915: Move SAGV block time to dev_priv

pecified gen. v2: Shorten the function name (Ville), return directly (Ville), move sagv_block_time_us value to dev_priv (Ville) Cc: Ville Syrjälä Cc: Stanislav Lisovskiy Cc: Lucas De Marchi Signed-off-by: James Ausmus --- Ville - with the amount of v1..v2 change in this first patch,

[Intel-gfx] [PATCH v2 2/2] drm/i915/tgl: Read SAGV block time from PCODE

Starting from TGL, we now need to read the SAGV block time via a PCODE mailbox, rather than having a static value. BSpec: 49326 v2: Fix up pcode val data type (Ville), tighten variable scope (Ville) Cc: Ville Syrjälä Cc: Stanislav Lisovskiy Cc: Lucas De Marchi Signed-off-by: James Ausmus

Re: [Intel-gfx] [PATCH 3/3] drm/i915/tgl: Remove single pipe restriction from SAGV

On Thu, Sep 26, 2019 at 03:34:35PM +0300, Ville Syrjälä wrote: > On Wed, Sep 25, 2019 at 01:33:52PM -0700, James Ausmus wrote: > > For Gen12, BSpec no longer tells us to disable SAGV when > 1 pipe is > > active. Update intel_can_enable_sagv to allow this, and loop through all &g

Re: [Intel-gfx] [PATCH v2] drm/i915/tgl: Add memory type decoding for bandwidth checking

On Wed, Sep 25, 2019 at 03:35:28PM -0700, Summers, Stuart wrote: > On Wed, 2019-09-25 at 08:35 -0700, James Ausmus wrote: > > On Wed, Sep 25, 2019 at 07:33:38AM -0700, Summers, Stuart wrote: > > > On Tue, 2019-09-24 at 15:28 -0700, James Ausmus wrote: > > > > The memo

[Intel-gfx] [PATCH 3/3] drm/i915/tgl: Remove single pipe restriction from SAGV

Cc: Lucas De Marchi Signed-off-by: James Ausmus --- drivers/gpu/drm/i915/intel_pm.c | 63 + 1 file changed, 32 insertions(+), 31 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index ca2bec09edb5..cb50c697a6b8 100644 --

[Intel-gfx] [PATCH 2/3] drm/i915/tgl: Read SAGV block time from PCODE

Starting from TGL, we now need to read the SAGV block time via a PCODE mailbox, rather than having a static value. BSpec: 49326 Cc: Ville Syrjälä Cc: Stanislav Lisovskiy Cc: Lucas De Marchi Signed-off-by: James Ausmus --- drivers/gpu/drm/i915/i915_reg.h | 1 + drivers/gpu/drm/i915

[Intel-gfx] [PATCH 1/3] drm/i915: Extract SAGV block time function

tanislav Lisovskiy Cc: Lucas De Marchi Signed-off-by: James Ausmus --- drivers/gpu/drm/i915/intel_pm.c | 24 ++-- 1 file changed, 18 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 6bed2ed14574..5ad72dcb0faa 1006

[Intel-gfx] Add support for TGL in SAGV code paths

Even though we can't actually turn on SAGV for TGL until HSDES 1409542895 is resolved, these patches prepare the code for enabling SAGV, so that once the HSDES is resolved, all we have to do is revert 8ffa4392a32e ("drm/i915/tgl: disable SAGV temporarily") to turn it on. _

Re: [Intel-gfx] [PATCH v2] drm/i915/tgl: Add memory type decoding for bandwidth checking

On Wed, Sep 25, 2019 at 07:33:38AM -0700, Summers, Stuart wrote: > On Tue, 2019-09-24 at 15:28 -0700, James Ausmus wrote: > > The memory type values have changed in TGL, so we need to translate > > them > > differently than ICL. While we're moving it, fix up the ICL >

[Intel-gfx] [PATCH v2] drm/i915/tgl: Add memory type decoding for bandwidth checking

igned-off-by: James Ausmus Reviewed-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_bw.c | 55 ++--- 1 file changed, 39 insertions(+), 16 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c index cd58e47

Re: [Intel-gfx] [v2][PATCH] drm/i915: Add Pipe D cursor ctrl register for Gen12

On Tue, Sep 24, 2019 at 01:01:52PM +0530, Nautiyal, Ankit K wrote: > From: Ankit Nautiyal Just a nit: Can you modify the subject to be "drm/i915/tgl" to make it easier for backporters to identify? > > Currently the offset for PIPE D cursor control register is missing in > i915_reg.h due to whic

Re: [Intel-gfx] [PATCH] drm/i915/tgl: Add memory type decoding for bandwidth checking

On Fri, Sep 20, 2019 at 03:29:06PM +0300, Ville Syrjälä wrote: > On Thu, Sep 19, 2019 at 03:16:40PM -0700, James Ausmus wrote: > > The memory type values have changed in TGL, so we need to translate them > > differently than ICL. > > > > BSpec: 53998 > > > &g

Re: [Intel-gfx] [PATCH v3] drm/i915: Add TigerLake bandwidth checking

> + else if (IS_GEN(dev_priv, 12)) Same comment here > + icl_get_bw_info(dev_priv, &tgl_sa_info); > } > > static unsigned int intel_max_data_rate(struct drm_i915_private *dev_priv, > int num_planes) &g

Re: [Intel-gfx] [PATCH v1] drm/i915: Add TigerLake bandwidth checking

On Tue, Sep 17, 2019 at 04:00:57PM +0300, Stanislav Lisovskiy wrote: > Added bandwidth calculation algorithm and checks, > similar way as it was done for ICL, some constants > were corrected according to BSpec. Heh - I'd been working in this same area, and had some code written up, but your patch

Re: [Intel-gfx] [PATCH 22/22] drm/i915/mst: Do not hardcoded the crtcs that encoder can connect

On Thu, Jul 18, 2019 at 04:10:13PM +0300, Ville Syrjälä wrote: > On Fri, Jul 12, 2019 at 06:09:40PM -0700, Lucas De Marchi wrote: > > From: José Roberto de Souza > > > > Tiger Lake has up to 4 pipes so the mask would need to be 0xf instead of > > 0x7. Do not hardcode the mask so it allows the fak

Re: [Intel-gfx] [PATCH] drm/i915/icl: Enable DC9 as lowest possible state during screen-off

On Tue, Oct 23, 2018 at 01:34:54PM -0700, Rodrigo Vivi wrote: > On Tue, Oct 23, 2018 at 01:01:11PM -0700, James Ausmus wrote: > > On Tue, Oct 23, 2018 at 11:52:31AM -0700, Rodrigo Vivi wrote: > > > On Tue, Oct 23, 2018 at 11:32:21AM -0700, Anusha Srivatsa wrote: > >

Re: [Intel-gfx] [PATCH] drm/i915/icl: Enable DC9 as lowest possible state during screen-off

On Tue, Oct 23, 2018 at 11:52:31AM -0700, Rodrigo Vivi wrote: > On Tue, Oct 23, 2018 at 11:32:21AM -0700, Anusha Srivatsa wrote: > > From: Animesh Manna > > > > ICL supports DC5, DC6, and DC9. Enable DC9 during screen-off, and enable > > DC5/6 when appropriate.

D15013: balootctl: fix 396535

jausmus added a comment. In D15013#314082 , @bruns wrote: > 1. Use a proper commit message, with subject and body > 2. Please use "arc diff ..." to upload the diff, revisions without context are hard to review. Will do, my apologies. Ha

D15013: balootctl: fix 396535

jausmus added a comment. In D15013#313885 , @mgallien wrote: > In D15013#313880 , @jausmus wrote: > > > In D15013#313867 , @anthonyfieroni wrote: > > >

D15013: balootctl: fix 396535

jausmus added a comment. In D15013#313867 , @anthonyfieroni wrote: > Do not use QDir::separator > > if (!folder.endsWith(QLatin1Char('/')) { > folder += QLatin1Char('/'); > } > Does balooctl not need cross platform sup

[frameworks-baloo] [Bug 396535] Balooctl seems to assume folders with hyphens in name are subfolders

https://bugs.kde.org/show_bug.cgi?id=396535 --- Comment #2 from James Ausmus --- Created attachment 114556 --> https://bugs.kde.org/attachment.cgi?id=114556&action=edit Fixes issue by appending path separator to parent dir check -- You are receiving this mail because: You are watch

D15013: balootctl: fix 396535

jausmus created this revision. jausmus added a project: Baloo. Herald added a project: Frameworks. Herald added subscribers: Baloo, kde-frameworks-devel. jausmus requested review of this revision. REPOSITORY R293 Baloo REVISION DETAIL https://phabricator.kde.org/D15013 AFFECTED FILES src/t

[frameworks-baloo] [Bug 396535] Balooctl seems to assume folders with hyphens in name are subfolders

https://bugs.kde.org/show_bug.cgi?id=396535 James Ausmus changed: What|Removed |Added Status|UNCONFIRMED |ASSIGNED Assignee|baloo-bugs-n

[frameworks-baloo] [Bug 396535] Balooctl seems to assume folders with hyphens in name are subfolders

https://bugs.kde.org/show_bug.cgi?id=396535 James Ausmus changed: What|Removed |Added CC||james.aus...@gmail.com --- Comment #1 from

Re: [Intel-gfx] [PATCH 27/24] drm/i915/dp: Add support for HBR3 and TPS4 during link training

patch adds the helpers to check if HBR3 is supported and uses > TPS4 in training pattern selection during link training. > > Cc: James Ausmus > Cc: Rodrigo Vivi > Cc: Jani Nikula > Signed-off-by: Manasi Navare Reviewed-by: James Ausmus > --- > drivers/gpu/drm/i915/i91

Re: [Intel-gfx] [PATCH 26/24] drm/i915/icl: Add allowed DP rates for Icelake

DP alternate mode, DP over TBT, > - DP on legacy connector - DDIC/D/E/F) > > Cc: Rodrigo Vivi > Cc: Jani Nikula > Cc: James Ausmus > Signed-off-by: Manasi Navare > Signed-off-by: James Ausmus Reviewed-by: James Ausmus > --- > drivers/gpu/drm/i915/intel_dp.c

Re: [Intel-gfx] [PATCH 08/24] drm/i915/icl: Map VBT DDC Pin to BSpec DDC Pin

; | PORT-2 | 0x5 | 0xA| > | PORT-3 | 0x6 | 0xB| > | PORT-4 | 0x7 | 0xC | > +--+---++ > > Cc: James Ausmus > Cc: Jani Nikula > Cc: Anusha Srivatsa > Cc: Clinton Ta

Re: [Intel-gfx] [PATCH 3/8] drm/i915/icl: add basic support for the ICL clocks

compute the actual PLL values, which are marked as TODO > comments and should be introduced as separate commits. > > Special thanks to James Ausmus for investigating and fixing a bug with > the placement of icl_unmap_plls_to_ports() function. > > v2: > - Rebase around dpll_

Re: [Intel-gfx] [PATCH 2/8] drm/i915/icl: add definitions for the ICL PLL registers

n for upstreaming. > v4: Fix MG_CLKTOP2_CORECLKCTL1 address and random typos (James). > > Cc: James Ausmus > Signed-off-by: Paulo Zanoni Reviewed-by: James Ausmus > --- > drivers/gpu/drm/i915/i915_reg.h | 149 > > 1 file changed, 149

Re: [Intel-gfx] [PATCH 3/8] drm/i915/icl: add basic support for the ICL clocks

compute the actual PLL values, which are marked as TODO > comments and should be introduced as separate commits. > > Special thanks to James Ausmus for investigating and fixing a bug with > the placement of icl_unmap_plls_to_ports() function. > > v2: > - Rebase around dpll_

Re: [Intel-gfx] [PATCH 04/17] drm/i915/icl: compute the combo PHY (DPLL) DP registers

> + { .dco_integer = 0x151, .dco_fraction = 0x4000, /* [7]: 8.1 */ > + .pdiv = 0x1 /* 2 */, .kdiv = 1, .qdiv_mode = 0, .qdiv_ratio = 0}, > +}; > + Maybe: /* Also used for 38.4MHz values */ Either way - Reviewed-by: James Ausmus > +static const struct skl_wrpll_params icl_

Re: [Intel-gfx] [PATCH 03/17] drm/i915/icl: compute the combo PHY (DPLL) HDMI registers

g like /* * ICL BSpec states "If reference frequency is 38.4, use 19.2 because * the DPLL automatically divides that by 2." */ With that - Reviewed-by: James Ausmus > + ref_clock = 19200; > + > + cnl_wrpll_params_populate(wrpll_params, best_dco, ref_clock, pd

Re: [Intel-gfx] [PATCH 02/17] drm/i915/icl: add basic support for the ICL clocks

l_ddi_pre_enable_dp(struct intel_encoder *encoder, > diff --git a/drivers/gpu/drm/i915/intel_display.c > b/drivers/gpu/drm/i915/intel_display.c > index 5d46771d58f6..bc4131a36c10 100644 > --- a/drivers/gpu/drm/i915/intel_display.c > +++ b/drivers/gpu/drm/i915/intel_display.c > @@ -

Re: [Intel-gfx] [PATCH 01/17] drm/i915/icl: add definitions for the ICL PLL registers

On Thu, Feb 22, 2018 at 12:55:03AM -0300, Paulo Zanoni wrote: > There's a lot of code for the PLL enabling, so let's first only > introduce the register definitions in order to make patch reviewing a > little easier. > > v2: Coding style (Jani). > v3: Preparation for upstreaming. > > Signed-off-b

Re: [Intel-gfx] [PATCH] drm/i915/cnl: Sync PCI ID with Spec.

ong and we were missing > a pci id. So to make our lives easier when checking against > spec let's simplify and sort like spec does. > > BSpec: 13621 > > Cc: Lucas De Marchi > Cc: James Ausmus > Signed-off-by: Rodrigo Vivi Matches BSpec. Reviewed-by: Ja

Re: [Intel-gfx] [PATCH] drm/i915: Fix incorrect comment

> CC: Jani Nikula > CC: Rodrigo Vivi > Signed-off-by: David Weinehall Matches my read of BSpec. Reviewed-by: James Ausmus > --- > drivers/gpu/drm/i915/intel_dp.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/intel_dp

Re: [Intel-gfx] [PATCH 3/5] drm/i915: Call i915_pipe_update_start with uncore.lock held.

On Fri, Feb 09, 2018 at 10:54:02AM +0100, Maarten Lankhorst wrote: > This requires being able to read the vblank counter with the > uncore.lock already held. This is also a preparation for > being able to run the entire vblank update sequence with > the uncore lock held. > > Signed-off-by: Maarten

Re: [Intel-gfx] [PATCH 2/6] drm/i915/icl: add the main CDCLK functions

ot;bypass" clock (Imre). > - Call intel_dump_cdclk_state() too. > - Rename a variable to avoid confusion. > - Simplify the DVFS part. > v4: > - Remove wrong bit definition (James). > - Also drive-by fix the coding style for the register definition we > touched.

Re: [Intel-gfx] [PATCH 01/17] drm/i915/icl: add the main CDCLK functions

On Fri, Feb 02, 2018 at 05:57:02PM -0200, Paulo Zanoni wrote: > This commit adds the basic CDCLK functions, but it's still missing > pieces of the display initialization sequence. > > v2: > - Implement the voltage levels. > - Rebase. > v3: > - Adjust to the new "bypass" clock (Imre). > - Call

Re: [Intel-gfx] [PATCH 02/17] drm/i915/icl: add ICL support to cnl_set_procmon_ref_values

27;t use a ternary operation when you can use _MMIO_PORT (Ville). > Add an extra comment about why we're passing PORT_A (James). > > Signed-off-by: Paulo Zanoni Reviewed-by: James Ausmus > --- > drivers/gpu/drm/i915/i915_reg.h | 22 ++ > driv

Re: [Intel-gfx] [PATCH 06/17] drm/i915/icl: Do not fix dbuf block size to 512

; Reviewed-by: Paulo Zanoni > Signed-off-by: Mahesh Kumar > Signed-off-by: Paulo Zanoni Reviewed-by: James Ausmus > --- > drivers/gpu/drm/i915/i915_drv.h | 1 + > drivers/gpu/drm/i915/intel_pm.c | 24 +--- > 2 files changed, 18 insertions(+), 7 deletions

Re: [Intel-gfx] [PATCH 07/17] drm/i915/icl: Fail flip if ddb allocated are less than min display buffer needed

ssue. > > Reviewed-by: Paulo Zanoni > Signed-off-by: Mahesh Kumar > Signed-off-by: Paulo Zanoni Reviewed-by: James Ausmus > --- > drivers/gpu/drm/i915/intel_pm.c | 30 +- > 1 file changed, 29 insertions(+), 1 deletion(-) > > diff --git

Re: [Intel-gfx] [PATCH 03/17] drm/i915/icl: implement the display init/uninit sequences

ily adapt code in case the spec changes more later. > > We're still missing the power wells and the mbus code, so leave those > pieces with a FIXME comment while they're not here yet. > > v2: Don't use _PICK, don't WARN_ON(1), don't forget the chicken bits. >

Re: [Intel-gfx] [PATCH 01/17] drm/i915/icl: add the main CDCLK functions

On Tue, Jan 23, 2018 at 05:05:20PM -0200, Paulo Zanoni wrote: > This commit adds the basic CDCLK functions, but it's still missing > pieces of the display initialization sequence. > > v2: > - Implement the voltage levels. > - Rebase. > > Signed-off-by: Paulo Zanoni > --- > drivers/gpu/drm/i91

Re: [Intel-gfx] [PATCH 02/17] drm/i915/icl: add ICL support to cnl_set_procmon_ref_values

On Fri, Jan 26, 2018 at 06:24:32PM -0200, Paulo Zanoni wrote: > Em Ter, 2018-01-23 às 16:32 -0800, James Ausmus escreveu: > > On Tue, Jan 23, 2018 at 05:05:21PM -0200, Paulo Zanoni wrote: > > > On ICL we have two sets of registers: one for port A and another > > > for &g

Re: [Intel-gfx] [PATCH 16/17] drm/i915/icl: enable SAGV for ICL platform

On Tue, Jan 23, 2018 at 05:05:35PM -0200, Paulo Zanoni wrote: > From: Mahesh Kumar > > Enable SAGV for ICL platform. > > Signed-off-by: Mahesh Kumar Reviewed-by: James Ausmus > --- > drivers/gpu/drm/i915/intel_pm.c | 2 +- > 1 file changed, 1 insertion(+), 1 delet

Re: [Intel-gfx] [PATCH 15/17] drm/i915/gen11: fix the SAGV block time for gen11

On Tue, Jan 23, 2018 at 05:05:34PM -0200, Paulo Zanoni wrote: > It's 10us for gen 11. > > Reviewed-by: Mahesh Kumar > Signed-off-by: Paulo Zanoni Reviewed-by: James Ausmus > --- > drivers/gpu/drm/i915/intel_pm.c | 9 - > 1 file changed, 8 insertions(+), 1 d

Re: [Intel-gfx] [PATCH 12/17] drm/i915/icl: track dbuf slice-2 status

-off-by: Mahesh Kumar Reviewed-by: James Ausmus > --- > drivers/gpu/drm/i915/i915_drv.h | 1 + > drivers/gpu/drm/i915/intel_display.c| 5 + > drivers/gpu/drm/i915/intel_pm.c | 20 > drivers/gpu/drm/i915/intel_runtime_pm.c | 4 ++

Re: [Intel-gfx] [PATCH 14/17] drm/i915/icl: update ddb entry start/end mask during hw ddb readout

On Tue, Jan 23, 2018 at 05:05:33PM -0200, Paulo Zanoni wrote: > From: Mahesh Kumar > > Gen11/ICL onward ddb entry start/end mask is increased from 10 bits to > 11 bits. This patch make changes to use proper mask for ICL+ during > hardware ddb value readout. > > Signed-off-by: Mahesh Kumar > ---

Re: [Intel-gfx] [PATCH 13/17] drm/i915/icl: Enable 2nd DBuf slice only when needed

On Tue, Jan 23, 2018 at 05:05:32PM -0200, Paulo Zanoni wrote: > From: Mahesh Kumar > > ICL has two slices of DBuf, each slice of size 1024 blocks. > We should not always enable slice-2. It should be enabled only if > display total required BW is > 12GBps OR more than 1 pipes are enabled. > > Cha

Re: [Intel-gfx] [PATCH 11/17] drm/i915/icl: program mbus during pipe enable

d WARN_ON (Paulo) > - Remove TODO comment > - Program 0 during pipe disable > - Rebase > > Reviewed-by: Paulo Zanoni > Signed-off-by: Mahesh Kumar > Signed-off-by: Paulo Zanoni Reviewed-by: James Ausmus > --- > drivers/gpu/drm/i915/intel_display.c | 20 ++

Re: [Intel-gfx] [PATCH 10/17] drm/i915/icl: initialize MBus during display init

e to use function like Macros > > Reviewed-by: Paulo Zanoni > Signed-off-by: Mahesh Kumar > Signed-off-by: Paulo Zanoni Reviewed-by: James Ausmus > --- > drivers/gpu/drm/i915/intel_runtime_pm.c | 14 +- > 1 file changed, 13 insertions(+), 1 deletion(-) > > d

Re: [Intel-gfx] [PATCH 09/17] drm/i915/icl: Introduce MBus related registers

os (Paulo) > - fix copy-paste error (Paulo) > > Reviewed-by: Paulo Zanoni > Signed-off-by: Mahesh Kumar > Signed-off-by: Paulo Zanoni Reviewed-by: James Ausmus > --- > drivers/gpu/drm/i915/i915_reg.h | 25 + > 1 file changed, 25 insertions(

Re: [Intel-gfx] [PATCH 08/17] drm/i915/icl: NV12 y-plane ddb is not in same plane

Zanoni > Signed-off-by: Mahesh Kumar > Signed-off-by: Paulo Zanoni Reviewed-by: James Ausmus > --- > drivers/gpu/drm/i915/intel_pm.c | 6 -- > 1 file changed, 4 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_

Re: [Intel-gfx] [PATCH 06/17] drm/i915/icl: Do not fix dbuf block size to 512

On Tue, Jan 23, 2018 at 05:05:25PM -0200, Paulo Zanoni wrote: > From: Mahesh Kumar > > GEN9/10 had fixed DBuf block size of 512. Dbuf block size is not a > fixed number anymore in GEN11, it varies according to bits per pixel > and tiling. If 8bpp & Yf-tile surface, block size = 256 else block > s

Re: [Intel-gfx] [PATCH 05/17] drm/i915/icl: Don't allocate fixed bypass path blocks for ICL

> > v2 (from Paulo): > - No need for a comment that says what the code already says. > > Reviewed-by: Paulo Zanoni > Signed-off-by: Mahesh Kumar > Signed-off-by: Paulo Zanoni Reviewed-by: James Ausmus > --- > drivers/gpu/drm/i915/intel_pm.c | 3 ++- > 1 file changed

Re: [Intel-gfx] [PATCH 04/17] drm/i915/icl: Enable both DBuf slices during init

On Tue, Jan 23, 2018 at 05:05:23PM -0200, Paulo Zanoni wrote: > From: Mahesh Kumar > > ICL has 2 slices of DBuf, enable both the slices during display init. > > Ideally we should only enable the second slice when needed in order to > save power, but while we're not there yet, adopt the simpler s

Re: [Intel-gfx] [PATCH 02/17] drm/i915/icl: add ICL support to cnl_set_procmon_ref_values

cnl_display_core_init(struct drm_i915_private *dev_priv, bool > resume) > @@ -2811,7 +2818,7 @@ static void cnl_display_core_init(struct > drm_i915_private *dev_priv, bool resume > val &= ~CNL_COMP_PWR_DOWN; > I915_WRITE(CHICKEN_MISC_2, val); > > - cnl_set_proc

Re: [Intel-gfx] [PATCH 6/8] drm/i915/icp: Add backlight Support for ICP

On Fri, Jan 19, 2018 at 09:26:02AM -0800, Anusha Srivatsa wrote: > On Fri, Jan 19, 2018 at 02:40:41PM -0200, Paulo Zanoni wrote: > > Em Qui, 2018-01-11 às 15:57 -0800, Rodrigo Vivi escreveu: > > > On Thu, Jan 11, 2018 at 09:48:57PM +, James Ausmus wrote: > > > >

Re: [Intel-gfx] [PATCH 6/8] drm/i915/icp: Add backlight Support for ICP

On Thu, Jan 11, 2018 at 04:00:08PM -0200, Paulo Zanoni wrote: > From: Anusha Srivatsa > > ICP has two backlight controllers - similar to previous platforms like > BXT. > > v2: Remove the usage of ICP_SECOND_PPS_BACKLIGHT register.(Jani) > Reuse BXT code since it is very similar.(Ville) > > v3 (

[Intel-gfx] [PATCH] drm/i915/cnl: Mask previous DDI - PLL mapping

Bugzilla link Fixes: 555e38d273172 ("drm/i915/cnl: DDI - PLL mapping") Testcase: igt/testdisplay Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103997 Cc: Rodrigo Vivi Cc: Matt Atwood Signed-off-by: James Ausmus --- drivers/gpu/drm/i915/intel_ddi.c | 1 + 1 file changed, 1 insertio

[Intel-gfx] [PATCH] drm/i915/cnl: Mask previous DDI - PLL mapping

: 555e38d273172 ("drm/i915/cnl: DDI - PLL mapping") Testcase: igt/testdisplay Cc: Rodrigo Vivi Cc: Matt Atwood Signed-off-by: James Ausmus --- drivers/gpu/drm/i915/intel_ddi.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_d

Re: [Intel-gfx] [PATCH v6 03/10] drm/i915: s/enum plane/enum i9xx_plane_id/

_id doesn't apply to SKL+ > v4: Rebase due to power domain handling in plane readout > v5: Rebase due to crtc->dspaddr_offset removal > v6: s/plane/i9xx_plane/ etc. (James) > > Cc: James Ausmus > Cc: Daniel Vetter > Signed-off-by: Ville Syrjälä And h

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