Re: set mtu size broken for dwmac-sun8i
Le Wed, Mar 17, 2021 at 10:19:26AM +0100, Belisko Marek a écrit : > Hi, > > I'm hunting an issue when setting mtu failed for dwmac-sun8i driver. > Basically adding more debug shows that in stmmac_change_mtu > tx_fifo_size is 0 and in this case EINVAL is reported. Isaw there was > fix for similar driver dwmac-sunxi driver by: > 806fd188ce2a4f8b587e83e73c478e6484fbfa55 > > IIRC dwmac-sun8i should get tx and rx fifo size from dma but seems > it's not the case. I'm using 5.4 kernel LTS release. Any ideas? > > Thanks and BR, > > marek > Hello Could you provide exact command line you tried to change mtu ? Along with all MTU values you tried. Thanks Regards
Re: set mtu size broken for dwmac-sun8i
Le Wed, Mar 17, 2021 at 12:37:48PM +0100, Belisko Marek a écrit :
> On Wed, Mar 17, 2021 at 12:33 PM Corentin Labbe
> wrote:
> >
> > Le Wed, Mar 17, 2021 at 10:19:26AM +0100, Belisko Marek a écrit :
> > > Hi,
> > >
> > > I'm hunting an issue when setting mtu failed for dwmac-sun8i driver.
> > > Basically adding more debug shows that in stmmac_change_mtu
> > > tx_fifo_size is 0 and in this case EINVAL is reported. Isaw there was
> > > fix for similar driver dwmac-sunxi driver by:
> > > 806fd188ce2a4f8b587e83e73c478e6484fbfa55
> > >
> > > IIRC dwmac-sun8i should get tx and rx fifo size from dma but seems
> > > it's not the case. I'm using 5.4 kernel LTS release. Any ideas?
> > >
> > > Thanks and BR,
> > >
> > > marek
> > >
> >
> > Hello
> >
> > Could you provide exact command line you tried to change mtu ?
> > Along with all MTU values you tried.
> I tried with ifconfig eth0 down && ifconfig eth0 mtu 1400 return:
> ifconfig: SIOCSIFMTU: Invalid argument
>
> btw board is orange-pi-pc-plus
> >
> > Thanks
> > Regards
>
I have added as CC sunxi maintainers
I can confirm that dwmac-sun8i need the same fix as
806fd188ce2a4f8b587e83e73c478e6484fbfa55.
With the patch below, I successfully changed MTU ... and the network is still
working.
My first test was on orange-pi-pc which is the same SoC than your board.
I test this patch on all other sunxi SoCs and I send it upstream after.
@netdev, does there is some specific MTU values interesting to test ? (I
curently try 68 500 1000 1200 1400 1500 1600 9000)
Regards
Author: Corentin Labbe
Date: Wed Mar 17 16:49:50 2021 +0100
net: stmmac: dwmac-sun8i: Provide TX and RX fifo sizes
MTU cannot be changed on dwmac-sun8i.
This is due to tx_fifo_size being 0.
Like dwmac-sunxi (with 806fd188ce2a ("net: stmmac: dwmac-sunxi: Provide TX
and RX fifo sizes"))
dwmac-sun8i need to have tx and rx fifo sizes set.
Fixes: 9f93ac8d408 ("net-next: stmmac: Add dwmac-sun8i")
Reported-by: Belisko Marek
Signed-off-by: Corentin Labbe
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
index 6b75cf2603ff..e62efd166ec8 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
@@ -1214,6 +1214,8 @@ static int sun8i_dwmac_probe(struct platform_device *pdev)
plat_dat->init = sun8i_dwmac_init;
plat_dat->exit = sun8i_dwmac_exit;
plat_dat->setup = sun8i_dwmac_setup;
+ plat_dat->tx_fifo_size = 4096;
+ plat_dat->rx_fifo_size = 16384;
ret = sun8i_dwmac_set_syscon(&pdev->dev, plat_dat);
if (ret)
[PATCH] net: stmmac: dwmac-sun8i: Provide TX and RX fifo sizes
MTU cannot be changed on dwmac-sun8i. (ip link set eth0 mtu xxx returning
EINVAL)
This is due to tx_fifo_size being 0, since this value is used to compute valid
MTU range.
Like dwmac-sunxi (with commit 806fd188ce2a ("net: stmmac: dwmac-sunxi: Provide
TX and RX fifo sizes"))
dwmac-sun8i need to have tx and rx fifo sizes set.
I have used values from datasheets.
After this patch, setting a non-default MTU (like 1000) value works and network
is still useable.
Tested-on: sun8i-h3-orangepi-pc
Tested-on: sun8i-r40-bananapi-m2-ultra
Tested-on: sun50i-a64-bananapi-m64
Tested-on: sun50i-h5-nanopi-neo-plus2
Tested-on: sun50i-h6-pine-h64
Fixes: 9f93ac8d408 ("net-next: stmmac: Add dwmac-sun8i")
Reported-by: Belisko Marek
Signed-off-by: Corentin Labbe
---
drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
index 6b75cf2603ff..e62efd166ec8 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
@@ -1214,6 +1214,8 @@ static int sun8i_dwmac_probe(struct platform_device *pdev)
plat_dat->init = sun8i_dwmac_init;
plat_dat->exit = sun8i_dwmac_exit;
plat_dat->setup = sun8i_dwmac_setup;
+ plat_dat->tx_fifo_size = 4096;
+ plat_dat->rx_fifo_size = 16384;
ret = sun8i_dwmac_set_syscon(&pdev->dev, plat_dat);
if (ret)
--
2.26.2
Re: dm9601: incorrect datasheet URL
On Wed, Jun 26, 2019 at 04:12:48PM +0200, Arkadiusz Drabczyk wrote: > http://ptm2.cc.utu.fi/ftp/network/cards/DM9601/From_NET/DM9601-DS-P01-930914.pdf > is gone. In fact, document titled `DM9601-DS-P01-930914.pdf' is > nowhere to be found online these days but there is > http://pdf.datasheet.live/74029349/davicom.com.tw/DM9601E.pdf. I'm > just not sure if this is the same document that the current link was > pointing to and what does E suffix mean. There is also > https://www.alldatasheet.com/datasheet-pdf/pdf/119750/ETC1/DM9601.html > but notice that it says `Version: DM9601-DS-F01' on the bottom of some > pages and `Version: DM9601-DS-P01' on others - I don't know what that > means. > > Should http://pdf.datasheet.live/74029349/davicom.com.tw/DM9601E.pdf > be used as a datasheet URL? > Hello I have noticed the same problem some days ago. The original datasheet could be found using archive.org. I have downloaded all datasheets and none has the same md5, so it need a more detailled inspection. Regards
Re: [PATCH 2/3] ARM: sun8i: sunxi-h3-h5: add phy-is-integrated property to internal PHY
On Fri, Aug 11, 2017 at 08:03:29AM -0700, Florian Fainelli wrote: > On August 11, 2017 6:25:26 AM PDT, Corentin Labbe > wrote: > >On Fri, Aug 11, 2017 at 04:22:11PM +0800, Chen-Yu Tsai wrote: > >> On Fri, Aug 11, 2017 at 4:19 PM, Corentin Labbe > >> wrote: > >> > On Fri, Aug 11, 2017 at 04:11:13PM +0800, Chen-Yu Tsai wrote: > >> >> On Fri, Aug 11, 2017 at 4:05 PM, Corentin Labbe > >> >> wrote: > >> >> > On Fri, Aug 11, 2017 at 10:42:51AM +0800, Chen-Yu Tsai wrote: > >> >> >> Hi, > >> >> >> > >> >> >> On Thu, Aug 10, 2017 at 4:51 PM, Corentin Labbe > >> >> >> wrote: > >> >> >> > This patch add the new phy-is-integrated property to the > >internal PHY > >> >> >> > node. > >> >> >> > > >> >> >> > Signed-off-by: Corentin Labbe > >> >> >> > --- > >> >> >> > arch/arm/boot/dts/sunxi-h3-h5.dtsi | 1 + > >> >> >> > 1 file changed, 1 insertion(+) > >> >> >> > > >> >> >> > diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi > >b/arch/arm/boot/dts/sunxi-h3-h5.dtsi > >> >> >> > index 4b599b5d26f6..54fc24e4c569 100644 > >> >> >> > --- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi > >> >> >> > +++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi > >> >> >> > @@ -425,6 +425,7 @@ > >> >> >> > reg = <1>; > >> >> >> > clocks = <&ccu > >CLK_BUS_EPHY>; > >> >> >> > resets = <&ccu > >RST_BUS_EPHY>; > >> >> >> > + phy-is-integrated; > >> >> >> > >> >> >> You also need to "delete" this property at the board level for > >> >> >> any board that has the external PHY at address <1>. Otherwise > >> >> >> they will stop working. This is due to the internal and > >external > >> >> >> PHYs having the same path and node name in the device tree, so > >> >> >> they are effectively the same node. > >> >> >> > >> >> >> ChenYu > >> >> >> > >> >> > > >> >> > They have not the same name, ext_rgmii_phy vs int_mii_phy. > >> >> > >> >> That is just the label. The label plays no part in device tree > >merging. The path > >> >> > >> >> /soc/ethernet@1c3/mdio/ethernet-phy@1 > >> >> > >> >> is the same. You can look under > >> >> > >> >> /proc/device-tree/soc/ethernet@1c3/mdio > >> >> > >> >> on the OrangePI Plus 2E or any other H3 board that uses an > >> >> external PHY at address 1. > >> >> > >> >> ChenYu > >> > > >> > Since we get the phy node by phy-handle and not by path, I think > >all should be good. > >> > >> You are not getting me. The fact that the two seemingly separate > >> nodes are merged together means, whatever properties you put in > >> the internal PHY node, also affect the external PHY node. Once > >> compiled, they are the SAME node. > > > >Hello Rob, florian, mark > > > >Adding a delete property on all external ethernet-phy@1 is a bit > >overkill, and I dont like the idea that nodes are merged. > > This is not exactly up to you that's just how DTC works. > > >What do you think about other possible solutions: > >- Using integrated-phy@1 for the integrated PHY node name > > That might be okay although you are using now a seemingly non-standard unit > name. > > >- Using a fake address like 31 (see patch below) > > You could also drop the address part in the unit name although we'd probably > get a DTC warning for that. > > I suspect both of your solutions and what I mentioned above will be producing > DTC warnings to some extent... Rob what do you think? > I think I found an easier solution, putting phy-is-integrated on board DT nodes only. I will send an updated serie. Regards
[PATCH v2 6/6] net: stmmac: dwmac-sun8i: choose internal PHY via phy-is-integrated
The current way to find if the phy is internal is to compare DT phy-mode
and emac_variant/internal_phy.
But it will negate a possible future SoC where an external PHY use the
same phy mode than the internal one.
This patch adds a new way to find if the PHY is internal, via
the phy-is-integrated property.
Since the internal_phy variable does not need anymore to contain the xMII mode
used by the internal PHY, it is still used for knowing the presence of an
internal PHY, so it is modified to a boolean soc_has_internal_phy.
Signed-off-by: Corentin Labbe
---
drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c | 16
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
index fffd6d5fc907..672553b652bd 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
@@ -41,14 +41,14 @@
* This value is used for disabling properly EMAC
* and used as a good starting value in case of the
* boot process(uboot) leave some stuff.
- * @internal_phy: Does the MAC embed an internal PHY
+ * @soc_has_internal_phy: Does the MAC embed an internal PHY
* @support_mii: Does the MAC handle MII
* @support_rmii: Does the MAC handle RMII
* @support_rgmii: Does the MAC handle RGMII
*/
struct emac_variant {
u32 default_syscon_value;
- int internal_phy;
+ bool soc_has_internal_phy;
bool support_mii;
bool support_rmii;
bool support_rgmii;
@@ -75,7 +75,7 @@ struct sunxi_priv_data {
static const struct emac_variant emac_variant_h3 = {
.default_syscon_value = 0x58000,
- .internal_phy = PHY_INTERFACE_MODE_MII,
+ .soc_has_internal_phy = true,
.support_mii = true,
.support_rmii = true,
.support_rgmii = true
@@ -83,20 +83,20 @@ static const struct emac_variant emac_variant_h3 = {
static const struct emac_variant emac_variant_v3s = {
.default_syscon_value = 0x38000,
- .internal_phy = PHY_INTERFACE_MODE_MII,
+ .soc_has_internal_phy = true,
.support_mii = true
};
static const struct emac_variant emac_variant_a83t = {
.default_syscon_value = 0,
- .internal_phy = 0,
+ .soc_has_internal_phy = false,
.support_mii = true,
.support_rgmii = true
};
static const struct emac_variant emac_variant_a64 = {
.default_syscon_value = 0,
- .internal_phy = 0,
+ .soc_has_internal_phy = false,
.support_mii = true,
.support_rmii = true,
.support_rgmii = true
@@ -648,7 +648,7 @@ static int sun8i_dwmac_set_syscon(struct stmmac_priv *priv)
"Current syscon value is not the default %x (expect
%x)\n",
val, reg);
- if (gmac->variant->internal_phy) {
+ if (gmac->variant->soc_has_internal_phy) {
if (!gmac->use_internal_phy) {
/* switch to external PHY interface */
reg &= ~H3_EPHY_SELECT;
@@ -932,7 +932,7 @@ static int sun8i_dwmac_probe(struct platform_device *pdev)
}
plat_dat->interface = of_get_phy_mode(dev->of_node);
- if (plat_dat->interface == gmac->variant->internal_phy) {
+ if (of_property_read_bool(plat_dat->phy_node, "phy-is-integrated")) {
dev_info(&pdev->dev, "Will use internal PHY\n");
gmac->use_internal_phy = true;
gmac->ephy_clk = of_clk_get(plat_dat->phy_node, 0);
--
2.13.0
[PATCH v2 5/6] ARM: sun8i: orangepi-one: Set phy-is-integrated to the internal phy node
This patch add the new phy-is-integrated property to the internal PHY node.
Signed-off-by: Corentin Labbe
---
arch/arm/boot/dts/sun8i-h3-orangepi-one.dts | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-one.dts
b/arch/arm/boot/dts/sun8i-h3-orangepi-one.dts
index 6880268e8b87..22c471473909 100644
--- a/arch/arm/boot/dts/sun8i-h3-orangepi-one.dts
+++ b/arch/arm/boot/dts/sun8i-h3-orangepi-one.dts
@@ -105,6 +105,10 @@
status = "okay";
};
+&int_mii_phy {
+ phy-is-integrated;
+};
+
&mmc0 {
pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>;
--
2.13.0
[PATCH v2 4/6] ARM: sun8i: orangepi-2: Set phy-is-integrated to the internal phy node
This patch add the new phy-is-integrated property to the internal PHY node.
Signed-off-by: Corentin Labbe
---
arch/arm/boot/dts/sun8i-h3-orangepi-2.dts | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts
b/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts
index 17cdeae19c6f..0801c808c5e5 100644
--- a/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts
+++ b/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts
@@ -131,6 +131,10 @@
status = "okay";
};
+&int_mii_phy {
+ phy-is-integrated;
+};
+
&mmc0 {
pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>;
--
2.13.0
[PATCH v2 1/6] ARM: sun8i: orangepipc: Set phy-is-integrated to the internal phy node
This patch add the new phy-is-integrated property to the internal PHY
node.
Signed-off-by: Corentin Labbe
---
arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts
b/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts
index f5f0f15a2088..68a618b5f18c 100644
--- a/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts
+++ b/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts
@@ -131,6 +131,10 @@
status = "okay";
};
+&int_mii_phy {
+ phy-is-integrated;
+};
+
&mmc0 {
pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>;
--
2.13.0
[PATCH v2 3/6] ARM: sun8i: nanopi-neo: Set phy-is-integrated to the internal phy node
This patch add the new phy-is-integrated property to the internal PHY node.
Signed-off-by: Corentin Labbe
---
arch/arm/boot/dts/sun8i-h3-nanopi-neo.dts | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-h3-nanopi-neo.dts
b/arch/arm/boot/dts/sun8i-h3-nanopi-neo.dts
index 78f6c24952dd..e77b51c98374 100644
--- a/arch/arm/boot/dts/sun8i-h3-nanopi-neo.dts
+++ b/arch/arm/boot/dts/sun8i-h3-nanopi-neo.dts
@@ -53,3 +53,7 @@
allwinner,leds-active-low;
status = "okay";
};
+
+&int_mii_phy {
+ phy-is-integrated;
+};
--
2.13.0
[PATCH v2 0/6] net: stmmac: Detect PHY location with phy-is-integrated
Hello The current way to find if the phy is internal is to compare DT phy-mode and emac_variant/internal_phy. But it will negate a possible future SoC where an external PHY use the same phy mode than the integrated one. This patchs series adds a new way to find if the PHY is integrated, via the phy-is-integrated DT property. Since it exists both integrated and external ethernet-phy@1, they are merged in the final DTB and so share all properties. For avoiding this, the phy-is-integrated is added only to board DT. The first five patchs should go via the sunxi tree. the last one should go via the net tree. Note that this serie will need backporting the patch "Documentation: net: phy: Add phy-is-integrated binding" which is in net-next Thanks Regards Changes since v1: - Dropped phy-is-integrated documentation patch since another same patch was already merged - Moved phy-is-integrated from SoC dtsi to final board DT. Corentin Labbe (6): ARM: sun8i: orangepipc: Set phy-is-integrated to the internal phy node ARM: sun8i: beelink-x2: Set phy-is-integrated to the internal phy node ARM: sun8i: nanopi-neo: Set phy-is-integrated to the internal phy node ARM: sun8i: orangepi-2: Set phy-is-integrated to the internal phy node ARM: sun8i: orangepi-one: Set phy-is-integrated to the internal phy node net: stmmac: dwmac-sun8i: choose internal PHY via phy-is-integrated arch/arm/boot/dts/sun8i-h3-beelink-x2.dts | 4 arch/arm/boot/dts/sun8i-h3-nanopi-neo.dts | 4 arch/arm/boot/dts/sun8i-h3-orangepi-2.dts | 4 arch/arm/boot/dts/sun8i-h3-orangepi-one.dts | 4 arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts| 4 drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c | 16 6 files changed, 28 insertions(+), 8 deletions(-) -- 2.13.0
[PATCH v2 2/6] ARM: sun8i: beelink-x2: Set phy-is-integrated to the internal phy node
This patch add the new phy-is-integrated property to the internal PHY node.
Signed-off-by: Corentin Labbe
---
arch/arm/boot/dts/sun8i-h3-beelink-x2.dts | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-h3-beelink-x2.dts
b/arch/arm/boot/dts/sun8i-h3-beelink-x2.dts
index 546837ccd8af..d0517240d5e3 100644
--- a/arch/arm/boot/dts/sun8i-h3-beelink-x2.dts
+++ b/arch/arm/boot/dts/sun8i-h3-beelink-x2.dts
@@ -121,6 +121,10 @@
status = "okay";
};
+&int_mii_phy {
+ phy-is-integrated;
+};
+
&mmc0 {
pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>;
--
2.13.0
Re: [PATCH v2 0/6] net: stmmac: Detect PHY location with phy-is-integrated
On Thu, Aug 17, 2017 at 09:51:43AM +0200, Corentin Labbe wrote: > Hello > > The current way to find if the phy is internal is to compare DT phy-mode > and emac_variant/internal_phy. > But it will negate a possible future SoC where an external PHY use the > same phy mode than the integrated one. > > This patchs series adds a new way to find if the PHY is integrated, via > the phy-is-integrated DT property. > > Since it exists both integrated and external ethernet-phy@1, they are merged > in > the final DTB and so share all properties. > For avoiding this, the phy-is-integrated is added only to board DT. > > The first five patchs should go via the sunxi tree. > the last one should go via the net tree. > Note that this serie will need backporting the patch > "Documentation: net: phy: Add phy-is-integrated binding" which is in net-next > > Thanks > Regards > > Changes since v1: > - Dropped phy-is-integrated documentation patch since another same patch was > already merged > - Moved phy-is-integrated from SoC dtsi to final board DT. > > Corentin Labbe (6): > ARM: sun8i: orangepipc: Set phy-is-integrated to the internal phy node > ARM: sun8i: beelink-x2: Set phy-is-integrated to the internal phy node > ARM: sun8i: nanopi-neo: Set phy-is-integrated to the internal phy node > ARM: sun8i: orangepi-2: Set phy-is-integrated to the internal phy node > ARM: sun8i: orangepi-one: Set phy-is-integrated to the internal phy > node > net: stmmac: dwmac-sun8i: choose internal PHY via phy-is-integrated > > arch/arm/boot/dts/sun8i-h3-beelink-x2.dts | 4 > arch/arm/boot/dts/sun8i-h3-nanopi-neo.dts | 4 > arch/arm/boot/dts/sun8i-h3-orangepi-2.dts | 4 > arch/arm/boot/dts/sun8i-h3-orangepi-one.dts | 4 > arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts| 4 > drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c | 16 > 6 files changed, 28 insertions(+), 8 deletions(-) > > -- > 2.13.0 > Hello Self NACK, the comment from Rob on previous series is pertinent. I will send a v3 which use a mdio-mux for solving all problems. Regards
[PATCH v3 4/4] dt-bindings: net: dwmac-sun8i: update documentation about integrated PHY
This patch add documentation about the MDIO switch used on sun8i-h3-emac
for integrated PHY.
Signed-off-by: Corentin Labbe
---
.../devicetree/bindings/net/dwmac-sun8i.txt| 112 +++--
1 file changed, 105 insertions(+), 7 deletions(-)
diff --git a/Documentation/devicetree/bindings/net/dwmac-sun8i.txt
b/Documentation/devicetree/bindings/net/dwmac-sun8i.txt
index 725f3b187886..631084122532 100644
--- a/Documentation/devicetree/bindings/net/dwmac-sun8i.txt
+++ b/Documentation/devicetree/bindings/net/dwmac-sun8i.txt
@@ -39,7 +39,7 @@ Optional properties for the following compatibles:
- allwinner,leds-active-low: EPHY LEDs are active low
Required child node of emac:
-- mdio bus node: should be named mdio
+- mdio bus node: should be named mdio (or mdio_parent in case of H3)
Required properties of the mdio node:
- #address-cells: shall be 1
@@ -48,14 +48,21 @@ Required properties of the mdio node:
The device node referenced by "phy" or "phy-handle" should be a child node
of the mdio node. See phy.txt for the generic PHY bindings.
-Required properties of the phy node with the following compatibles:
+Required mdio-mux nodes for the following compatibles:
+ - "allwinner,sun8i-h3-emac",
+- a mdio-mux node with compatible = "allwinner,sun8i-h3-mdio-switch"
+ - mdio-parent-bus: The parent bus is "mdio_parent"
+ - two child mdio, one for the integrated mdio, one for the external mdio
+
+Required properties of the integrated phy node with the following compatibles:
- "allwinner,sun8i-h3-emac",
- "allwinner,sun8i-v3s-emac":
- clocks: a phandle to the reference clock for the EPHY
- resets: a phandle to the reset control for the EPHY
+- phy-is-integrated
+- Should be a child of the integrated mdio
-Example:
-
+Example with integrated PHY:
emac: ethernet@1c0b000 {
compatible = "allwinner,sun8i-h3-emac";
syscon = <&syscon>;
@@ -75,10 +82,101 @@ emac: ethernet@1c0b000 {
mdio: mdio {
#address-cells = <1>;
#size-cells = <0>;
- int_mii_phy: ethernet-phy@1 {
+ };
+ mdio-mux {
+ compatible = "allwinner,sun8i-h3-mdio-switch";
+ mdio-parent-bus = <&mdio>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ int_mdio: mdio@1 {
+ reg = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ int_mii_phy: ethernet-phy@1 {
+ reg = <1>;
+ clocks = <&ccu CLK_BUS_EPHY>;
+ resets = <&ccu RST_BUS_EPHY>;
+ phy-is-integrated
+ };
+ };
+ ext_mdio: mdio@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+};
+
+Example with external PHY:
+emac: ethernet@1c0b000 {
+ compatible = "allwinner,sun8i-h3-emac";
+ syscon = <&syscon>;
+ reg = <0x01c0b000 0x104>;
+ interrupts = ;
+ interrupt-names = "macirq";
+ resets = <&ccu RST_BUS_EMAC>;
+ reset-names = "stmmaceth";
+ clocks = <&ccu CLK_BUS_EMAC>;
+ clock-names = "stmmaceth";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ phy-handle = <&ext_rgmii_phy>;
+ phy-mode = "rgmii";
+ allwinner,leds-active-low;
+ mdio: mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ mdio-mux {
+ compatible = "allwinner,sun8i-h3-mdio-switch";
+ mdio-parent-bus = <&mdio>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ int_mdio: mdio@1 {
+ reg = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ int_mii_phy: ethernet-phy@1 {
+ reg = <1>;
+ clocks = <&ccu CLK_BUS_EPHY>;
+ resets = <&ccu RST_BUS_EPHY>;
+ phy-is-integrated
+ };
+ };
+ ext_mdio: mdio@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ ext_rgmii_phy: ethernet-phy@1 {
+ reg = <1>;
+ };
+ };
+};
[PATCH v3 2/4] net: stmmac: dwmac-sun8i: choose internal PHY via phy-is-integrated
The current way to find if the phy is internal is to compare DT phy-mode
and emac_variant/internal_phy.
But it will negate a possible future SoC where an external PHY use the
same phy mode than the internal one.
This patch adds a new way to find if the PHY is internal, via
the phy-is-integrated property.
Since the internal_phy variable does not need anymore to contain the xMII mode
used by the internal PHY, it is still used for knowing the presence of an
internal PHY, so it is modified to a boolean soc_has_internal_phy.
Signed-off-by: Corentin Labbe
---
drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c | 16
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
index fffd6d5fc907..672553b652bd 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
@@ -41,14 +41,14 @@
* This value is used for disabling properly EMAC
* and used as a good starting value in case of the
* boot process(uboot) leave some stuff.
- * @internal_phy: Does the MAC embed an internal PHY
+ * @soc_has_internal_phy: Does the MAC embed an internal PHY
* @support_mii: Does the MAC handle MII
* @support_rmii: Does the MAC handle RMII
* @support_rgmii: Does the MAC handle RGMII
*/
struct emac_variant {
u32 default_syscon_value;
- int internal_phy;
+ bool soc_has_internal_phy;
bool support_mii;
bool support_rmii;
bool support_rgmii;
@@ -75,7 +75,7 @@ struct sunxi_priv_data {
static const struct emac_variant emac_variant_h3 = {
.default_syscon_value = 0x58000,
- .internal_phy = PHY_INTERFACE_MODE_MII,
+ .soc_has_internal_phy = true,
.support_mii = true,
.support_rmii = true,
.support_rgmii = true
@@ -83,20 +83,20 @@ static const struct emac_variant emac_variant_h3 = {
static const struct emac_variant emac_variant_v3s = {
.default_syscon_value = 0x38000,
- .internal_phy = PHY_INTERFACE_MODE_MII,
+ .soc_has_internal_phy = true,
.support_mii = true
};
static const struct emac_variant emac_variant_a83t = {
.default_syscon_value = 0,
- .internal_phy = 0,
+ .soc_has_internal_phy = false,
.support_mii = true,
.support_rgmii = true
};
static const struct emac_variant emac_variant_a64 = {
.default_syscon_value = 0,
- .internal_phy = 0,
+ .soc_has_internal_phy = false,
.support_mii = true,
.support_rmii = true,
.support_rgmii = true
@@ -648,7 +648,7 @@ static int sun8i_dwmac_set_syscon(struct stmmac_priv *priv)
"Current syscon value is not the default %x (expect
%x)\n",
val, reg);
- if (gmac->variant->internal_phy) {
+ if (gmac->variant->soc_has_internal_phy) {
if (!gmac->use_internal_phy) {
/* switch to external PHY interface */
reg &= ~H3_EPHY_SELECT;
@@ -932,7 +932,7 @@ static int sun8i_dwmac_probe(struct platform_device *pdev)
}
plat_dat->interface = of_get_phy_mode(dev->of_node);
- if (plat_dat->interface == gmac->variant->internal_phy) {
+ if (of_property_read_bool(plat_dat->phy_node, "phy-is-integrated")) {
dev_info(&pdev->dev, "Will use internal PHY\n");
gmac->use_internal_phy = true;
gmac->ephy_clk = of_clk_get(plat_dat->phy_node, 0);
--
2.13.0
[PATCH v3 3/4] net: stmmac: register parent MDIO node for sun8i-h3-emac
In case of a MDIO switch, the registered MDIO node should be
the parent of the PHY. Otherwise of_phy_connect will fail.
Signed-off-by: Corentin Labbe
---
drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c | 12 ++--
1 file changed, 10 insertions(+), 2 deletions(-)
diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
index a366b3747eeb..ca3cc99d8960 100644
--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
@@ -312,10 +312,12 @@ static int stmmac_dt_phy(struct plat_stmmacenet_data
*plat,
static const struct of_device_id need_mdio_ids[] = {
{ .compatible = "snps,dwc-qos-ethernet-4.10" },
{ .compatible = "allwinner,sun8i-a83t-emac" },
- { .compatible = "allwinner,sun8i-h3-emac" },
{ .compatible = "allwinner,sun8i-v3s-emac" },
{ .compatible = "allwinner,sun50i-a64-emac" },
};
+ static const struct of_device_id need_mdio_mux_ids[] = {
+ { .compatible = "allwinner,sun8i-h3-emac" },
+ };
/* If phy-handle property is passed from DT, use it as the PHY */
plat->phy_node = of_parse_phandle(np, "phy-handle", 0);
@@ -332,7 +334,13 @@ static int stmmac_dt_phy(struct plat_stmmacenet_data *plat,
mdio = false;
}
- if (of_match_node(need_mdio_ids, np)) {
+ /*
+* In case of a MDIO switch/mux, the registered MDIO node should be
+* the parent of the PHY. Otherwise of_phy_connect will fail.
+*/
+ if (of_match_node(need_mdio_mux_ids, np)) {
+plat->mdio_node = of_get_parent(plat->phy_node);
+ } else if (of_match_node(need_mdio_ids, np)) {
plat->mdio_node = of_get_child_by_name(np, "mdio");
} else {
/**
--
2.13.0
[PATCH v3 1/4] ARM: dts: sunxi: h3/h5: represent the mdio switch used by sun8i-h3-emac
Since dwmac-sun8i could use either an integrated PHY or an external PHY
(which could be at same MDIO address), we need to represent this selection
by a MDIO switch.
Signed-off-by: Corentin Labbe
---
arch/arm/boot/dts/sunxi-h3-h5.dtsi | 28 +++-
1 file changed, 23 insertions(+), 5 deletions(-)
diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi
b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
index 4b599b5d26f6..74fdfcc9dfd3 100644
--- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi
+++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
@@ -417,14 +417,32 @@
#size-cells = <0>;
status = "disabled";
- mdio: mdio {
+ mdio_parent: mdio {
#address-cells = <1>;
#size-cells = <0>;
- int_mii_phy: ethernet-phy@1 {
- compatible =
"ethernet-phy-ieee802.3-c22";
+ };
+ mdio-mux {
+ compatible = "allwinner,sun8i-h3-mdio-switch";
+ mdio-parent-bus = <&mdio_parent>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ internal_mdio: mdio@1 {
reg = <1>;
- clocks = <&ccu CLK_BUS_EPHY>;
- resets = <&ccu RST_BUS_EPHY>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ int_mii_phy: ethernet-phy@1 {
+ compatible =
"ethernet-phy-ieee802.3-c22";
+ reg = <1>;
+ clocks = <&ccu CLK_BUS_EPHY>;
+ resets = <&ccu RST_BUS_EPHY>;
+ phy-is-integrated;
+ };
+ };
+ mdio: mdio@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
};
};
};
--
2.13.0
[PATCH v3 0/4] net: stmmac: Detect PHY location with phy-is-integrated
Hello The current way to find if the PHY is internal is to compare DT phy-mode and emac_variant/internal_phy. But it will negate a possible future SoC where an external PHY use the same phy mode than the integrated one. This patchs series adds a new way to find if the PHY is integrated, via the phy-is-integrated DT property. Since it exists both integrated and external ethernet-phy@1, they are merged in the final DTB and so share all properties. For avoiding this, and better represent the reality, we use a MDIO mux. Note that sun8i-v3s-emac have also an integrated PHY, but since it lacks any external PHY support, it is not necessary to add MDIO mux to it. The first patch should go via the sunxi tree. Note that this serie will need backporting the patch "Documentation: net: phy: Add phy-is-integrated binding" which is in net-next Thanks Regards Changes since v2: - Add a MDIO mux for creating distinction between integrated and external MDIO. - phy-is-integrated is not set in dtsi. Changes since v1: - Dropped phy-is-integrated documentation patch since another same patch was already merged - Moved phy-is-integrated from SoC dtsi to final board DT. Corentin Labbe (4): ARM: dts: sunxi: h3/h5: represent the mdio switch used by sun8i-h3-emac net: stmmac: dwmac-sun8i: choose internal PHY via phy-is-integrated net: stmmac: register parent MDIO node for sun8i-h3-emac dt-bindings: net: dwmac-sun8i: update documentation about integrated PHY .../devicetree/bindings/net/dwmac-sun8i.txt| 112 +++-- arch/arm/boot/dts/sunxi-h3-h5.dtsi | 28 +- drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c | 16 +-- .../net/ethernet/stmicro/stmmac/stmmac_platform.c | 12 ++- 4 files changed, 146 insertions(+), 22 deletions(-) -- 2.13.0
Re: [PATCH v3 4/4] dt-bindings: net: dwmac-sun8i: update documentation about integrated PHY
On Sat, Aug 19, 2017 at 12:57:07AM +0800, Chen-Yu Tsai wrote:
> On Fri, Aug 18, 2017 at 8:21 PM, Corentin Labbe
> wrote:
> > This patch add documentation about the MDIO switch used on sun8i-h3-emac
> > for integrated PHY.
> >
> > Signed-off-by: Corentin Labbe
> > ---
> > .../devicetree/bindings/net/dwmac-sun8i.txt| 112
> > +++--
> > 1 file changed, 105 insertions(+), 7 deletions(-)
> >
> > diff --git a/Documentation/devicetree/bindings/net/dwmac-sun8i.txt
> > b/Documentation/devicetree/bindings/net/dwmac-sun8i.txt
> > index 725f3b187886..631084122532 100644
> > --- a/Documentation/devicetree/bindings/net/dwmac-sun8i.txt
> > +++ b/Documentation/devicetree/bindings/net/dwmac-sun8i.txt
> > @@ -39,7 +39,7 @@ Optional properties for the following compatibles:
> > - allwinner,leds-active-low: EPHY LEDs are active low
> >
> > Required child node of emac:
> > -- mdio bus node: should be named mdio
> > +- mdio bus node: should be named mdio (or mdio_parent in case of H3)
>
> The node would still be named "mdio". You are confusing the node name
> with the label. But you don't really need the mdio node for the H3.
> You could say here that it is not needed for the H3. See below.
>
> >
> > Required properties of the mdio node:
> > - #address-cells: shall be 1
> > @@ -48,14 +48,21 @@ Required properties of the mdio node:
> > The device node referenced by "phy" or "phy-handle" should be a child node
> > of the mdio node. See phy.txt for the generic PHY bindings.
> >
> > -Required properties of the phy node with the following compatibles:
> > +Required mdio-mux nodes for the following compatibles:
>
> The following compatibles require an mdio-mux node:
>
> > + - "allwinner,sun8i-h3-emac",
>
> Drop the comma. It's already a list.
>
> > +- a mdio-mux node with compatible = "allwinner,sun8i-h3-mdio-switch"
>
> Required properties for the mdio-mux node:
> - compatible: "allwinner,sun8i-h3-mdio-switch"
>
> > + - mdio-parent-bus: The parent bus is "mdio_parent"
>
> This is optional in the mdio-mux binding. Since you have the mdio-mux under
> the EMAC node, it should be obvious that it is connected to the EMAC. The
> parent phandle is more useful for muxes that are separate from the controller,
> such as an external GPIO-controlled mux. So you could just drop it.
>
> > + - two child mdio, one for the integrated mdio, one for the external mdio
> > +
> > +Required properties of the integrated phy node with the following
> > compatibles:
>
> The following compatibles require a PHY node representing the integrated
> PHY, under the integrated MDIO bus node if an mdio-mux node is used:
>
> >- "allwinner,sun8i-h3-emac",
> >- "allwinner,sun8i-v3s-emac":
>
> Required properties of the integrated PHY node:
>
> > - clocks: a phandle to the reference clock for the EPHY
> > - resets: a phandle to the reset control for the EPHY
> > +- phy-is-integrated
> > +- Should be a child of the integrated mdio
> >
> > -Example:
> > -
> > +Example with integrated PHY:
> > emac: ethernet@1c0b000 {
> > compatible = "allwinner,sun8i-h3-emac";
> > syscon = <&syscon>;
> > @@ -75,10 +82,101 @@ emac: ethernet@1c0b000 {
> > mdio: mdio {
> > #address-cells = <1>;
> > #size-cells = <0>;
> > - int_mii_phy: ethernet-phy@1 {
> > + };
> > + mdio-mux {
>
> Drop the mdio node as mentioned above. And also have spaces between
> blocks to be consistent in styling. It's also easier to read.
>
> > + compatible = "allwinner,sun8i-h3-mdio-switch";
> > + mdio-parent-bus = <&mdio>;
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > +
> > + int_mdio: mdio@1 {
> > + reg = <1>;
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + int_mii_phy: ethernet-phy@1 {
> > + reg = <1>;
> > + clocks = <&ccu CLK_BUS_EPHY>;
> > + resets = <&ccu RST_BUS_EPHY>;
> > + phy-is-integrated
> > + };
> > +
Re: [PATCH v3 3/4] net: stmmac: register parent MDIO node for sun8i-h3-emac
On Sat, Aug 19, 2017 at 01:05:21AM +0800, Chen-Yu Tsai wrote:
> On Fri, Aug 18, 2017 at 8:21 PM, Corentin Labbe
> wrote:
> > In case of a MDIO switch, the registered MDIO node should be
> > the parent of the PHY. Otherwise of_phy_connect will fail.
> >
> > Signed-off-by: Corentin Labbe
> > ---
> > drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c | 12 ++--
> > 1 file changed, 10 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
> > b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
> > index a366b3747eeb..ca3cc99d8960 100644
> > --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
> > +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
> > @@ -312,10 +312,12 @@ static int stmmac_dt_phy(struct plat_stmmacenet_data
> > *plat,
> > static const struct of_device_id need_mdio_ids[] = {
> > { .compatible = "snps,dwc-qos-ethernet-4.10" },
> > { .compatible = "allwinner,sun8i-a83t-emac" },
> > - { .compatible = "allwinner,sun8i-h3-emac" },
> > { .compatible = "allwinner,sun8i-v3s-emac" },
> > { .compatible = "allwinner,sun50i-a64-emac" },
> > };
> > + static const struct of_device_id need_mdio_mux_ids[] = {
> > + { .compatible = "allwinner,sun8i-h3-emac" },
> > + };
> >
> > /* If phy-handle property is passed from DT, use it as the PHY */
> > plat->phy_node = of_parse_phandle(np, "phy-handle", 0);
> > @@ -332,7 +334,13 @@ static int stmmac_dt_phy(struct plat_stmmacenet_data
> > *plat,
> > mdio = false;
> > }
> >
> > - if (of_match_node(need_mdio_ids, np)) {
> > + /*
> > +* In case of a MDIO switch/mux, the registered MDIO node should be
> > +* the parent of the PHY. Otherwise of_phy_connect will fail.
> > +*/
> > + if (of_match_node(need_mdio_mux_ids, np)) {
> > +plat->mdio_node = of_get_parent(plat->phy_node);
>
> Extra space before of_get_parent.
>
> Also this is going to fail horribly if a fixed link is used.
>
Hello
I will add an extra patch for handling fixed-link for both
need_mdio_mux_ids/need_mdio_ids cases.
Thanks
Regards
Re: [PATCH v3 3/4] net: stmmac: register parent MDIO node for sun8i-h3-emac
On Sat, Aug 19, 2017 at 10:38:36PM +0200, Andrew Lunn wrote: > On Sat, Aug 19, 2017 at 08:50:25PM +0200, Corentin Labbe wrote: > > On Sat, Aug 19, 2017 at 01:05:21AM +0800, Chen-Yu Tsai wrote: > > > On Fri, Aug 18, 2017 at 8:21 PM, Corentin Labbe > > > wrote: > > > > In case of a MDIO switch, the registered MDIO node should be > > > > the parent of the PHY. Otherwise of_phy_connect will fail. > > Hi Corentin > > Sorry, I missed this patch series. Looking at patchwork... That's my fault, I forgot to set you in recipient like in last send. > > Can you represent the MDIO mux using > > Documentation/devicetree/bindings/net/mdio-mux-mmioreg.txt > > It would be better if you could reuse existing infrastructure than > invent something new. > I think we cannot use mdio-mux-mmioreg since the register for doing the switch is in middle of the "System Control" and shared with other functions. This is why we use a sycon/regmap for selecting the MDIO. Regards
[WARNING] stmmac: refcount_t: saturated; leaking memory
Hello I got on all my stmmac boards the following warning: [12605.062840] [ cut here ] [12605.062956] WARNING: CPU: 0 PID: 15637 at /linux-next/lib/refcount.c:77 refcount_add_not_zero+0xa8/0xb8 [12605.062972] refcount_t: saturated; leaking memory. [12605.062987] Modules linked in: iptable_filter ip_tables x_tables nfnetlink_log nfnetlink sun8i_ce crypto_engine [12605.063122] CPU: 0 PID: 15637 Comm: kworker/0:1 Not tainted 4.13.0-rc5-next-20170817+ #403 [12605.063136] Hardware name: Allwinner sun8i Family [12605.063161] Workqueue: rpciod rpc_async_schedule [12605.063186] Backtrace: [12605.063222] [] (dump_backtrace) from [] (show_stack+0x18/0x1c) [12605.063241] r7:c0c51700 r6: r5:600d0013 r4:c0c51700 [12605.063262] [] (show_stack) from [] (dump_stack+0xac/0xd8) [12605.063283] [] (dump_stack) from [] (__warn+0xec/0x104) [12605.063304] r10:c064c3c8 r9:c0400ea8 r8:004d r7:0009 r6:c0987468 r5: [12605.063319] r4:ed8cd7b0 r3:00040d00 [12605.063339] [] (__warn) from [] (warn_slowpath_fmt+0x40/0x48) [12605.063359] r9:ee2c5bb8 r8:ebf8e6c0 r7:c064c3c8 r6:ebf8ee40 r5:0a028725 r4:c0987440 [12605.063379] [] (warn_slowpath_fmt) from [] (refcount_add_not_zero+0xa8/0xb8) [12605.063395] r3:c0c5262c r2:c0987440 [12605.063408] r4:0001 [12605.063427] [] (refcount_add_not_zero) from [] (refcount_add+0x10/0x50) [12605.063443] r5:0a028725 r4:ee5f4e80 [12605.063465] [] (refcount_add) from [] (tcp_gso_segment+0x448/0x47c) [12605.063486] [] (tcp_gso_segment) from [] (tcp4_gso_segment+0x4c/0xac) [12605.063506] r10:c08744bc r9:005e r8: r7:0020 r6:4833 r5:006c [12605.063520] r4:ee2c5bb8 [12605.063541] [] (tcp4_gso_segment) from [] (inet_gso_segment+0x1a0/0x330) [12605.063559] r7: r6:184e r5:006c r4:ee2c5bb8 [12605.063582] [] (inet_gso_segment) from [] (skb_mac_gso_segment+0xe8/0x1f4) [12605.063602] r10:ee842850 r9:ee9e8000 r8:c0671e8c r7:ee2c5bb8 r6:0008 r5:0020 [12605.063616] r4:4833 [12605.063638] [] (skb_mac_gso_segment) from [] (__skb_gso_segment+0xd0/0x198) [12605.063657] r8: r7:0020 r6:4833 r5:0001 r4:ee2c5bb8 [12605.063679] [] (__skb_gso_segment) from [] (validate_xmit_skb+0x124/0x2e4) [12605.063698] r9:ee9e8000 r8: r7:0020 r6:4833 r5: r4:ee2c5bb8 [12605.063720] [] (validate_xmit_skb) from [] (validate_xmit_skb_list+0x38/0x68) [12605.063740] r10:ee842850 r9: r8: r7:ee9e8000 r6: r5:ee2c5bb8 [12605.063754] r4: [12605.063777] [] (validate_xmit_skb_list) from [] (sch_direct_xmit+0x154/0x19c) [12605.063797] r9: r8:0001 r7:ee9e8000 r6:ee91d800 r5:ee2c5bb8 r4:ee842800 [12605.063817] [] (sch_direct_xmit) from [] (__dev_queue_xmit+0x614/0x7ec) [12605.063836] r8:013ba711 r7: r6:0bd4 r5:ee842800 r4:0001 [12605.063858] [] (__dev_queue_xmit) from [] (dev_queue_xmit+0x14/0x18) [12605.063877] r10: r9:000e r8:ee2c5bb8 r7:ee84210c r6: r5:ee842144 [12605.063891] r4:ee842000 [12605.063913] [] (dev_queue_xmit) from [] (ip_finish_output2+0x2e8/0x758) [12605.063933] [] (ip_finish_output2) from [] (ip_finish_output+0x238/0x348) [12605.063953] r10:ee9e8000 r9:0001 r8:05dc r7: r6:c0c4a580 r5:ee336580 [12605.063966] r4:ee2c5bb8 [12605.063985] [] (ip_finish_output) from [] (ip_output+0x10c/0x30c) [12605.064005] r10:ee9e8000 r9: r8:3eb6 r7: r6:00291fb3 r5:ee2c5bb8 [12605.064018] r4:ef7b1288 [12605.064037] [] (ip_output) from [] (ip_local_out+0x48/0x84) [12605.064057] r10:ee27f900 r9:00026900 r8:00026900 r7: r6:ee336580 r5:c0c4a580 [12605.064070] r4:ee2c5bb8 [12605.064089] [] (ip_local_out) from [] (ip_queue_xmit+0x1e8/0x634) [12605.064107] r7: r6:ee3368b0 r5:ee336580 r4:ee2c5bb8 [12605.064129] [] (ip_queue_xmit) from [] (tcp_transmit_skb+0x444/0x8e4) [12605.064149] r10: r9:00026900 r8:00026900 r7: r6: r5:ee2c5bb8 [12605.064163] r4:ee336580 [12605.064184] [] (tcp_transmit_skb) from [] (tcp_write_xmit+0x21c/0xfe0) [12605.064204] r9:05a8 r8:0a02817d r7: r6:ee2c5b00 r5:0b50 r4:ee336580 [12605.064225] [] (tcp_write_xmit) from [] (__tcp_push_pending_frames+0x3c/0xa4) [12605.064245] r10:05a8 r9: r8:0f03 r7:0a02817d r6:8000 r5:ee2c5b00 [12605.064259] r4:ee336580 [12605.064280] [] (__tcp_push_pending_frames) from [] (tcp_push+0xcc/0x138) [12605.064294] r4:ee336580 [12605.064314] [] (tcp_push) from [] (do_tcp_sendpages+0x568/0x5b0) [12605.064331] r7:c040 r6:0f03 r5:ee2c5b00 r4:ee336580 [12605.064351] [] (do_tcp_sendpages) from [] (tcp_sendpage_locked+0xac/0xc8) [12605.064371] r10:ed8cddf4 r9:0f03 r8:0f03 r7: r6:0008 r5:eff47880 [12605.064385] r4:ee336580 [12605.064405] [] (tcp_sendpage_locked) from [] (tcp_sendpage+0x44/0x5c) [12605.064423] r7: r6:eff47880 r5:c040 r4:ee336580 [12605.064443] [] (tcp_sendpage) f
Re: [PATCH v3 3/4] net: stmmac: register parent MDIO node for sun8i-h3-emac
On Mon, Aug 21, 2017 at 04:23:21PM +0200, Andrew Lunn wrote:
> > All muxes are mostly always represented the same way afaik, or do you
> > want to simply introduce a new compatible / property?
>
> + mdio-mux {
> + compatible = "allwinner,sun8i-h3-mdio-switch";
> + mdio-parent-bus = <&mdio_parent>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + internal_mdio: mdio@1 {
> reg = <1>;
> - clocks = <&ccu CLK_BUS_EPHY>;
> - resets = <&ccu RST_BUS_EPHY>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + int_mii_phy: ethernet-phy@1 {
> + compatible = "ethernet-phy-ieee802.3-c22";
> + reg = <1>;
> + clocks = <&ccu CLK_BUS_EPHY>;
> + resets = <&ccu RST_BUS_EPHY>;
> + phy-is-integrated;
> + };
> + };
> + mdio: mdio@0 {
> + reg = <0>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> };
>
> Hi Maxim
>
> Anybody who knows the MDIO-mux code/binding, knows that it is a run
> time mux. You swap the mux per MDIO transaction. You can access all
> the PHY and switches on the mux'ed MDIO bus.
>
> However here, it is effectively a boot-time MUX. You cannot change it
> on the fly. What happens when somebody has a phandle to a PHY on the
> internal and a phandle to a phy on the external? Does the driver at
> least return -EINVAL, or -EBUSY? Is there a representation which
> eliminates this possibility?
>
Exactly you can change it on the fly, but you need to reset the MAC for
enabling the new configuration.
The stmmac driver does not handle mdio-mux. It is why I have a patch which
automaticly select parent MDIO node of the PHY node.
For representation we could keep the current. (With a big comment stating that
it is a switch)
We can also add a mdio-switch type node, or add a mdio-switch property to
mdio-mux.
Regards
Re: [PATCH v3 3/4] net: stmmac: register parent MDIO node for sun8i-h3-emac
On Tue, Aug 22, 2017 at 09:40:24AM -0700, Florian Fainelli wrote:
> On 08/22/2017 08:39 AM, Chen-Yu Tsai wrote:
> > On Mon, Aug 21, 2017 at 10:23 PM, Andrew Lunn wrote:
> >>> All muxes are mostly always represented the same way afaik, or do you
> >>> want to simply introduce a new compatible / property?
> >>
> >> + mdio-mux {
> >> + compatible = "allwinner,sun8i-h3-mdio-switch";
> >> + mdio-parent-bus = <&mdio_parent>;
> >> + #address-cells = <1>;
> >> + #size-cells = <0>;
> >> +
> >> + internal_mdio: mdio@1 {
> >> reg = <1>;
> >> - clocks = <&ccu CLK_BUS_EPHY>;
> >> - resets = <&ccu RST_BUS_EPHY>;
> >> + #address-cells = <1>;
> >> + #size-cells = <0>;
> >> + int_mii_phy: ethernet-phy@1 {
> >> + compatible = "ethernet-phy-ieee802.3-c22";
> >> + reg = <1>;
> >> + clocks = <&ccu CLK_BUS_EPHY>;
> >> + resets = <&ccu RST_BUS_EPHY>;
> >> + phy-is-integrated;
> >> + };
> >> + };
> >> + mdio: mdio@0 {
> >> + reg = <0>;
> >> + #address-cells = <1>;
> >> + #size-cells = <0>;
> >> };
> >>
> >> Hi Maxim
> >>
> >> Anybody who knows the MDIO-mux code/binding, knows that it is a run
> >> time mux. You swap the mux per MDIO transaction. You can access all
> >> the PHY and switches on the mux'ed MDIO bus.
> >>
> >> However here, it is effectively a boot-time MUX. You cannot change it
> >> on the fly. What happens when somebody has a phandle to a PHY on the
> >> internal and a phandle to a phy on the external? Does the driver at
> >> least return -EINVAL, or -EBUSY? Is there a representation which
> >> eliminates this possibility?
> >
> > There is only one controller. Either you use the internal PHY, which
> > is then directly coupled (no magnetics needed) to the RJ45 port, or
> > you use an external PHY over MII/RMII/RGMII. You could supposedly
> > have both on a board, and let the user choose one. But why bother
> > with the extra complexity and cost? Either you use the internal PHY
> > at 100M, or an external RGMII PHY for gigabit speeds.
>
> I agree, there is no point in over-engineering any of this. I don't
> think there is actually any MDIO mux per-se in that the MDIO clock and
> data lines are muxed, however there has to be some kind of built-in port
> multiplexer that lets you chose between connecting to the internal PHY
> and any external PHY/MAC, but that is not what a "mdio-mux" node represents.
>
> >
> > So I think what you are saying is either impossible or engineering-wise
> > a very stupid design, like using an external MAC with a discrete PHY
> > connected to the internal MAC's MDIO bus, while using the internal MAC
> > with the internal PHY.
> >
> > Now can we please decide on something? We're a week and a half from
> > the 4.13 release. If mdio-mux is wrong, then we could have two mdio
> > nodes (internal-mdio & external-mdio).
>
> I really don't see a need for a mdio-mux in the first place, just have
> one MDIO controller (current state) sub-node which describes the
> built-in STMMAC MDIO controller and declare the internal PHY as a child
> node (along with 'phy-is-integrated'). If a different configuration is
> used, then just put the external PHY as a child node there.
>
> If fixed-link is required, the mdio node becomes unused anyway.
>
> Works for everyone?
If we put an external PHY with reg=1 as a child of internal MDIO, il will be
merged with internal PHY node and get phy-is-integrated.
Does two MDIO node "internal-mdio" and "mdio" works for you ?
(We keep "mdio" for external MDIO for reducing the number of patchs)
Thanks
Regards
diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi
b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
index 4b599b5d26f6..d5e7cf0d9454 100644
--- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi
+++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
@@ -417,7 +417,8 @@
#size-cells = <0>;
status = "disabled";
- mdio: mdio {
+ /* Only one MDIO is usable at the time */
+ internal_mdio: mdio@1 {
#address-cells = <1>;
#size-cells = <0>;
int_mii_phy: ethernet-phy@1 {
@@ -425,8 +426,13 @@
reg = <1>;
clocks = <&ccu CLK_BUS_EPHY>;
resets = <&ccu RST_BUS_EPHY>;
+ phy-is-integrated;
};
};
+
Re: [PATCH v3 3/4] net: stmmac: register parent MDIO node for sun8i-h3-emac
On Tue, Aug 22, 2017 at 11:35:01AM -0700, Florian Fainelli wrote:
> On 08/22/2017 11:11 AM, Corentin Labbe wrote:
> > On Tue, Aug 22, 2017 at 09:40:24AM -0700, Florian Fainelli wrote:
> >> On 08/22/2017 08:39 AM, Chen-Yu Tsai wrote:
> >>> On Mon, Aug 21, 2017 at 10:23 PM, Andrew Lunn wrote:
> >>>>> All muxes are mostly always represented the same way afaik, or do you
> >>>>> want to simply introduce a new compatible / property?
> >>>>
> >>>> + mdio-mux {
> >>>> + compatible = "allwinner,sun8i-h3-mdio-switch";
> >>>> + mdio-parent-bus = <&mdio_parent>;
> >>>> + #address-cells = <1>;
> >>>> + #size-cells = <0>;
> >>>> +
> >>>> + internal_mdio: mdio@1 {
> >>>> reg = <1>;
> >>>> - clocks = <&ccu CLK_BUS_EPHY>;
> >>>> - resets = <&ccu RST_BUS_EPHY>;
> >>>> + #address-cells = <1>;
> >>>> + #size-cells = <0>;
> >>>> + int_mii_phy: ethernet-phy@1 {
> >>>> + compatible =
> >>>> "ethernet-phy-ieee802.3-c22";
> >>>> + reg = <1>;
> >>>> + clocks = <&ccu CLK_BUS_EPHY>;
> >>>> + resets = <&ccu RST_BUS_EPHY>;
> >>>> + phy-is-integrated;
> >>>> + };
> >>>> + };
> >>>> + mdio: mdio@0 {
> >>>> + reg = <0>;
> >>>> + #address-cells = <1>;
> >>>> + #size-cells = <0>;
> >>>> };
> >>>>
> >>>> Hi Maxim
> >>>>
> >>>> Anybody who knows the MDIO-mux code/binding, knows that it is a run
> >>>> time mux. You swap the mux per MDIO transaction. You can access all
> >>>> the PHY and switches on the mux'ed MDIO bus.
> >>>>
> >>>> However here, it is effectively a boot-time MUX. You cannot change it
> >>>> on the fly. What happens when somebody has a phandle to a PHY on the
> >>>> internal and a phandle to a phy on the external? Does the driver at
> >>>> least return -EINVAL, or -EBUSY? Is there a representation which
> >>>> eliminates this possibility?
> >>>
> >>> There is only one controller. Either you use the internal PHY, which
> >>> is then directly coupled (no magnetics needed) to the RJ45 port, or
> >>> you use an external PHY over MII/RMII/RGMII. You could supposedly
> >>> have both on a board, and let the user choose one. But why bother
> >>> with the extra complexity and cost? Either you use the internal PHY
> >>> at 100M, or an external RGMII PHY for gigabit speeds.
> >>
> >> I agree, there is no point in over-engineering any of this. I don't
> >> think there is actually any MDIO mux per-se in that the MDIO clock and
> >> data lines are muxed, however there has to be some kind of built-in port
> >> multiplexer that lets you chose between connecting to the internal PHY
> >> and any external PHY/MAC, but that is not what a "mdio-mux" node
> >> represents.
> >>
> >>>
> >>> So I think what you are saying is either impossible or engineering-wise
> >>> a very stupid design, like using an external MAC with a discrete PHY
> >>> connected to the internal MAC's MDIO bus, while using the internal MAC
> >>> with the internal PHY.
> >>>
> >>> Now can we please decide on something? We're a week and a half from
> >>> the 4.13 release. If mdio-mux is wrong, then we could have two mdio
> >>> nodes (internal-mdio & external-mdio).
> >>
> >> I really don't see a need for a mdio-mux in the first place, just have
> >> one MDIO controller (current state) sub-node which describes the
> >> built-in STMMAC MDIO controller and declare the internal PHY as a child
> >> node (along with 'phy-is-integrated'). If a different configuration is
> >> use
Re: [PATCH v3 3/4] net: stmmac: register parent MDIO node for sun8i-h3-emac
On Wed, Aug 23, 2017 at 09:31:53AM -0700, Florian Fainelli wrote:
> On 08/23/2017 12:49 AM, Maxime Ripard wrote:
> > Hi Florian,
> >
> > On Tue, Aug 22, 2017 at 11:35:01AM -0700, Florian Fainelli wrote:
> > So I think what you are saying is either impossible or engineering-wise
> > a very stupid design, like using an external MAC with a discrete PHY
> > connected to the internal MAC's MDIO bus, while using the internal MAC
> > with the internal PHY.
> >
> > Now can we please decide on something? We're a week and a half from
> > the 4.13 release. If mdio-mux is wrong, then we could have two mdio
> > nodes (internal-mdio & external-mdio).
>
> I really don't see a need for a mdio-mux in the first place, just have
> one MDIO controller (current state) sub-node which describes the
> built-in STMMAC MDIO controller and declare the internal PHY as a child
> node (along with 'phy-is-integrated'). If a different configuration is
> used, then just put the external PHY as a child node there.
>
> If fixed-link is required, the mdio node becomes unused anyway.
>
> Works for everyone?
> >>>
> >>> If we put an external PHY with reg=1 as a child of internal MDIO,
> >>> il will be merged with internal PHY node and get
> >>> phy-is-integrated.
> >>
> >> Then have the .dtsi file contain just the mdio node, but no internal or
> >> external PHY and push all the internal and external PHY node definition
> >> (in its entirety) to the per-board DTS file, does not that work?
> >
> > If possible, I'd really like to have the internal PHY in the
> > DTSI. It's always there in hardware anyway, and duplicating the PHY,
> > with its clock, reset line, and whatever info we might need in the
> > future in each and every board DTS that uses it will be very error
> > prone and we will have the usual bunch of issues that come up with
> > duplication.
>
> OK, then what if you put the internal PHY in the DTSI, mark it with a
> status = "disabled" property, and have the per-board DTS put a status =
> "okay" property along with a "phy-is-integrated" boolean property? Would
> that work?
No, I tested and for example with sun8i-h3-orangepi-plus.dts, the external PHY
(ethernet-phy@1) is still merged.
So that adding a 'status = "disabled"' does not bring anything.
>
> What I really don't think is necessary is:
>
> - duplicating the "mdio" controller node for external vs. internal PHY,
> because this is not accurate, there is just one MDIO controller, but
> there may be different kinds of MDIO/PHY devices attached
For me, if we want to represent the reality, we need two MDIO:
- since two PHY at the same address could co-exists
- since they are isolated so not on the same MDIO bus
> - having the STMMAC driver MDIO probing code having to deal with a
> "mdio" sub-node or an "internal-mdio" sub-node because this is confusing
> and requiring more driver-level changes that are error prone
My patch for stmmac is really small, only the name of my variable
("need_mdio_mux_ids")
have to be changed to something like "register_parent_mdio"
So I agree with Maxime, we need to avoid merging PHY nodes, and we can avoid it
only by having two separate MDIO nodes.
Furthermore, with only one MDIO, we will face with lots of small patch for
adding phy-is-integrated, with two we do not need to change any board DT, all
is simply clean.
Really having two MDIO seems cleaner.
Regards
Re: [PATCH v3 3/4] net: stmmac: register parent MDIO node for sun8i-h3-emac
On Thu, Aug 24, 2017 at 10:21:24AM +0200, Corentin Labbe wrote:
> On Wed, Aug 23, 2017 at 09:31:53AM -0700, Florian Fainelli wrote:
> > On 08/23/2017 12:49 AM, Maxime Ripard wrote:
> > > Hi Florian,
> > >
> > > On Tue, Aug 22, 2017 at 11:35:01AM -0700, Florian Fainelli wrote:
> > >>>>> So I think what you are saying is either impossible or
> > >>>>> engineering-wise
> > >>>>> a very stupid design, like using an external MAC with a discrete PHY
> > >>>>> connected to the internal MAC's MDIO bus, while using the internal MAC
> > >>>>> with the internal PHY.
> > >>>>>
> > >>>>> Now can we please decide on something? We're a week and a half from
> > >>>>> the 4.13 release. If mdio-mux is wrong, then we could have two mdio
> > >>>>> nodes (internal-mdio & external-mdio).
> > >>>>
> > >>>> I really don't see a need for a mdio-mux in the first place, just have
> > >>>> one MDIO controller (current state) sub-node which describes the
> > >>>> built-in STMMAC MDIO controller and declare the internal PHY as a child
> > >>>> node (along with 'phy-is-integrated'). If a different configuration is
> > >>>> used, then just put the external PHY as a child node there.
> > >>>>
> > >>>> If fixed-link is required, the mdio node becomes unused anyway.
> > >>>>
> > >>>> Works for everyone?
> > >>>
> > >>> If we put an external PHY with reg=1 as a child of internal MDIO,
> > >>> il will be merged with internal PHY node and get
> > >>> phy-is-integrated.
> > >>
> > >> Then have the .dtsi file contain just the mdio node, but no internal or
> > >> external PHY and push all the internal and external PHY node definition
> > >> (in its entirety) to the per-board DTS file, does not that work?
> > >
> > > If possible, I'd really like to have the internal PHY in the
> > > DTSI. It's always there in hardware anyway, and duplicating the PHY,
> > > with its clock, reset line, and whatever info we might need in the
> > > future in each and every board DTS that uses it will be very error
> > > prone and we will have the usual bunch of issues that come up with
> > > duplication.
> >
> > OK, then what if you put the internal PHY in the DTSI, mark it with a
> > status = "disabled" property, and have the per-board DTS put a status =
> > "okay" property along with a "phy-is-integrated" boolean property? Would
> > that work?
>
> No, I tested and for example with sun8i-h3-orangepi-plus.dts, the external
> PHY (ethernet-phy@1) is still merged.
> So that adding a 'status = "disabled"' does not bring anything.
>
> >
> > What I really don't think is necessary is:
> >
> > - duplicating the "mdio" controller node for external vs. internal PHY,
> > because this is not accurate, there is just one MDIO controller, but
> > there may be different kinds of MDIO/PHY devices attached
>
> For me, if we want to represent the reality, we need two MDIO:
> - since two PHY at the same address could co-exists
> - since they are isolated so not on the same MDIO bus
>
> > - having the STMMAC driver MDIO probing code having to deal with a
> > "mdio" sub-node or an "internal-mdio" sub-node because this is confusing
> > and requiring more driver-level changes that are error prone
>
> My patch for stmmac is really small, only the name of my variable
> ("need_mdio_mux_ids")
> have to be changed to something like "register_parent_mdio"
>
>
> So I agree with Maxime, we need to avoid merging PHY nodes, and we can avoid
> it only by having two separate MDIO nodes.
> Furthermore, with only one MDIO, we will face with lots of small patch for
> adding phy-is-integrated, with two we do not need to change any board DT, all
> is simply clean.
> Really having two MDIO seems cleaner.
>
Hello
I have speaked with Neil Amstrong, and he said that they get the same problem
on amlogic.
They use a mdio-mux-mmioreg, (see eth-phy-mux in
arch/arm64/boot/dts/amlogic/meson-gxl.dtsi)
So tomorow, i will send a patch series which do the same with the exception
that we need a mdio-mux-syscon (which is easy/simple to do).
Since their setup use stmmac, it means that we will need 0 changes on stmmac.
Regards
[PATCH] net: stmmac: dwmac-sun8i: Use reset exclusive
The current dwmac_sun8i module cannot be rmmod/modprobe due to that
the reset controller was not released when removed.
This patch remove ambiguity, by using of_reset_control_get_exclusive and
add the missing reset_control_put().
Signed-off-by: Corentin Labbe
---
drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
index fffd6d5fc907..675a09629d85 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
@@ -782,6 +782,7 @@ static int sun8i_dwmac_unpower_internal_phy(struct
sunxi_priv_data *gmac)
clk_disable_unprepare(gmac->ephy_clk);
reset_control_assert(gmac->rst_ephy);
+ reset_control_put(gmac->rst_ephy);
return 0;
}
@@ -942,7 +943,7 @@ static int sun8i_dwmac_probe(struct platform_device *pdev)
return -EINVAL;
}
- gmac->rst_ephy = of_reset_control_get(plat_dat->phy_node, NULL);
+ gmac->rst_ephy =
of_reset_control_get_exclusive(plat_dat->phy_node, NULL);
if (IS_ERR(gmac->rst_ephy)) {
ret = PTR_ERR(gmac->rst_ephy);
if (ret == -EPROBE_DEFER)
--
2.13.5
[PATCH] net: stmmac: Handle possible fixed-link with need_mdio_ids
In case of fixed link, there are no mdio node.
This patch add a test for fixed-link for bypassing MDIO node register.
Signed-off-by: Corentin Labbe
---
drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
index a366b3747eeb..e1be5735365b 100644
--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
@@ -332,7 +332,7 @@ static int stmmac_dt_phy(struct plat_stmmacenet_data *plat,
mdio = false;
}
- if (of_match_node(need_mdio_ids, np)) {
+ if (of_match_node(need_mdio_ids, np) && !of_phy_is_fixed_link(np)) {
plat->mdio_node = of_get_child_by_name(np, "mdio");
} else {
/**
--
2.13.5
Re: [PATCH] net: stmmac: dwmac-sun8i: Use reset exclusive
On Fri, Aug 25, 2017 at 04:48:32PM +0200, Maxime Ripard wrote: > On Fri, Aug 25, 2017 at 04:38:05PM +0200, Corentin Labbe wrote: > > The current dwmac_sun8i module cannot be rmmod/modprobe due to that > > the reset controller was not released when removed. > > > > This patch remove ambiguity, by using of_reset_control_get_exclusive and > > add the missing reset_control_put(). > > > > Signed-off-by: Corentin Labbe > > --- > > drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c | 3 ++- > > 1 file changed, 2 insertions(+), 1 deletion(-) > > > > diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c > > b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c > > index fffd6d5fc907..675a09629d85 100644 > > --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c > > +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c > > @@ -782,6 +782,7 @@ static int sun8i_dwmac_unpower_internal_phy(struct > > sunxi_priv_data *gmac) > > > > clk_disable_unprepare(gmac->ephy_clk); > > reset_control_assert(gmac->rst_ephy); > > + reset_control_put(gmac->rst_ephy); > > return 0; > > } > > > > @@ -942,7 +943,7 @@ static int sun8i_dwmac_probe(struct platform_device > > *pdev) > > return -EINVAL; > > } > > > > - gmac->rst_ephy = of_reset_control_get(plat_dat->phy_node, NULL); > > + gmac->rst_ephy = > > of_reset_control_get_exclusive(plat_dat->phy_node, NULL); > > Why not just use devm_reset_control_get? > Because there no devm_ functions with of_ Regards
Re: [PATCH] net: stmmac: Handle possible fixed-link with need_mdio_ids
On Fri, Aug 25, 2017 at 09:45:23AM -0700, Florian Fainelli wrote:
> On 08/25/2017 09:28 AM, Andrew Lunn wrote:
> > On Fri, Aug 25, 2017 at 04:42:08PM +0200, Corentin Labbe wrote:
> >> In case of fixed link, there are no mdio node.
> >> This patch add a test for fixed-link for bypassing MDIO node register.
> >
> > The two are not mutually exclusive. E.g.
> > vf610-zii-dev.dtsi/vf610-zii-dev-rev-b.dts. It has a fixed-link on
> > the FEC ethernet controller, and an Ethernet switch on the MDIO bus.
> >
> > If anybody ever wants to use a switch with the stmmac, this will be
> > required.
>
> This is already done in the Lamobo R1 DTS file so it would be nice not
> to break this use case:
>
> &gmac {
> pinctrl-names = "default";
> pinctrl-0 = <&gmac_pins_rgmii_a>;
> phy-mode = "rgmii";
> phy-supply = <®_gmac_3v3>;
> status = "okay";
>
> fixed-link {
> speed = <1000>;
> full-duplex;
> };
>
> mdio {
> compatible = "snps,dwmac-mdio";
> #address-cells = <1>;
> #size-cells = <0>;
>
> switch: ethernet-switch@1e {
> compatible = "brcm,bcm53125";
> reg = <30>;
> #address-cells = <1>;
> #size-cells = <0>;
>
>
> >
> > Andrew
> >
>
Sorry, I have made a bad commit message.
This commit only change behaviour for nodes that match need_mdio_ids.
The behaviour for snps,dwmac-mdio does not change as it is handled in follow up
of the "ifthenelse"
I will resent it with correct commit message.
Regards
[PATCH v4 3/5] dt-bindings: net: dwmac-sun8i: update documentation about integrated PHY
This patch add documentation about the MDIO switch used on sun8i-h3-emac
for integrated PHY.
Signed-off-by: Corentin Labbe
---
.../devicetree/bindings/net/dwmac-sun8i.txt| 117 -
1 file changed, 112 insertions(+), 5 deletions(-)
diff --git a/Documentation/devicetree/bindings/net/dwmac-sun8i.txt
b/Documentation/devicetree/bindings/net/dwmac-sun8i.txt
index 725f3b187886..5751f7afc5dd 100644
--- a/Documentation/devicetree/bindings/net/dwmac-sun8i.txt
+++ b/Documentation/devicetree/bindings/net/dwmac-sun8i.txt
@@ -39,7 +39,7 @@ Optional properties for the following compatibles:
- allwinner,leds-active-low: EPHY LEDs are active low
Required child node of emac:
-- mdio bus node: should be named mdio
+- mdio bus node: should be labelled mdio
Required properties of the mdio node:
- #address-cells: shall be 1
@@ -48,14 +48,25 @@ Required properties of the mdio node:
The device node referenced by "phy" or "phy-handle" should be a child node
of the mdio node. See phy.txt for the generic PHY bindings.
-Required properties of the phy node with the following compatibles:
+The following compatibles require an mdio-mux node:
+ - "allwinner,sun8i-h3-emac"
+Required properties for the mdio-mux node:
+ - compatible = "mdio-mux"
+ - two child mdio, one for the integrated mdio, one for the external mdio
+ - mdio-parent-bus: a phandle to the emac's MDIO node
+
+The following compatibles require a PHY node representing the integrated
+PHY, under the integrated MDIO bus node if an mdio-mux node is used:
- "allwinner,sun8i-h3-emac",
- "allwinner,sun8i-v3s-emac":
+
+Required properties of the integrated phy node:
- clocks: a phandle to the reference clock for the EPHY
- resets: a phandle to the reset control for the EPHY
+- phy-is-integrated
+- Should be a child of the integrated mdio
-Example:
-
+Example with integrated PHY:
emac: ethernet@1c0b000 {
compatible = "allwinner,sun8i-h3-emac";
syscon = <&syscon>;
@@ -72,13 +83,109 @@ emac: ethernet@1c0b000 {
phy-handle = <&int_mii_phy>;
phy-mode = "mii";
allwinner,leds-active-low;
- mdio: mdio {
+
+ mdio0: mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "snps,dwmac-mdio";
+ };
+
+};
+eth-phy-mux {
+ compatible = "mdio-mux";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ mdio-parent-bus = <&mdio0>;
+
+ int_mdio: mdio@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ int_mii_phy: ethernet-phy@1 {
+ reg = <1>;
+ clocks = <&ccu CLK_BUS_EPHY>;
+ resets = <&ccu RST_BUS_EPHY>;
+ phy-is-integrated
+ };
+ };
+ ext_mdio: mdio@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+};
+
+Example with external PHY:
+emac: ethernet@1c0b000 {
+ compatible = "allwinner,sun8i-h3-emac";
+ syscon = <&syscon>;
+ reg = <0x01c0b000 0x104>;
+ interrupts = ;
+ interrupt-names = "macirq";
+ resets = <&ccu RST_BUS_EMAC>;
+ reset-names = "stmmaceth";
+ clocks = <&ccu CLK_BUS_EMAC>;
+ clock-names = "stmmaceth";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ phy-handle = <&ext_rgmii_phy>;
+ phy-mode = "rgmii";
+ allwinner,leds-active-low;
+
+ mdio0: mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "snps,dwmac-mdio";
+ };
+
+};
+eth-phy-mux {
+ compatible = "mdio-mux";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ mdio-parent-bus = <&mdio0>;
+
+ int_mdio: mdio@1 {
#address-cells = <1>;
#size-cells = <0>;
int_mii_phy: ethernet-phy@1 {
reg = <1>;
clocks = <&ccu CLK_BUS_EPHY>;
resets = <&ccu RST_BUS_EPHY>;
+ phy-is-integrated
+ };
+ };
+ ext_mdio: mdio@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ ext_rgmii_phy: ethernet-phy@1 {
+ reg = <1>;
+ };
+ };
+};
+
+Example with SoC without integrated PHY
+
+emac: ethernet@1c0b000 {
+ compatible = "allwinner,sun8i-a83t-emac";
+ syscon = <&syscon>;
+ reg = <0x01c0b000 0x104>;
+
[PATCH v4 5/5] net: stmmac: Register parent MDIO in case of fake mdio-mux
In case of a fake MDIO switch/mux (like Allwinner H3),
the registered MDIO node should be the parent of the PHY.
Otherwise of_phy_connect will fail.
Signed-off-by: Corentin Labbe
---
drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c | 13 +++--
1 file changed, 11 insertions(+), 2 deletions(-)
diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
index e1be5735365b..4d5f3cc82476 100644
--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
@@ -312,10 +312,12 @@ static int stmmac_dt_phy(struct plat_stmmacenet_data
*plat,
static const struct of_device_id need_mdio_ids[] = {
{ .compatible = "snps,dwc-qos-ethernet-4.10" },
{ .compatible = "allwinner,sun8i-a83t-emac" },
- { .compatible = "allwinner,sun8i-h3-emac" },
{ .compatible = "allwinner,sun8i-v3s-emac" },
{ .compatible = "allwinner,sun50i-a64-emac" },
};
+ static const struct of_device_id register_parent_mdio_ids[] = {
+ { .compatible = "allwinner,sun8i-h3-emac" },
+ };
/* If phy-handle property is passed from DT, use it as the PHY */
plat->phy_node = of_parse_phandle(np, "phy-handle", 0);
@@ -332,7 +334,14 @@ static int stmmac_dt_phy(struct plat_stmmacenet_data *plat,
mdio = false;
}
- if (of_match_node(need_mdio_ids, np) && !of_phy_is_fixed_link(np)) {
+ /*
+* In case of a fake MDIO switch/mux (like Allwinner H3),
+* the registered MDIO node should be the parent of the PHY.
+* Otherwise of_phy_connect will fail.
+*/
+ if (of_match_node(register_parent_mdio_ids, np) &&
!of_phy_is_fixed_link(np)) {
+ plat->mdio_node = of_get_parent(plat->phy_node);
+ } else if (of_match_node(need_mdio_ids, np) &&
!of_phy_is_fixed_link(np)) {
plat->mdio_node = of_get_child_by_name(np, "mdio");
} else {
/**
--
2.13.5
[PATCH v4 0/5] net: stmmac: Detect PHY location with phy-is-integrated
Hello The current way to find if the PHY is internal is to compare DT phy-mode and emac_variant/internal_phy. But it will negate a possible future SoC where an external PHY use the same phy mode than the integrated one. This patchs series adds a new way to find if the PHY is integrated, via the phy-is-integrated DT property. Since it exists both integrated and external ethernet-phy@1, they are merged in the final DTB and so share all properties. For avoiding this, and better represent the reality, we use a MDIO mux. The first try was to create a new MDIO mux "mdio-mux-syscon". mdio-mux-syscon working the same way than mdio-mux-mmioreg with the exception that the register is used via syscon/regmap. But this solution does not work for two reason: - changing the MDIO selection need the reset of MAC which cannot be done by the mdio-mux-syscon driver - There were driver loading order problem: - mdio-mux-syscon needing that stmmac register the parent MDIO - stmmac needing that child MDIO was registered just after registering parent MDIO So we cannot use any external MDIO-mux. The final solution was to represent a mdio-mux but let the MAC handle all things. The only hack that comes with this solution is that we add a patch "net: stmmac: Register parent MDIO in case of fake mdio-mux" because we have ino other way to know which MDIO node to register. Note that sun8i-v3s-emac have also an integrated PHY, but since it lacks any external PHY support it is not necessary to add MDIO mux to it. All patchs should go via the net tree with exception of DT patchs which should go via the sunxi tree Note that this serie will need backporting the patch "Documentation: net: phy: Add phy-is-integrated binding" which is in net-next Regards Changes since v3: - Added a patch for handling fixed-link - Updated documentation Changes since v2: - Add a MDIO mux for creating distinction between integrated and external MDIO. - phy-is-integrated is not set in dtsi. Changes since v1: - Dropped phy-is-integrated documentation patch since another same patch was already merged - Moved phy-is-integrated from SoC dtsi to final board DT. Corentin Labbe (5): net: stmmac: Handle possible fixed-link with need_mdio_ids ARM: dts: sunxi: h3/h5: represent the mdio switch used by sun8i-h3-emac dt-bindings: net: dwmac-sun8i: update documentation about integrated PHY net: stmmac: dwmac-sun8i: choose internal PHY via phy-is-integrated net: stmmac: Register parent MDIO in case of fake mdio-mux .../devicetree/bindings/net/dwmac-sun8i.txt| 117 - arch/arm/boot/dts/sunxi-h3-h5.dtsi | 22 +++- drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c | 16 +-- .../net/ethernet/stmicro/stmmac/stmmac_platform.c | 13 ++- 4 files changed, 152 insertions(+), 16 deletions(-) -- 2.13.5
[PATCH v4 4/5] net: stmmac: dwmac-sun8i: choose internal PHY via phy-is-integrated
The current way to find if the phy is internal is to compare DT phy-mode
and emac_variant/internal_phy.
But it will negate a possible future SoC where an external PHY use the
same phy mode than the internal one.
This patch adds a new way to find if the PHY is internal, via
the phy-is-integrated property.
Since the internal_phy variable does not need anymore to contain the xMII mode
used by the internal PHY, it is still used for knowing the presence of an
internal PHY, so it is modified to a boolean soc_has_internal_phy.
Signed-off-by: Corentin Labbe
Acked-by: Chen-Yu Tsai
Reviewed-by: Florian Fainelli
---
drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c | 16
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
index 675a09629d85..c353e5bcb3c1 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
@@ -41,14 +41,14 @@
* This value is used for disabling properly EMAC
* and used as a good starting value in case of the
* boot process(uboot) leave some stuff.
- * @internal_phy: Does the MAC embed an internal PHY
+ * @soc_has_internal_phy: Does the MAC embed an internal PHY
* @support_mii: Does the MAC handle MII
* @support_rmii: Does the MAC handle RMII
* @support_rgmii: Does the MAC handle RGMII
*/
struct emac_variant {
u32 default_syscon_value;
- int internal_phy;
+ bool soc_has_internal_phy;
bool support_mii;
bool support_rmii;
bool support_rgmii;
@@ -75,7 +75,7 @@ struct sunxi_priv_data {
static const struct emac_variant emac_variant_h3 = {
.default_syscon_value = 0x58000,
- .internal_phy = PHY_INTERFACE_MODE_MII,
+ .soc_has_internal_phy = true,
.support_mii = true,
.support_rmii = true,
.support_rgmii = true
@@ -83,20 +83,20 @@ static const struct emac_variant emac_variant_h3 = {
static const struct emac_variant emac_variant_v3s = {
.default_syscon_value = 0x38000,
- .internal_phy = PHY_INTERFACE_MODE_MII,
+ .soc_has_internal_phy = true,
.support_mii = true
};
static const struct emac_variant emac_variant_a83t = {
.default_syscon_value = 0,
- .internal_phy = 0,
+ .soc_has_internal_phy = false,
.support_mii = true,
.support_rgmii = true
};
static const struct emac_variant emac_variant_a64 = {
.default_syscon_value = 0,
- .internal_phy = 0,
+ .soc_has_internal_phy = false,
.support_mii = true,
.support_rmii = true,
.support_rgmii = true
@@ -648,7 +648,7 @@ static int sun8i_dwmac_set_syscon(struct stmmac_priv *priv)
"Current syscon value is not the default %x (expect
%x)\n",
val, reg);
- if (gmac->variant->internal_phy) {
+ if (gmac->variant->soc_has_internal_phy) {
if (!gmac->use_internal_phy) {
/* switch to external PHY interface */
reg &= ~H3_EPHY_SELECT;
@@ -933,7 +933,7 @@ static int sun8i_dwmac_probe(struct platform_device *pdev)
}
plat_dat->interface = of_get_phy_mode(dev->of_node);
- if (plat_dat->interface == gmac->variant->internal_phy) {
+ if (of_property_read_bool(plat_dat->phy_node, "phy-is-integrated")) {
dev_info(&pdev->dev, "Will use internal PHY\n");
gmac->use_internal_phy = true;
gmac->ephy_clk = of_clk_get(plat_dat->phy_node, 0);
--
2.13.5
[PATCH v4 2/5] ARM: dts: sunxi: h3/h5: represent the mdio switch used by sun8i-h3-emac
Since dwmac-sun8i could use either an integrated PHY or an external PHY
(which could be at same MDIO address), we need to represent this selection
by a MDIO switch.
Signed-off-by: Corentin Labbe
---
arch/arm/boot/dts/sunxi-h3-h5.dtsi | 22 +-
1 file changed, 21 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi
b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
index 4b599b5d26f6..5ffb940a44bb 100644
--- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi
+++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
@@ -417,7 +417,22 @@
#size-cells = <0>;
status = "disabled";
- mdio: mdio {
+ mdio0: mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "snps,dwmac-mdio";
+ };
+
+ };
+
+ eth-phy-mux {
+ compatible = "mdio-mux";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ mdio-parent-bus = <&mdio0>;
+
+ /* Only one MDIO is usable at the time */
+ internal_mdio: mdio@1 {
#address-cells = <1>;
#size-cells = <0>;
int_mii_phy: ethernet-phy@1 {
@@ -425,8 +440,13 @@
reg = <1>;
clocks = <&ccu CLK_BUS_EPHY>;
resets = <&ccu RST_BUS_EPHY>;
+ phy-is-integrated;
};
};
+ mdio: mdio@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
};
spi0: spi@01c68000 {
--
2.13.5
[PATCH v4 1/5] net: stmmac: Handle possible fixed-link with need_mdio_ids
In case of fixed link, there are no mdio node.
This patch add a test for fixed-link for bypassing MDIO node register
that match need_mdio_ids.
Note that this do not change behaviour for MDIO snps,dwmac-mdio nodes.
Signed-off-by: Corentin Labbe
---
drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
index a366b3747eeb..e1be5735365b 100644
--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
@@ -332,7 +332,7 @@ static int stmmac_dt_phy(struct plat_stmmacenet_data *plat,
mdio = false;
}
- if (of_match_node(need_mdio_ids, np)) {
+ if (of_match_node(need_mdio_ids, np) && !of_phy_is_fixed_link(np)) {
plat->mdio_node = of_get_child_by_name(np, "mdio");
} else {
/**
--
2.13.5
[PATCH] net: ethernet: stmmac: dwmac-sun8i: enable support of unicast filtering
When adding more MAC address to a dwmac-sun8i interface, the device goes
directly in promiscuous mode.
This is due to IFF_UNICAST_FLT missing flag.
So since the hardware support unicast filtering, let's add IFF_UNICAST_FLT.
Fixes: 9f93ac8d4085 ("net-next: stmmac: Add dwmac-sun8i")
Signed-off-by: Corentin Labbe
---
drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
index ac19bf62db70..9d3112beb19f 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
@@ -1018,6 +1018,8 @@ static struct mac_device_info *sun8i_dwmac_setup(void
*ppriv)
mac->mac = &sun8i_dwmac_ops;
mac->dma = &sun8i_dwmac_dma_ops;
+ priv->dev->priv_flags |= IFF_UNICAST_FLT;
+
/* The loopback bit seems to be re-set when link change
* Simply mask it each time
* Speed 10/100/1000 are set in BIT(2)/BIT(3)
--
2.21.0
Re: [RFC net-next v2 00/14] net: stmmac: Selftests
On Tue, May 14, 2019 at 05:45:22PM +0200, Jose Abreu wrote: > [ Submitting with net-next closed for proper review and testing. ] > > This introduces selftests support in stmmac driver. We add 9 basic sanity > checks and MAC loopback support for all cores within the driver. This way > more tests can easily be added in the future and can be run in virtually > any MAC/GMAC/QoS/XGMAC platform. > > Having this we can find regressions and missing features in the driver > while at the same time we can check if the IP is correctly working. > > We have been using this for some time now and I do have more tests to > submit in the feature. My experience is that although writing the tests > adds more development time, the gain results are obvious. > > I let this feature optional within the driver under a Kconfig option. > > Cc: Joao Pinto > Cc: David S. Miller > Cc: Giuseppe Cavallaro > Cc: Alexandre Torgue > Cc: Corentin Labbe > Cc: Andrew Lunn > > Corentin Labbe (1): > net: ethernet: stmmac: dwmac-sun8i: Enable control of loopback > > Jose Abreu (13): > net: stmmac: Add MAC loopback callback to HWIF > net: stmmac: dwmac100: Add MAC loopback support > net: stmmac: dwmac1000: Add MAC loopback support > net: stmmac: dwmac4/5: Add MAC loopback support > net: stmmac: dwxgmac2: Add MAC loopback support > net: stmmac: Switch MMC functions to HWIF callbacks > net: stmmac: dwmac1000: Also pass control frames while in promisc mode > net: stmmac: dwmac4/5: Also pass control frames while in promisc mode > net: stmmac: dwxgmac2: Also pass control frames while in promisc mode > net: stmmac: Introduce selftests support > net: stmmac: dwmac1000: Fix Hash Filter > net: stmmac: dwmac1000: Clear unused address entries > net: stmmac: dwmac4/5: Fix Hash Filter > > drivers/net/ethernet/stmicro/stmmac/Kconfig| 9 + > drivers/net/ethernet/stmicro/stmmac/Makefile | 2 + > drivers/net/ethernet/stmicro/stmmac/common.h | 1 + > drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c | 13 + > drivers/net/ethernet/stmicro/stmmac/dwmac1000.h| 1 + > .../net/ethernet/stmicro/stmmac/dwmac1000_core.c | 22 +- > .../net/ethernet/stmicro/stmmac/dwmac100_core.c| 13 + > drivers/net/ethernet/stmicro/stmmac/dwmac4.h | 3 + > drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c | 19 +- > drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h | 2 + > .../net/ethernet/stmicro/stmmac/dwxgmac2_core.c| 15 +- > drivers/net/ethernet/stmicro/stmmac/hwif.c | 9 + > drivers/net/ethernet/stmicro/stmmac/hwif.h | 21 + > drivers/net/ethernet/stmicro/stmmac/mmc.h | 4 - > drivers/net/ethernet/stmicro/stmmac/mmc_core.c | 13 +- > drivers/net/ethernet/stmicro/stmmac/stmmac.h | 22 + > .../net/ethernet/stmicro/stmmac/stmmac_ethtool.c | 8 +- > drivers/net/ethernet/stmicro/stmmac/stmmac_main.c | 4 +- > .../net/ethernet/stmicro/stmmac/stmmac_selftests.c | 846 > +++++ > 19 files changed, 1014 insertions(+), 13 deletions(-) > create mode 100644 drivers/net/ethernet/stmicro/stmmac/stmmac_selftests.c > > -- > 2.7.4 > Tested-by: Corentin LABBE Tested-on: sun7i-a20-cubieboard2 Tested-on: sun50i-a64-bananapi-m64 Tested-on: meson-gxl-s905x-libretech-cc For information the output is: On sun50i-a64-bananapi-m64 ethtool --test eth0 offline The test result is PASS The test extra info: 1. MAC Loopback 0 2. PHY Loopback -95 3. MMC Counters -95 4. EEE -95 5. Hash Filter MC 0 6. Perfect Filter UC0 7. MC Filter0 8. UC Filter0 9. Flow Control -95 with onine I got dwmac-sun8i 1c3.ethernet eth0: Only offline tests are supported on sun7i-a20-cubieboard2: ethtool --test eth0 offline The test result is PASS The test extra info: 1. MAC Loopback 0 2. PHY Loopback -95 3. MMC Counters -95 4. EEE -95 5. Hash Filter MC 0 6. Perfect Filter UC0 7. MC Filter0 8. UC Filter0 9. Flow Control -95 With online I got: sun7i-dwmac 1c5.ethernet eth0: Only offline tests are supported on meson-gxl-s905x-libretech-cc: ethtool --test eth0 offline The test result is FAIL The test extra info: 1. MAC Loopback 0 2. PHY Loopback -95 3. MMC Counters -1 4. EEE -95 5. Hash Filter MC 0 6. Perfect Filter UC0 7. MC Filter0 8. UC Filter0 9. Flow Control -95 with onine I got meson8b-dwmac c941.ethernet eth0: Only offline tests are supported I will try to investigate the MMC failure. Does -1 (vs other -E) is the right error code to return from the driver ?
Re: [PATCH v6 05/11] dt-bindings: net: dwmac-sun8i: update documentation about integrated PHY
On Thu, Sep 28, 2017 at 09:37:08AM +0200, Corentin Labbe wrote:
> On Wed, Sep 27, 2017 at 04:02:10PM +0200, Andrew Lunn wrote:
> > Hi Corentin
> >
> > > +Required properties for the mdio-mux node:
> > > + - compatible = "mdio-mux"
> >
> > This is too generic. Please add a more specific compatible for this
> > particular mux. You can keep "mdio-mux", since that is what the MDIO
> > subsystem will look for.
> >
>
> I will add allwinner,sun8i-h3-mdio-mux
>
> > > +Required properties of the integrated phy node:
> > > - clocks: a phandle to the reference clock for the EPHY
> > > - resets: a phandle to the reset control for the EPHY
> > > +- phy-is-integrated
> >
> > So the last thing you said is that the mux is not the problem
> > here. Something else is locking up. Did you discover what?
> >
> > I really would like phy-is-integrated to go away.
> >
>
> I have found the problem: by enabling ephy clk/reset the timeout does not
> occur anymore.
> So we could remove phy-is-integrated by:
> Moving internal phy clk/reset handling in mdio_mux_syscon_switch_fn()
> But this means:
> - getting internalphy node always by manually get internal_mdio/internal_phy
> (and not by the given phyhandle)
> - doing some unnecessary tasks (enable/scan/disable) when external_phy is
> needed
>
> Regards
Hello all
Below is the current patch, as you can read, it does not use anymore the
phy-is-integrated property.
So now, the mdio-mux must always enable the internal mdio when switch_fn ask
for it and so reset MAC and so need to enable ephy clk/reset.
But for this I need a reference to thoses clock and reset. (this is done in
get_ephy_nodes)
The current version set those clock in mdio-mux node, and as you can see it is
already ugly (lots of get next node),
if the clk/rst nodes were as it should be, in phy nodes, it will be more bad.
So, since the MAC have a dependency on thoses clk/rst nodes for doing reset(),
I seek a proper way to get references on it.
OR do you agree that putting ephy clk/rst in emac is acceptable ?
thanks
regards
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
@@ -17,6 +17,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -41,14 +42,14 @@
* This value is used for disabling properly EMAC
* and used as a good starting value in case of the
* boot process(uboot) leave some stuff.
- * @internal_phy: Does the MAC embed an internal PHY
+ * @soc_has_internal_phy: Does the MAC embed an internal PHY
* @support_mii: Does the MAC handle MII
* @support_rmii: Does the MAC handle RMII
* @support_rgmii: Does the MAC handle RGMII
*/
struct emac_variant {
u32 default_syscon_value;
- int internal_phy;
+ bool soc_has_internal_phy;
bool support_mii;
bool support_rmii;
bool support_rgmii;
@@ -61,7 +62,7 @@ struct emac_variant {
* @rst_ephy: reference to the optional EPHY reset for the internal PHY
* @variant: reference to the current board variant
* @regmap:regmap for using the syscon
- * @use_internal_phy: Does the current PHY choice imply using the internal PHY
+ * @internal_phy_powered: Does the internal PHY is enabled
*/
struct sunxi_priv_data {
struct clk *tx_clk;
@@ -70,12 +71,13 @@ struct sunxi_priv_data {
struct reset_control *rst_ephy;
const struct emac_variant *variant;
struct regmap *regmap;
- bool use_internal_phy;
+ bool internal_phy_powered;
+ void *mux_handle;
};
static const struct emac_variant emac_variant_h3 = {
.default_syscon_value = 0x58000,
- .internal_phy = PHY_INTERFACE_MODE_MII,
+ .soc_has_internal_phy = true,
.support_mii = true,
.support_rmii = true,
.support_rgmii = true
@@ -83,20 +85,20 @@ static const struct emac_variant emac_variant_h3 = {
static const struct emac_variant emac_variant_v3s = {
.default_syscon_value = 0x38000,
- .internal_phy = PHY_INTERFACE_MODE_MII,
+ .soc_has_internal_phy = true,
.support_mii = true
};
static const struct emac_variant emac_variant_a83t = {
.default_syscon_value = 0,
- .internal_phy = 0,
+ .soc_has_internal_phy = false,
.support_mii = true,
.support_rgmii = true
};
static const struct emac_variant emac_variant_a64 = {
.default_syscon_value = 0,
- .internal_phy = 0,
+ .soc_has_internal_phy = false,
.support_mii = true,
.support_rmii = true,
.support_rgmii = true
@@ -195,6 +197,9 @@ static const struct emac_variant emac_variant_a6
[PATCH v7 06/10] ARM: dts: sunxi: h3/h5: represent the mdio switch used by sun8i-h3-emac
Since dwmac-sun8i could use either an integrated PHY or an external PHY
(which could be at same MDIO address), we need to represent this selection
by a MDIO switch.
Signed-off-by: Corentin Labbe
---
arch/arm/boot/dts/sunxi-h3-h5.dtsi | 33 +++--
1 file changed, 27 insertions(+), 6 deletions(-)
diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi
b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
index d762098fc589..895816f4d741 100644
--- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi
+++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
@@ -422,14 +422,35 @@
#size-cells = <0>;
status = "disabled";
- mdio: mdio {
+ mdio0: mdio {
#address-cells = <1>;
#size-cells = <0>;
- int_mii_phy: ethernet-phy@1 {
- compatible =
"ethernet-phy-ieee802.3-c22";
- reg = <1>;
- clocks = <&ccu CLK_BUS_EPHY>;
- resets = <&ccu RST_BUS_EPHY>;
+ compatible = "snps,dwmac-mdio";
+
+ mdio-mux {
+ compatible = "mdio-mux",
"allwinner,sun8i-h3-mdio-mux";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ /* Only one MDIO is usable at the time
*/
+ internal_mdio: mdio@1 {
+ compatible =
"allwinner,sun8i-h3-mdio-internal";
+ reg = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ int_mii_phy: ethernet-phy@1 {
+ compatible =
"ethernet-phy-ieee802.3-c22";
+ reg = <1>;
+ clocks = <&ccu
CLK_BUS_EPHY>;
+ resets = <&ccu
RST_BUS_EPHY>;
+ };
+ };
+
+ external_mdio: mdio@2 {
+ reg = <2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
};
};
};
--
2.13.6
[PATCH v7 10/10] of: mdio: Prevent of_mdiobus_register from scanning mdio-mux nodes
Each child node of an MDIO node is scanned as a PHY when calling
of_mdiobus_register() givint the following result:
[ 18.175379] mdio_bus stmmac-0: /soc/ethernet@1c3/mdio/mdio-mux has
invalid PHY address
[ 18.175408] mdio_bus stmmac-0: scan phy mdio-mux at address 0
[ 18.175450] mdio_bus stmmac-0: scan phy mdio-mux at address 1
[...]
[ 18.176420] mdio_bus stmmac-0: scan phy mdio-mux at address 30
[ 18.176452] mdio_bus stmmac-0: scan phy mdio-mux at address 31
Since mdio-mux nodes are not PHY, this patch a way to to not scan
them.
Signed-off-by: Corentin Labbe
---
drivers/of/of_mdio.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/drivers/of/of_mdio.c b/drivers/of/of_mdio.c
index d94dd8b77abd..90f3ac87c98f 100644
--- a/drivers/of/of_mdio.c
+++ b/drivers/of/of_mdio.c
@@ -190,6 +190,10 @@ int of_mdiobus_register(struct mii_bus *mdio, struct
device_node *np)
struct device_node *child;
bool scanphys = false;
int addr, rc;
+ static const struct of_device_id compatible_muxes[] = {
+ { .compatible = "mdio-mux" },
+ {}
+ };
/* Do not continue if the node is disabled */
if (!of_device_is_available(np))
@@ -212,6 +216,9 @@ int of_mdiobus_register(struct mii_bus *mdio, struct
device_node *np)
/* Loop over the child nodes and register a phy_device for each phy */
for_each_available_child_of_node(np, child) {
+ if (of_match_node(compatible_muxes, child))
+ continue;
+
addr = of_mdio_parse_addr(&mdio->dev, child);
if (addr < 0) {
scanphys = true;
@@ -229,6 +236,9 @@ int of_mdiobus_register(struct mii_bus *mdio, struct
device_node *np)
/* auto scan for PHYs with empty reg property */
for_each_available_child_of_node(np, child) {
+ if (of_match_node(compatible_muxes, child))
+ continue;
+
/* Skip PHYs with reg property set */
if (of_find_property(child, "reg", NULL))
continue;
--
2.13.6
[PATCH v7 09/10] net: stmmac: dwmac-sun8i: Handle integrated/external MDIOs
The Allwinner H3 SoC have two distinct MDIO bus, only one could be
active at the same time.
The selection of the active MDIO bus are done via some bits in the EMAC
register of the system controller.
This patch implement this MDIO switch via a custom MDIO-mux.
Signed-off-by: Corentin Labbe
---
drivers/net/ethernet/stmicro/stmmac/Kconfig | 1 +
drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c | 353 ++
2 files changed, 224 insertions(+), 130 deletions(-)
diff --git a/drivers/net/ethernet/stmicro/stmmac/Kconfig
b/drivers/net/ethernet/stmicro/stmmac/Kconfig
index 97035766c291..e28c0d2c58e9 100644
--- a/drivers/net/ethernet/stmicro/stmmac/Kconfig
+++ b/drivers/net/ethernet/stmicro/stmmac/Kconfig
@@ -159,6 +159,7 @@ config DWMAC_SUN8I
tristate "Allwinner sun8i GMAC support"
default ARCH_SUNXI
depends on OF && (ARCH_SUNXI || COMPILE_TEST)
+ select MDIO_BUS_MUX
---help---
Support for Allwinner H3 A83T A64 EMAC ethernet controllers.
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
index fffd6d5fc907..7741235093b9 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
@@ -17,6 +17,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -41,14 +42,14 @@
* This value is used for disabling properly EMAC
* and used as a good starting value in case of the
* boot process(uboot) leave some stuff.
- * @internal_phy: Does the MAC embed an internal PHY
+ * @soc_has_internal_phy: Does the MAC embed an internal PHY
* @support_mii: Does the MAC handle MII
* @support_rmii: Does the MAC handle RMII
* @support_rgmii: Does the MAC handle RGMII
*/
struct emac_variant {
u32 default_syscon_value;
- int internal_phy;
+ bool soc_has_internal_phy;
bool support_mii;
bool support_rmii;
bool support_rgmii;
@@ -61,7 +62,8 @@ struct emac_variant {
* @rst_ephy: reference to the optional EPHY reset for the internal PHY
* @variant: reference to the current board variant
* @regmap:regmap for using the syscon
- * @use_internal_phy: Does the current PHY choice imply using the internal PHY
+ * @internal_phy_powered: Does the internal PHY is enabled
+ * @mux_handle:Internal pointer used by mdio-mux lib
*/
struct sunxi_priv_data {
struct clk *tx_clk;
@@ -70,12 +72,13 @@ struct sunxi_priv_data {
struct reset_control *rst_ephy;
const struct emac_variant *variant;
struct regmap *regmap;
- bool use_internal_phy;
+ bool internal_phy_powered;
+ void *mux_handle;
};
static const struct emac_variant emac_variant_h3 = {
.default_syscon_value = 0x58000,
- .internal_phy = PHY_INTERFACE_MODE_MII,
+ .soc_has_internal_phy = true,
.support_mii = true,
.support_rmii = true,
.support_rgmii = true
@@ -83,20 +86,20 @@ static const struct emac_variant emac_variant_h3 = {
static const struct emac_variant emac_variant_v3s = {
.default_syscon_value = 0x38000,
- .internal_phy = PHY_INTERFACE_MODE_MII,
+ .soc_has_internal_phy = true,
.support_mii = true
};
static const struct emac_variant emac_variant_a83t = {
.default_syscon_value = 0,
- .internal_phy = 0,
+ .soc_has_internal_phy = false,
.support_mii = true,
.support_rgmii = true
};
static const struct emac_variant emac_variant_a64 = {
.default_syscon_value = 0,
- .internal_phy = 0,
+ .soc_has_internal_phy = false,
.support_mii = true,
.support_rmii = true,
.support_rgmii = true
@@ -195,6 +198,9 @@ static const struct emac_variant emac_variant_a64 = {
#define H3_EPHY_LED_POLBIT(17) /* 1: active low, 0: active
high */
#define H3_EPHY_SHUTDOWN BIT(16) /* 1: shutdown, 0: power up */
#define H3_EPHY_SELECT BIT(15) /* 1: internal PHY, 0: external PHY */
+#define H3_EPHY_MUX_MASK (H3_EPHY_SHUTDOWN | H3_EPHY_SELECT)
+#define DWMAC_SUN8I_MDIO_MUX_INTERNAL_ID 1
+#define DWMAC_SUN8I_MDIO_MUX_EXTERNAL_ID 2
/* H3/A64 specific bits */
#define SYSCON_RMII_EN BIT(13) /* 1: enable RMII (overrides EPIT) */
@@ -634,6 +640,159 @@ static int sun8i_dwmac_reset(struct stmmac_priv *priv)
return 0;
}
+/* Search in mdio-mux node for internal PHY node and get its clk/reset */
+static int get_ephy_nodes(struct stmmac_priv *priv)
+{
+ struct sunxi_priv_data *gmac = priv->plat->bsp_priv;
+ struct device_node *mdio_mux, *iphynode;
+ struct device_node *mdio_internal;
+ int ret;
+
+ mdio_mux = of_get_child_by_name(priv->plat->mdio_node, &quo
[PATCH v7 08/10] net: stmmac: snps,dwmac-mdio MDIOs are automatically registered
stmmac bindings docs said that its mdio node must have
compatible = "snps,dwmac-mdio";
Since dwmac-sun8i does not have any good reasons to not doing it, all
their MDIO node must have it.
Since these compatible is automatically registered, dwmac-sun8i compatible
does not need to be in need_mdio_ids.
Signed-off-by: Corentin Labbe
---
drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c | 4
1 file changed, 4 deletions(-)
diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
index 8a280b48e3a9..9e616da0745d 100644
--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
@@ -311,10 +311,6 @@ static int stmmac_dt_phy(struct plat_stmmacenet_data *plat,
bool mdio = true;
static const struct of_device_id need_mdio_ids[] = {
{ .compatible = "snps,dwc-qos-ethernet-4.10" },
- { .compatible = "allwinner,sun8i-a83t-emac" },
- { .compatible = "allwinner,sun8i-h3-emac" },
- { .compatible = "allwinner,sun8i-v3s-emac" },
- { .compatible = "allwinner,sun50i-a64-emac" },
{},
};
--
2.13.6
[PATCH v7 05/10] dt-bindings: net: dwmac-sun8i: update documentation about integrated PHY
This patch add documentation about the MDIO switch used on sun8i-h3-emac
for integrated PHY.
Signed-off-by: Corentin Labbe
---
.../devicetree/bindings/net/dwmac-sun8i.txt| 139 +++--
1 file changed, 127 insertions(+), 12 deletions(-)
diff --git a/Documentation/devicetree/bindings/net/dwmac-sun8i.txt
b/Documentation/devicetree/bindings/net/dwmac-sun8i.txt
index 725f3b187886..0ae7d2096375 100644
--- a/Documentation/devicetree/bindings/net/dwmac-sun8i.txt
+++ b/Documentation/devicetree/bindings/net/dwmac-sun8i.txt
@@ -4,18 +4,18 @@ This device is a platform glue layer for stmmac.
Please see stmmac.txt for the other unchanged properties.
Required properties:
-- compatible: should be one of the following string:
+- compatible: must be one of the following string:
"allwinner,sun8i-a83t-emac"
"allwinner,sun8i-h3-emac"
"allwinner,sun8i-v3s-emac"
"allwinner,sun50i-a64-emac"
- reg: address and length of the register for the device.
- interrupts: interrupt for the device
-- interrupt-names: should be "macirq"
+- interrupt-names: must be "macirq"
- clocks: A phandle to the reference clock for this device
-- clock-names: should be "stmmaceth"
+- clock-names: must be "stmmaceth"
- resets: A phandle to the reset control for this device
-- reset-names: should be "stmmaceth"
+- reset-names: must be "stmmaceth"
- phy-mode: See ethernet.txt
- phy-handle: See ethernet.txt
- #address-cells: shall be 1
@@ -39,23 +39,38 @@ Optional properties for the following compatibles:
- allwinner,leds-active-low: EPHY LEDs are active low
Required child node of emac:
-- mdio bus node: should be named mdio
+- mdio bus node: with compatible "snps,dwmac-mdio"
Required properties of the mdio node:
- #address-cells: shall be 1
- #size-cells: shall be 0
-The device node referenced by "phy" or "phy-handle" should be a child node
+The device node referenced by "phy" or "phy-handle" must be a child node
of the mdio node. See phy.txt for the generic PHY bindings.
-Required properties of the phy node with the following compatibles:
+The following compatibles require that the mdio node have a mdio-mux child
+node called "mdio-mux":
+ - "allwinner,sun8i-h3-emac"
+ - "allwinner,sun8i-v3s-emac":
+Required properties for the mdio-mux node:
+ - compatible = "mdio-mux", "allwinner,sun8i-h3-mdio-mux"
+ - one child mdio for the integrated mdio with the compatible
+"allwinner,sun8i-h3-mdio-internal"
+ - one child mdio for the external mdio if present (V3s have none)
+Required properties for the mdio-mux children node:
+ - reg: 1 for internal MDIO bus, 2 for external MDIO bus
+
+The following compatibles require a PHY node representing the integrated
+PHY, under the integrated MDIO bus node if an mdio-mux node is used:
- "allwinner,sun8i-h3-emac",
- "allwinner,sun8i-v3s-emac":
+
+Required properties of the integrated phy node:
- clocks: a phandle to the reference clock for the EPHY
- resets: a phandle to the reset control for the EPHY
+- Must be a child of the integrated mdio
-Example:
-
+Example with integrated PHY:
emac: ethernet@1c0b000 {
compatible = "allwinner,sun8i-h3-emac";
syscon = <&syscon>;
@@ -72,13 +87,113 @@ emac: ethernet@1c0b000 {
phy-handle = <&int_mii_phy>;
phy-mode = "mii";
allwinner,leds-active-low;
+
+ mdio0: mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "snps,dwmac-mdio";
+
+ mdio-mux {
+ compatible = "mdio-mux", "allwinner,sun8i-h3-mdio-mux";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ int_mdio: mdio@1 {
+ compatible = "allwinner,sun8i-h3-mdio-internal";
+ reg = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ int_mii_phy: ethernet-phy@1 {
+ reg = <1>;
+ clocks = <&ccu CLK_BUS_EPHY>;
+ resets = <&ccu RST_BUS_EPHY>;
+ phy-is-integrated;
+ };
+ };
+ ext_mdio: mdio@2 {
+ reg = <2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
[PATCH v7 04/10] net: stmmac: sun8i: Restore the compatibles
The original dwmac-sun8i DT bindings have some issue on how to handle
integrated PHY and was reverted in last RC of 4.13.
But now we have a solution so we need to get back that was reverted.
This patch restore compatibles about dwmac-sun8i
This reverts commit ad4540cc5aa3 ("net: stmmac: sun8i: Remove the compatibles")
Signed-off-by: Corentin Labbe
---
drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
index 39c2122a4f26..fffd6d5fc907 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
@@ -979,6 +979,14 @@ static int sun8i_dwmac_probe(struct platform_device *pdev)
}
static const struct of_device_id sun8i_dwmac_match[] = {
+ { .compatible = "allwinner,sun8i-h3-emac",
+ .data = &emac_variant_h3 },
+ { .compatible = "allwinner,sun8i-v3s-emac",
+ .data = &emac_variant_v3s },
+ { .compatible = "allwinner,sun8i-a83t-emac",
+ .data = &emac_variant_a83t },
+ { .compatible = "allwinner,sun50i-a64-emac",
+ .data = &emac_variant_a64 },
{ }
};
MODULE_DEVICE_TABLE(of, sun8i_dwmac_match);
--
2.13.6
[PATCH v7 07/10] arm64: dts: allwinner: add snps,dwmac-mdio compatible to emac/mdio
stmmac bindings docs said that its mdio node must have
compatible = "snps,dwmac-mdio";
Since dwmac-sun8i does not have any good reasons to not doing it, all
their MDIO node must have it.
Signed-off-by: Corentin Labbe
---
arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
index 0650a1cda107..0a2074f86f2c 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
@@ -532,6 +532,7 @@
#size-cells = <0>;
mdio: mdio {
+ compatible = "snps,dwmac-mdio";
#address-cells = <1>;
#size-cells = <0>;
};
--
2.13.6
[PATCH v7 03/10] arm64: dts: allwinner: Restore EMAC changes
The original dwmac-sun8i DT bindings have some issue on how to handle
integrated PHY and was reverted in last RC of 4.13.
But now we have a solution so we need to get back that was reverted.
This patch restore arm64 DT about dwmac-sun8i
This reverts commit 87e1f5e8bb4b ("arm64: dts: allwinner: Revert EMAC changes")
Signed-off-by: Corentin Labbe
---
.../boot/dts/allwinner/sun50i-a64-bananapi-m64.dts | 16
.../boot/dts/allwinner/sun50i-a64-pine64-plus.dts| 15 +++
arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts | 17 +
.../dts/allwinner/sun50i-a64-sopine-baseboard.dts| 16
arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi| 20
.../boot/dts/allwinner/sun50i-h5-nanopi-neo2.dts | 17 +
.../boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts| 17 +
.../boot/dts/allwinner/sun50i-h5-orangepi-prime.dts | 17 +
8 files changed, 135 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts
b/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts
index d347f52e27f6..45bdbfb96126 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts
@@ -51,6 +51,7 @@
compatible = "sinovoip,bananapi-m64", "allwinner,sun50i-a64";
aliases {
+ ethernet0 = &emac;
serial0 = &uart0;
serial1 = &uart1;
};
@@ -69,6 +70,14 @@
status = "okay";
};
+&emac {
+ pinctrl-names = "default";
+ pinctrl-0 = <&rgmii_pins>;
+ phy-mode = "rgmii";
+ phy-handle = <&ext_rgmii_phy>;
+ status = "okay";
+};
+
&i2c1 {
pinctrl-names = "default";
pinctrl-0 = <&i2c1_pins>;
@@ -79,6 +88,13 @@
bias-pull-up;
};
+&mdio {
+ ext_rgmii_phy: ethernet-phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <1>;
+ };
+};
+
&mmc0 {
pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins>;
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-plus.dts
b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-plus.dts
index f82ccf332c0f..24f1aac366d6 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-plus.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-plus.dts
@@ -48,3 +48,18 @@
/* TODO: Camera, touchscreen, etc. */
};
+
+&emac {
+ pinctrl-names = "default";
+ pinctrl-0 = <&rgmii_pins>;
+ phy-mode = "rgmii";
+ phy-handle = <&ext_rgmii_phy>;
+ status = "okay";
+};
+
+&mdio {
+ ext_rgmii_phy: ethernet-phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <1>;
+ };
+};
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
index d06e34b5d192..806442d3e846 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
@@ -51,6 +51,7 @@
compatible = "pine64,pine64", "allwinner,sun50i-a64";
aliases {
+ ethernet0 = &emac;
serial0 = &uart0;
serial1 = &uart1;
serial2 = &uart2;
@@ -71,6 +72,15 @@
status = "okay";
};
+&emac {
+ pinctrl-names = "default";
+ pinctrl-0 = <&rmii_pins>;
+ phy-mode = "rmii";
+ phy-handle = <&ext_rmii_phy1>;
+ status = "okay";
+
+};
+
&i2c1 {
pinctrl-names = "default";
pinctrl-0 = <&i2c1_pins>;
@@ -81,6 +91,13 @@
bias-pull-up;
};
+&mdio {
+ ext_rmii_phy1: ethernet-phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <1>;
+ };
+};
+
&mmc0 {
pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins>;
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts
b/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts
index 17ccc12b58df..0eb2acedf8c3 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts
@@ -53,6 +53,7 @@
"allwinner,sun50i-a64";
aliases {
+ ethernet0 = &emac;
serial0 = &uart0;
};
@@ -76,6 +77,21 @@
status = "okay";
};
+&emac {
+ pinctrl-names = "default";
+ pinctrl-0 = <&rgmii_pins>;
+ phy-mode =
[PATCH v7 02/10] arm: dts: sunxi: Restore EMAC changes
The original dwmac-sun8i DT bindings have some issue on how to handle
integrated PHY and was reverted in last RC of 4.13.
But now we have a solution so we need to get back that was reverted.
This patch restore arm DT about dwmac-sun8i
This reverts commit fe45174b72ae ("arm: dts: sunxi: Revert EMAC changes")
Signed-off-by: Corentin Labbe
---
arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts | 9
arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts | 19 +
arch/arm/boot/dts/sun8i-h3-nanopi-m1-plus.dts | 19 +
arch/arm/boot/dts/sun8i-h3-nanopi-neo.dts | 7 ++
arch/arm/boot/dts/sun8i-h3-orangepi-2.dts | 8 +++
arch/arm/boot/dts/sun8i-h3-orangepi-one.dts | 8 +++
arch/arm/boot/dts/sun8i-h3-orangepi-pc-plus.dts | 5 +
arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts| 8 +++
arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts | 22 +++
arch/arm/boot/dts/sun8i-h3-orangepi-plus2e.dts| 16 ++
arch/arm/boot/dts/sunxi-h3-h5.dtsi| 26 +++
11 files changed, 147 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts
b/arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts
index b1502df7b509..6713d0f2b3f4 100644
--- a/arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts
+++ b/arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts
@@ -56,6 +56,8 @@
aliases {
serial0 = &uart0;
+ /* ethernet0 is the H3 emac, defined in sun8i-h3.dtsi */
+ ethernet0 = &emac;
ethernet1 = &xr819;
};
@@ -102,6 +104,13 @@
status = "okay";
};
+&emac {
+ phy-handle = <&int_mii_phy>;
+ phy-mode = "mii";
+ allwinner,leds-active-low;
+ status = "okay";
+};
+
&mmc0 {
pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins_a>;
diff --git a/arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts
b/arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts
index e1dba9ffa94b..f2292deaa590 100644
--- a/arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts
+++ b/arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts
@@ -52,6 +52,7 @@
compatible = "sinovoip,bpi-m2-plus", "allwinner,sun8i-h3";
aliases {
+ ethernet0 = &emac;
serial0 = &uart0;
serial1 = &uart1;
};
@@ -111,6 +112,24 @@
status = "okay";
};
+&emac {
+ pinctrl-names = "default";
+ pinctrl-0 = <&emac_rgmii_pins>;
+ phy-supply = <®_gmac_3v3>;
+ phy-handle = <&ext_rgmii_phy>;
+ phy-mode = "rgmii";
+
+ allwinner,leds-active-low;
+ status = "okay";
+};
+
+&external_mdio {
+ ext_rgmii_phy: ethernet-phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <0>;
+ };
+};
+
&ir {
pinctrl-names = "default";
pinctrl-0 = <&ir_pins_a>;
diff --git a/arch/arm/boot/dts/sun8i-h3-nanopi-m1-plus.dts
b/arch/arm/boot/dts/sun8i-h3-nanopi-m1-plus.dts
index 73766d38ee6c..cfb96da3cfef 100644
--- a/arch/arm/boot/dts/sun8i-h3-nanopi-m1-plus.dts
+++ b/arch/arm/boot/dts/sun8i-h3-nanopi-m1-plus.dts
@@ -66,6 +66,25 @@
status = "okay";
};
+&emac {
+ pinctrl-names = "default";
+ pinctrl-0 = <&emac_rgmii_pins>;
+ phy-supply = <®_gmac_3v3>;
+ phy-handle = <&ext_rgmii_phy>;
+ phy-mode = "rgmii";
+
+ allwinner,leds-active-low;
+
+ status = "okay";
+};
+
+&external_mdio {
+ ext_rgmii_phy: ethernet-phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <7>;
+ };
+};
+
&ir {
pinctrl-names = "default";
pinctrl-0 = <&ir_pins_a>;
diff --git a/arch/arm/boot/dts/sun8i-h3-nanopi-neo.dts
b/arch/arm/boot/dts/sun8i-h3-nanopi-neo.dts
index 8d2cc6e9a03f..78f6c24952dd 100644
--- a/arch/arm/boot/dts/sun8i-h3-nanopi-neo.dts
+++ b/arch/arm/boot/dts/sun8i-h3-nanopi-neo.dts
@@ -46,3 +46,10 @@
model = "FriendlyARM NanoPi NEO";
compatible = "friendlyarm,nanopi-neo", "allwinner,sun8i-h3";
};
+
+&emac {
+ phy-handle = <&int_mii_phy>;
+ phy-mode = "mii";
+ allwinner,leds-active-low;
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts
b/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts
index 1bf51802f5aa..b20be95b49d5 100644
--- a/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts
+++ b/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts
@@ -54,6 +54,7 @@
aliases {
serial0 = &uart0;
/* ethernet0 is the H
[PATCH v7 01/10] dt-bindings: net: Restore sun8i dwmac binding
The original dwmac-sun8i DT bindings have some issue on how to handle
integrated PHY and was reverted in last RC of 4.13.
But now we have a solution so we need to get back that was reverted.
This patch restore dt-bindings documentation about dwmac-sun8i
This reverts commit 8aa33ec2f481 ("dt-bindings: net: Revert sun8i dwmac
binding")
Signed-off-by: Corentin Labbe
---
.../devicetree/bindings/net/dwmac-sun8i.txt| 84 ++
1 file changed, 84 insertions(+)
create mode 100644 Documentation/devicetree/bindings/net/dwmac-sun8i.txt
diff --git a/Documentation/devicetree/bindings/net/dwmac-sun8i.txt
b/Documentation/devicetree/bindings/net/dwmac-sun8i.txt
new file mode 100644
index ..725f3b187886
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/dwmac-sun8i.txt
@@ -0,0 +1,84 @@
+* Allwinner sun8i GMAC ethernet controller
+
+This device is a platform glue layer for stmmac.
+Please see stmmac.txt for the other unchanged properties.
+
+Required properties:
+- compatible: should be one of the following string:
+ "allwinner,sun8i-a83t-emac"
+ "allwinner,sun8i-h3-emac"
+ "allwinner,sun8i-v3s-emac"
+ "allwinner,sun50i-a64-emac"
+- reg: address and length of the register for the device.
+- interrupts: interrupt for the device
+- interrupt-names: should be "macirq"
+- clocks: A phandle to the reference clock for this device
+- clock-names: should be "stmmaceth"
+- resets: A phandle to the reset control for this device
+- reset-names: should be "stmmaceth"
+- phy-mode: See ethernet.txt
+- phy-handle: See ethernet.txt
+- #address-cells: shall be 1
+- #size-cells: shall be 0
+- syscon: A phandle to the syscon of the SoC with one of the following
+ compatible string:
+ - allwinner,sun8i-h3-system-controller
+ - allwinner,sun8i-v3s-system-controller
+ - allwinner,sun50i-a64-system-controller
+ - allwinner,sun8i-a83t-system-controller
+
+Optional properties:
+- allwinner,tx-delay-ps: TX clock delay chain value in ps. Range value is
0-700. Default is 0)
+- allwinner,rx-delay-ps: RX clock delay chain value in ps. Range value is
0-3100. Default is 0)
+Both delay properties need to be a multiple of 100. They control the delay for
+external PHY.
+
+Optional properties for the following compatibles:
+ - "allwinner,sun8i-h3-emac",
+ - "allwinner,sun8i-v3s-emac":
+- allwinner,leds-active-low: EPHY LEDs are active low
+
+Required child node of emac:
+- mdio bus node: should be named mdio
+
+Required properties of the mdio node:
+- #address-cells: shall be 1
+- #size-cells: shall be 0
+
+The device node referenced by "phy" or "phy-handle" should be a child node
+of the mdio node. See phy.txt for the generic PHY bindings.
+
+Required properties of the phy node with the following compatibles:
+ - "allwinner,sun8i-h3-emac",
+ - "allwinner,sun8i-v3s-emac":
+- clocks: a phandle to the reference clock for the EPHY
+- resets: a phandle to the reset control for the EPHY
+
+Example:
+
+emac: ethernet@1c0b000 {
+ compatible = "allwinner,sun8i-h3-emac";
+ syscon = <&syscon>;
+ reg = <0x01c0b000 0x104>;
+ interrupts = ;
+ interrupt-names = "macirq";
+ resets = <&ccu RST_BUS_EMAC>;
+ reset-names = "stmmaceth";
+ clocks = <&ccu CLK_BUS_EMAC>;
+ clock-names = "stmmaceth";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ phy-handle = <&int_mii_phy>;
+ phy-mode = "mii";
+ allwinner,leds-active-low;
+ mdio: mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ int_mii_phy: ethernet-phy@1 {
+ reg = <1>;
+ clocks = <&ccu CLK_BUS_EPHY>;
+ resets = <&ccu RST_BUS_EPHY>;
+ };
+ };
+};
--
2.13.6
[PATCH v7 00/10] net: stmmac: dwmac-sun8i: Handle integrated PHY
Hello The current way to find if the PHY is internal is to compare DT phy-mode and emac_variant/internal_phy. But it will negate a possible future SoC where an external PHY use the same phy mode than the integrated one. This patchs series adds a new way to handle this problem via a mdio-mux. The first try was to create a new MDIO mux "mdio-mux-syscon". mdio-mux-syscon working the same way than mdio-mux-mmioreg with the exception that the register is used via syscon/regmap. But this solution does not work for two reason: - changing the MDIO selection need the reset of MAC which cannot be done by the mdio-mux-syscon driver - There were driver loading order problem: - mdio-mux-syscon needing that stmmac register the parent MDIO - stmmac needing that child MDIO was registered just after registering parent MDIO So we cannot use any external MDIO-mux. The final solution was to represent the mdio-mux in MAC node and let the MAC handle all things. Since DT bits was reverted in 4.13, this patch series include the revert of the revert. So - the first four patchs bring back DT/stmmac stuff that was in 4.13 (and reverted) - fifth patch document how DT MDIO mux is implemented - patch 6 and 7 modify DT - patch 8, 9 Modify stmmac according to the new bindings I have let patch splited for easy review. (for seeing what's new) But the final serie could have some patch squashed if someone want. Like squashing patch and 2 and 5 (documentation) Regards Changes since v6: - renamed external mdio to "external_mdio" - added compatible to mdio-mux and internal-mdio - removed usage of phy-is-integrated - renamed do_not_scan to compatible_muxes (patch 10) - patch 8 9 of v6 are squashed Changes since v5: - reordered patch 1 and 2 - mdio-mux node is now a mdio's child - added patch 11 for removing unnecessary scan of mdio-mux Changes since v4: - Update documentation for new bindings - Added 4 patchs for bring back reverted stuff of 4.13 - dwmac-sun8i now handle mdio-mux - MDIO use now compatible = "snps,dwmac-mdio"; Changes since v3: - Added a patch for handling fixed-link - Updated documentation Changes since v2: - Add a MDIO mux for creating distinction between integrated and external MDIO. - phy-is-integrated is not set in dtsi. Changes since v1: - Dropped phy-is-integrated documentation patch since another same patch was already merged - Moved phy-is-integrated from SoC dtsi to final board DT. Corentin Labbe (10): dt-bindings: net: Restore sun8i dwmac binding arm: dts: sunxi: Restore EMAC changes arm64: dts: allwinner: Restore EMAC changes net: stmmac: sun8i: Restore the compatibles dt-bindings: net: dwmac-sun8i: update documentation about integrated PHY ARM: dts: sunxi: h3/h5: represent the mdio switch used by sun8i-h3-emac arm64: dts: allwinner: add snps,dwmac-mdio compatible to emac/mdio net: stmmac: snps,dwmac-mdio MDIOs are automatically registered net: stmmac: dwmac-sun8i: Handle integrated/external MDIOs of: mdio: Prevent of_mdiobus_register from scanning mdio-mux nodes .../devicetree/bindings/net/dwmac-sun8i.txt| 199 arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts | 9 + arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts| 19 ++ arch/arm/boot/dts/sun8i-h3-nanopi-m1-plus.dts | 19 ++ arch/arm/boot/dts/sun8i-h3-nanopi-neo.dts | 7 + arch/arm/boot/dts/sun8i-h3-orangepi-2.dts | 8 + arch/arm/boot/dts/sun8i-h3-orangepi-one.dts| 8 + arch/arm/boot/dts/sun8i-h3-orangepi-pc-plus.dts| 5 + arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts | 8 + arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts | 22 ++ arch/arm/boot/dts/sun8i-h3-orangepi-plus2e.dts | 16 + arch/arm/boot/dts/sunxi-h3-h5.dtsi | 47 +++ .../boot/dts/allwinner/sun50i-a64-bananapi-m64.dts | 16 + .../boot/dts/allwinner/sun50i-a64-pine64-plus.dts | 15 + .../arm64/boot/dts/allwinner/sun50i-a64-pine64.dts | 17 + .../dts/allwinner/sun50i-a64-sopine-baseboard.dts | 16 + arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 21 ++ .../boot/dts/allwinner/sun50i-h5-nanopi-neo2.dts | 17 + .../boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts | 17 + .../dts/allwinner/sun50i-h5-orangepi-prime.dts | 17 + drivers/net/ethernet/stmicro/stmmac/Kconfig| 1 + drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c | 361 + .../net/ethernet/stmicro/stmmac/stmmac_platform.c | 4 - drivers/of/of_mdio.c | 10 + 24 files changed, 745 insertions(+), 134 deletions(-) create mode 100644 Documentation/devicetree/bindings/net/dwmac-sun8i.txt -- 2.13.6
Re: [PATCH v5 05/10] dt-bindings: net: dwmac-sun8i: update documentation about integrated PHY
On Tue, Sep 19, 2017 at 09:49:52PM -0500, Rob Herring wrote: > On Thu, Sep 14, 2017 at 2:19 PM, Andrew Lunn wrote: > >> > Is the MDIO controller "allwinner,sun8i-h3-emac" or "snps,dwmac-mdio"? > >> > If the latter, then I think the node is fine, but then the mux should be > >> > a child node of it. IOW, the child of an MDIO controller should either > >> > be a mux node or slave devices. > > > > Hi Rob > > > > Up until now, children of an MDIO bus have been MDIO devices. Those > > MDIO devices are either Ethernet PHYs, Ethernet Switches, or the > > oddball devices that Broadcom iProc has, like generic PHYs. > > > > We have never had MDIO-muxes as MDIO children. A Mux is not an MDIO > > device, and does not have the properties of an MDIO device. It is not > > addressable on the MDIO bus. The current MUXes are addressed via GPIOs > > or MMIO. > > The DT parent/child relationship defines the bus topology. We describe > MDIO buses in that way and if a mux is sitting between the controller > and the devices, then the DT hierarchy should reflect that. Now > sometimes we have 2 options for what interface has the parent/child > relationship (e.g. an I2C controlled USB hub chip), but in this case > we don't. > Putting mdio-mux as a child of it (the mdio node) give me: [ 18.175338] libphy: stmmac: probed [ 18.175379] mdio_bus stmmac-0: /soc/ethernet@1c3/mdio/mdio-mux has invalid PHY address [ 18.175408] mdio_bus stmmac-0: scan phy mdio-mux at address 0 [ 18.175450] mdio_bus stmmac-0: scan phy mdio-mux at address 1 [ 18.175482] mdio_bus stmmac-0: scan phy mdio-mux at address 2 [ 18.175513] mdio_bus stmmac-0: scan phy mdio-mux at address 3 [ 18.175544] mdio_bus stmmac-0: scan phy mdio-mux at address 4 [ 18.175575] mdio_bus stmmac-0: scan phy mdio-mux at address 5 [ 18.175607] mdio_bus stmmac-0: scan phy mdio-mux at address 6 [ 18.175638] mdio_bus stmmac-0: scan phy mdio-mux at address 7 [ 18.175669] mdio_bus stmmac-0: scan phy mdio-mux at address 8 [ 18.175700] mdio_bus stmmac-0: scan phy mdio-mux at address 9 [ 18.175731] mdio_bus stmmac-0: scan phy mdio-mux at address 10 [ 18.175762] mdio_bus stmmac-0: scan phy mdio-mux at address 11 [ 18.175795] mdio_bus stmmac-0: scan phy mdio-mux at address 12 [ 18.175827] mdio_bus stmmac-0: scan phy mdio-mux at address 13 [ 18.175858] mdio_bus stmmac-0: scan phy mdio-mux at address 14 [ 18.175889] mdio_bus stmmac-0: scan phy mdio-mux at address 15 [ 18.175919] mdio_bus stmmac-0: scan phy mdio-mux at address 16 [ 18.175951] mdio_bus stmmac-0: scan phy mdio-mux at address 17 [ 18.175982] mdio_bus stmmac-0: scan phy mdio-mux at address 18 [ 18.176014] mdio_bus stmmac-0: scan phy mdio-mux at address 19 [ 18.176045] mdio_bus stmmac-0: scan phy mdio-mux at address 20 [ 18.176076] mdio_bus stmmac-0: scan phy mdio-mux at address 21 [ 18.176107] mdio_bus stmmac-0: scan phy mdio-mux at address 22 [ 18.176139] mdio_bus stmmac-0: scan phy mdio-mux at address 23 [ 18.176170] mdio_bus stmmac-0: scan phy mdio-mux at address 24 [ 18.176202] mdio_bus stmmac-0: scan phy mdio-mux at address 25 [ 18.176233] mdio_bus stmmac-0: scan phy mdio-mux at address 26 [ 18.176271] mdio_bus stmmac-0: scan phy mdio-mux at address 27 [ 18.176320] mdio_bus stmmac-0: scan phy mdio-mux at address 28 [ 18.176371] mdio_bus stmmac-0: scan phy mdio-mux at address 29 [ 18.176420] mdio_bus stmmac-0: scan phy mdio-mux at address 30 [ 18.176452] mdio_bus stmmac-0: scan phy mdio-mux at address 31 Adding a fake to mdio-mux remove it, but I found that a bit ugly. Or perhaps patching of_mdiobus_register() to not scan node with compatible "mdio-mux". What do you think ? Regards
[PATCH v6 11/11] of: mdio: Prevent of_mdiobus_register from scanning mdio-mux nodes
Each child node of an MDIO node is scanned as a PHY when calling
of_mdiobus_register() givint the following result:
[ 18.175379] mdio_bus stmmac-0: /soc/ethernet@1c3/mdio/mdio-mux has
invalid PHY address
[ 18.175408] mdio_bus stmmac-0: scan phy mdio-mux at address 0
[ 18.175450] mdio_bus stmmac-0: scan phy mdio-mux at address 1
[...]
[ 18.176420] mdio_bus stmmac-0: scan phy mdio-mux at address 30
[ 18.176452] mdio_bus stmmac-0: scan phy mdio-mux at address 31
Since mdio-mux nodes are not PHY, this patch a way to to not scan
them.
Signed-off-by: Corentin Labbe
---
drivers/of/of_mdio.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/drivers/of/of_mdio.c b/drivers/of/of_mdio.c
index d94dd8b77abd..d90ddb0d90f2 100644
--- a/drivers/of/of_mdio.c
+++ b/drivers/of/of_mdio.c
@@ -190,6 +190,10 @@ int of_mdiobus_register(struct mii_bus *mdio, struct
device_node *np)
struct device_node *child;
bool scanphys = false;
int addr, rc;
+ static const struct of_device_id do_not_scan[] = {
+ { .compatible = "mdio-mux" },
+ {}
+ };
/* Do not continue if the node is disabled */
if (!of_device_is_available(np))
@@ -212,6 +216,9 @@ int of_mdiobus_register(struct mii_bus *mdio, struct
device_node *np)
/* Loop over the child nodes and register a phy_device for each phy */
for_each_available_child_of_node(np, child) {
+ if (of_match_node(do_not_scan, child))
+ continue;
+
addr = of_mdio_parse_addr(&mdio->dev, child);
if (addr < 0) {
scanphys = true;
@@ -229,6 +236,9 @@ int of_mdiobus_register(struct mii_bus *mdio, struct
device_node *np)
/* auto scan for PHYs with empty reg property */
for_each_available_child_of_node(np, child) {
+ if (of_match_node(do_not_scan, child))
+ continue;
+
/* Skip PHYs with reg property set */
if (of_find_property(child, "reg", NULL))
continue;
--
2.13.5
[PATCH v6 10/11] net: stmmac: dwmac-sun8i: Handle integrated/external MDIOs
The Allwinner H3 SoC have two distinct MDIO bus, only one could be
active at the same time.
The selection of the active MDIO bus are done via some bits in the EMAC
register of the system controller.
This patch implement this MDIO switch via a custom MDIO-mux.
Signed-off-by: Corentin Labbe
---
drivers/net/ethernet/stmicro/stmmac/Kconfig | 1 +
drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c | 116 +++---
2 files changed, 104 insertions(+), 13 deletions(-)
diff --git a/drivers/net/ethernet/stmicro/stmmac/Kconfig
b/drivers/net/ethernet/stmicro/stmmac/Kconfig
index 97035766c291..e28c0d2c58e9 100644
--- a/drivers/net/ethernet/stmicro/stmmac/Kconfig
+++ b/drivers/net/ethernet/stmicro/stmmac/Kconfig
@@ -159,6 +159,7 @@ config DWMAC_SUN8I
tristate "Allwinner sun8i GMAC support"
default ARCH_SUNXI
depends on OF && (ARCH_SUNXI || COMPILE_TEST)
+ select MDIO_BUS_MUX
---help---
Support for Allwinner H3 A83T A64 EMAC ethernet controllers.
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
index 672553b652bd..8bd500c351b4 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
@@ -17,6 +17,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -71,6 +72,7 @@ struct sunxi_priv_data {
const struct emac_variant *variant;
struct regmap *regmap;
bool use_internal_phy;
+ void *mux_handle;
};
static const struct emac_variant emac_variant_h3 = {
@@ -195,6 +197,9 @@ static const struct emac_variant emac_variant_a64 = {
#define H3_EPHY_LED_POLBIT(17) /* 1: active low, 0: active
high */
#define H3_EPHY_SHUTDOWN BIT(16) /* 1: shutdown, 0: power up */
#define H3_EPHY_SELECT BIT(15) /* 1: internal PHY, 0: external PHY */
+#define H3_EPHY_MUX_MASK (H3_EPHY_SHUTDOWN | H3_EPHY_SELECT)
+#define DWMAC_SUN8I_MDIO_MUX_INTERNAL_ID 1
+#define DWMAC_SUN8I_MDIO_MUX_EXTERNAL_ID 2
/* H3/A64 specific bits */
#define SYSCON_RMII_EN BIT(13) /* 1: enable RMII (overrides EPIT) */
@@ -634,6 +639,76 @@ static int sun8i_dwmac_reset(struct stmmac_priv *priv)
return 0;
}
+/* MDIO multiplexing switch function
+ * This function is called by the mdio-mux layer when it thinks the mdio bus
+ * multiplexer needs to switch.
+ * 'current_child' is the current value of the mux register
+ * 'desired_child' is the value of the 'reg' property of the target child MDIO
+ * node.
+ * The first time this function is called, current_child == -1.
+ * If current_child == desired_child, then the mux is already set to the
+ * correct bus.
+ *
+ * Note that we do not use reg/mask like mdio-mux-mmioreg because we need to
+ * know easily which bus is used (reset must be done only for desired bus).
+ */
+static int mdio_mux_syscon_switch_fn(int current_child, int desired_child,
+void *data)
+{
+ struct stmmac_priv *priv = data;
+ struct sunxi_priv_data *gmac = priv->plat->bsp_priv;
+ u32 reg, val;
+ int ret = 0;
+ bool need_reset = false;
+
+ if (current_child ^ desired_child) {
+ regmap_read(gmac->regmap, SYSCON_EMAC_REG, ®);
+ switch (desired_child) {
+ case DWMAC_SUN8I_MDIO_MUX_INTERNAL_ID:
+ dev_info(priv->device, "Switch mux to internal PHY");
+ val = (reg & ~H3_EPHY_MUX_MASK) | H3_EPHY_SELECT;
+ if (gmac->use_internal_phy)
+ need_reset = true;
+ break;
+ case DWMAC_SUN8I_MDIO_MUX_EXTERNAL_ID:
+ dev_info(priv->device, "Switch mux to external PHY");
+ val = (reg & ~H3_EPHY_MUX_MASK) | H3_EPHY_SHUTDOWN;
+ if (!gmac->use_internal_phy)
+ need_reset = true;
+ break;
+ default:
+ dev_err(priv->device, "Invalid child id %x\n",
desired_child);
+ return -EINVAL;
+ }
+ regmap_write(gmac->regmap, SYSCON_EMAC_REG, val);
+ /* After changing syscon value, the MAC need reset or it will
use
+* the last value (and so the last PHY set).
+* Reset is necessary only when we reach the needed MDIO,
+* it timeout in other case.
+*/
+ if (need_reset)
+ ret = sun8i_dwmac_reset(priv);
+ else
+ dev_dbg(priv->device, "skipped reset\n");
+ }
+ return ret;
+}
+
+static int sun8i_dwmac_register_mdio_mux(struct stmmac_pri
[PATCH v6 09/11] net: stmmac: dwmac-sun8i: choose internal PHY via phy-is-integrated
The current way to find if the phy is internal is to compare DT phy-mode
and emac_variant/internal_phy.
But it will negate a possible future SoC where an external PHY use the
same phy mode than the internal one.
This patch adds a new way to find if the PHY is internal, via
the phy-is-integrated property.
Since the internal_phy variable does not need anymore to contain the xMII mode
used by the internal PHY, it is still used for knowing the presence of an
internal PHY, so it is modified to a boolean soc_has_internal_phy.
Signed-off-by: Corentin Labbe
Acked-by: Chen-Yu Tsai
Reviewed-by: Florian Fainelli
---
drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c | 16
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
index fffd6d5fc907..672553b652bd 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
@@ -41,14 +41,14 @@
* This value is used for disabling properly EMAC
* and used as a good starting value in case of the
* boot process(uboot) leave some stuff.
- * @internal_phy: Does the MAC embed an internal PHY
+ * @soc_has_internal_phy: Does the MAC embed an internal PHY
* @support_mii: Does the MAC handle MII
* @support_rmii: Does the MAC handle RMII
* @support_rgmii: Does the MAC handle RGMII
*/
struct emac_variant {
u32 default_syscon_value;
- int internal_phy;
+ bool soc_has_internal_phy;
bool support_mii;
bool support_rmii;
bool support_rgmii;
@@ -75,7 +75,7 @@ struct sunxi_priv_data {
static const struct emac_variant emac_variant_h3 = {
.default_syscon_value = 0x58000,
- .internal_phy = PHY_INTERFACE_MODE_MII,
+ .soc_has_internal_phy = true,
.support_mii = true,
.support_rmii = true,
.support_rgmii = true
@@ -83,20 +83,20 @@ static const struct emac_variant emac_variant_h3 = {
static const struct emac_variant emac_variant_v3s = {
.default_syscon_value = 0x38000,
- .internal_phy = PHY_INTERFACE_MODE_MII,
+ .soc_has_internal_phy = true,
.support_mii = true
};
static const struct emac_variant emac_variant_a83t = {
.default_syscon_value = 0,
- .internal_phy = 0,
+ .soc_has_internal_phy = false,
.support_mii = true,
.support_rgmii = true
};
static const struct emac_variant emac_variant_a64 = {
.default_syscon_value = 0,
- .internal_phy = 0,
+ .soc_has_internal_phy = false,
.support_mii = true,
.support_rmii = true,
.support_rgmii = true
@@ -648,7 +648,7 @@ static int sun8i_dwmac_set_syscon(struct stmmac_priv *priv)
"Current syscon value is not the default %x (expect
%x)\n",
val, reg);
- if (gmac->variant->internal_phy) {
+ if (gmac->variant->soc_has_internal_phy) {
if (!gmac->use_internal_phy) {
/* switch to external PHY interface */
reg &= ~H3_EPHY_SELECT;
@@ -932,7 +932,7 @@ static int sun8i_dwmac_probe(struct platform_device *pdev)
}
plat_dat->interface = of_get_phy_mode(dev->of_node);
- if (plat_dat->interface == gmac->variant->internal_phy) {
+ if (of_property_read_bool(plat_dat->phy_node, "phy-is-integrated")) {
dev_info(&pdev->dev, "Will use internal PHY\n");
gmac->use_internal_phy = true;
gmac->ephy_clk = of_clk_get(plat_dat->phy_node, 0);
--
2.13.5
[PATCH v6 07/11] arm64: dts: allwinner: add snps,dwmac-mdio compatible to emac/mdio
stmmac bindings docs said that its mdio node must have
compatible = "snps,dwmac-mdio";
Since dwmac-sun8i does not have any good reasons to not doing it, all
their MDIO node must have it.
Signed-off-by: Corentin Labbe
---
arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
index 75494cd90e40..e30476f05802 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
@@ -517,6 +517,7 @@
#size-cells = <0>;
mdio: mdio {
+ compatible = "snps,dwmac-mdio";
#address-cells = <1>;
#size-cells = <0>;
};
--
2.13.5
[PATCH v6 06/11] ARM: dts: sunxi: h3/h5: represent the mdio switch used by sun8i-h3-emac
Since dwmac-sun8i could use either an integrated PHY or an external PHY
(which could be at same MDIO address), we need to represent this selection
by a MDIO switch.
Signed-off-by: Corentin Labbe
---
arch/arm/boot/dts/sunxi-h3-h5.dtsi | 31 +--
1 file changed, 25 insertions(+), 6 deletions(-)
diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi
b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
index 3b7d953429a6..a8e9b8f378ba 100644
--- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi
+++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
@@ -422,14 +422,33 @@
#size-cells = <0>;
status = "disabled";
- mdio: mdio {
+ mdio0: mdio {
#address-cells = <1>;
#size-cells = <0>;
- int_mii_phy: ethernet-phy@1 {
- compatible =
"ethernet-phy-ieee802.3-c22";
- reg = <1>;
- clocks = <&ccu CLK_BUS_EPHY>;
- resets = <&ccu RST_BUS_EPHY>;
+ compatible = "snps,dwmac-mdio";
+
+ mdio-mux {
+ compatible = "mdio-mux";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ /* Only one MDIO is usable at the time
*/
+ internal_mdio: mdio@1 {
+ reg = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ int_mii_phy: ethernet-phy@1 {
+ compatible =
"ethernet-phy-ieee802.3-c22";
+ reg = <1>;
+ clocks = <&ccu
CLK_BUS_EPHY>;
+ resets = <&ccu
RST_BUS_EPHY>;
+ phy-is-integrated;
+ };
+ };
+ mdio: mdio@2 {
+ reg = <2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
};
};
};
--
2.13.5
[PATCH v6 08/11] net: stmmac: snps,dwmac-mdio MDIOs are automatically registered
stmmac bindings docs said that its mdio node must have
compatible = "snps,dwmac-mdio";
Since dwmac-sun8i does not have any good reasons to not doing it, all
their MDIO node must have it.
Since these compatible is automatically registered, dwmac-sun8i compatible
does not need to be in need_mdio_ids.
Signed-off-by: Corentin Labbe
---
drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c | 4
1 file changed, 4 deletions(-)
diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
index 8a280b48e3a9..9e616da0745d 100644
--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
@@ -311,10 +311,6 @@ static int stmmac_dt_phy(struct plat_stmmacenet_data *plat,
bool mdio = true;
static const struct of_device_id need_mdio_ids[] = {
{ .compatible = "snps,dwc-qos-ethernet-4.10" },
- { .compatible = "allwinner,sun8i-a83t-emac" },
- { .compatible = "allwinner,sun8i-h3-emac" },
- { .compatible = "allwinner,sun8i-v3s-emac" },
- { .compatible = "allwinner,sun50i-a64-emac" },
{},
};
--
2.13.5
[PATCH v6 03/11] arm64: dts: allwinner: Restore EMAC changes
This patch restore arm64 DT about dwmac-sun8i
This reverts commit 87e1f5e8bb4b ("arm64: dts: allwinner: Revert EMAC changes")
Signed-off-by: Corentin Labbe
---
.../boot/dts/allwinner/sun50i-a64-bananapi-m64.dts | 16
.../boot/dts/allwinner/sun50i-a64-pine64-plus.dts| 15 +++
arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts | 17 +
.../dts/allwinner/sun50i-a64-sopine-baseboard.dts| 16
arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi| 20
.../boot/dts/allwinner/sun50i-h5-nanopi-neo2.dts | 17 +
.../boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts| 17 +
.../boot/dts/allwinner/sun50i-h5-orangepi-prime.dts | 17 +
8 files changed, 135 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts
b/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts
index d347f52e27f6..45bdbfb96126 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts
@@ -51,6 +51,7 @@
compatible = "sinovoip,bananapi-m64", "allwinner,sun50i-a64";
aliases {
+ ethernet0 = &emac;
serial0 = &uart0;
serial1 = &uart1;
};
@@ -69,6 +70,14 @@
status = "okay";
};
+&emac {
+ pinctrl-names = "default";
+ pinctrl-0 = <&rgmii_pins>;
+ phy-mode = "rgmii";
+ phy-handle = <&ext_rgmii_phy>;
+ status = "okay";
+};
+
&i2c1 {
pinctrl-names = "default";
pinctrl-0 = <&i2c1_pins>;
@@ -79,6 +88,13 @@
bias-pull-up;
};
+&mdio {
+ ext_rgmii_phy: ethernet-phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <1>;
+ };
+};
+
&mmc0 {
pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins>;
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-plus.dts
b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-plus.dts
index f82ccf332c0f..24f1aac366d6 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-plus.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64-plus.dts
@@ -48,3 +48,18 @@
/* TODO: Camera, touchscreen, etc. */
};
+
+&emac {
+ pinctrl-names = "default";
+ pinctrl-0 = <&rgmii_pins>;
+ phy-mode = "rgmii";
+ phy-handle = <&ext_rgmii_phy>;
+ status = "okay";
+};
+
+&mdio {
+ ext_rgmii_phy: ethernet-phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <1>;
+ };
+};
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
index d06e34b5d192..806442d3e846 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
@@ -51,6 +51,7 @@
compatible = "pine64,pine64", "allwinner,sun50i-a64";
aliases {
+ ethernet0 = &emac;
serial0 = &uart0;
serial1 = &uart1;
serial2 = &uart2;
@@ -71,6 +72,15 @@
status = "okay";
};
+&emac {
+ pinctrl-names = "default";
+ pinctrl-0 = <&rmii_pins>;
+ phy-mode = "rmii";
+ phy-handle = <&ext_rmii_phy1>;
+ status = "okay";
+
+};
+
&i2c1 {
pinctrl-names = "default";
pinctrl-0 = <&i2c1_pins>;
@@ -81,6 +91,13 @@
bias-pull-up;
};
+&mdio {
+ ext_rmii_phy1: ethernet-phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <1>;
+ };
+};
+
&mmc0 {
pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins>;
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts
b/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts
index 17ccc12b58df..0eb2acedf8c3 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts
@@ -53,6 +53,7 @@
"allwinner,sun50i-a64";
aliases {
+ ethernet0 = &emac;
serial0 = &uart0;
};
@@ -76,6 +77,21 @@
status = "okay";
};
+&emac {
+ pinctrl-names = "default";
+ pinctrl-0 = <&rgmii_pins>;
+ phy-mode = "rgmii";
+ phy-handle = <&ext_rgmii_phy>;
+ status = "okay";
+};
+
+&mdio {
+ ext_rgmii_phy: ethernet-
[PATCH v6 02/11] arm: dts: sunxi: Restore EMAC changes
This patch restore arm DT about dwmac-sun8i
This reverts commit fe45174b72ae ("arm: dts: sunxi: Revert EMAC changes")
Signed-off-by: Corentin Labbe
---
arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts | 9
arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts | 19 +
arch/arm/boot/dts/sun8i-h3-nanopi-neo.dts | 7 ++
arch/arm/boot/dts/sun8i-h3-orangepi-2.dts | 8 +++
arch/arm/boot/dts/sun8i-h3-orangepi-one.dts | 8 +++
arch/arm/boot/dts/sun8i-h3-orangepi-pc-plus.dts | 5 +
arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts| 8 +++
arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts | 22 +++
arch/arm/boot/dts/sun8i-h3-orangepi-plus2e.dts| 16 ++
arch/arm/boot/dts/sunxi-h3-h5.dtsi| 26 +++
10 files changed, 128 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts
b/arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts
index b1502df7b509..6713d0f2b3f4 100644
--- a/arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts
+++ b/arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts
@@ -56,6 +56,8 @@
aliases {
serial0 = &uart0;
+ /* ethernet0 is the H3 emac, defined in sun8i-h3.dtsi */
+ ethernet0 = &emac;
ethernet1 = &xr819;
};
@@ -102,6 +104,13 @@
status = "okay";
};
+&emac {
+ phy-handle = <&int_mii_phy>;
+ phy-mode = "mii";
+ allwinner,leds-active-low;
+ status = "okay";
+};
+
&mmc0 {
pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins_a>;
diff --git a/arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts
b/arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts
index e1dba9ffa94b..cc20d676a642 100644
--- a/arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts
+++ b/arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts
@@ -52,6 +52,7 @@
compatible = "sinovoip,bpi-m2-plus", "allwinner,sun8i-h3";
aliases {
+ ethernet0 = &emac;
serial0 = &uart0;
serial1 = &uart1;
};
@@ -111,12 +112,30 @@
status = "okay";
};
+&emac {
+ pinctrl-names = "default";
+ pinctrl-0 = <&emac_rgmii_pins>;
+ phy-supply = <®_gmac_3v3>;
+ phy-handle = <&ext_rgmii_phy>;
+ phy-mode = "rgmii";
+
+ allwinner,leds-active-low;
+ status = "okay";
+};
+
&ir {
pinctrl-names = "default";
pinctrl-0 = <&ir_pins_a>;
status = "okay";
};
+&mdio {
+ ext_rgmii_phy: ethernet-phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <0>;
+ };
+};
+
&mmc0 {
pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>;
diff --git a/arch/arm/boot/dts/sun8i-h3-nanopi-neo.dts
b/arch/arm/boot/dts/sun8i-h3-nanopi-neo.dts
index 8d2cc6e9a03f..78f6c24952dd 100644
--- a/arch/arm/boot/dts/sun8i-h3-nanopi-neo.dts
+++ b/arch/arm/boot/dts/sun8i-h3-nanopi-neo.dts
@@ -46,3 +46,10 @@
model = "FriendlyARM NanoPi NEO";
compatible = "friendlyarm,nanopi-neo", "allwinner,sun8i-h3";
};
+
+&emac {
+ phy-handle = <&int_mii_phy>;
+ phy-mode = "mii";
+ allwinner,leds-active-low;
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts
b/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts
index 8ff71b1bb45b..17cdeae19c6f 100644
--- a/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts
+++ b/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts
@@ -54,6 +54,7 @@
aliases {
serial0 = &uart0;
/* ethernet0 is the H3 emac, defined in sun8i-h3.dtsi */
+ ethernet0 = &emac;
ethernet1 = &rtl8189;
};
@@ -117,6 +118,13 @@
status = "okay";
};
+&emac {
+ phy-handle = <&int_mii_phy>;
+ phy-mode = "mii";
+ allwinner,leds-active-low;
+ status = "okay";
+};
+
&ir {
pinctrl-names = "default";
pinctrl-0 = <&ir_pins_a>;
diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-one.dts
b/arch/arm/boot/dts/sun8i-h3-orangepi-one.dts
index 5fea430e0eb1..6880268e8b87 100644
--- a/arch/arm/boot/dts/sun8i-h3-orangepi-one.dts
+++ b/arch/arm/boot/dts/sun8i-h3-orangepi-one.dts
@@ -52,6 +52,7 @@
compatible = "xunlong,orangepi-one", "allwinner,sun8i-h3";
aliases {
+ ethernet0 = &emac;
serial0 = &uart0;
};
@@ -97,6 +98,13 @@
status = "okay";
};
+&emac {
+ phy-handle
[PATCH v6 05/11] dt-bindings: net: dwmac-sun8i: update documentation about integrated PHY
This patch add documentation about the MDIO switch used on sun8i-h3-emac
for integrated PHY.
Signed-off-by: Corentin Labbe
---
.../devicetree/bindings/net/dwmac-sun8i.txt| 138 +++--
1 file changed, 126 insertions(+), 12 deletions(-)
diff --git a/Documentation/devicetree/bindings/net/dwmac-sun8i.txt
b/Documentation/devicetree/bindings/net/dwmac-sun8i.txt
index 725f3b187886..e2ef4683df08 100644
--- a/Documentation/devicetree/bindings/net/dwmac-sun8i.txt
+++ b/Documentation/devicetree/bindings/net/dwmac-sun8i.txt
@@ -4,18 +4,18 @@ This device is a platform glue layer for stmmac.
Please see stmmac.txt for the other unchanged properties.
Required properties:
-- compatible: should be one of the following string:
+- compatible: must be one of the following string:
"allwinner,sun8i-a83t-emac"
"allwinner,sun8i-h3-emac"
"allwinner,sun8i-v3s-emac"
"allwinner,sun50i-a64-emac"
- reg: address and length of the register for the device.
- interrupts: interrupt for the device
-- interrupt-names: should be "macirq"
+- interrupt-names: must be "macirq"
- clocks: A phandle to the reference clock for this device
-- clock-names: should be "stmmaceth"
+- clock-names: must be "stmmaceth"
- resets: A phandle to the reset control for this device
-- reset-names: should be "stmmaceth"
+- reset-names: must be "stmmaceth"
- phy-mode: See ethernet.txt
- phy-handle: See ethernet.txt
- #address-cells: shall be 1
@@ -39,23 +39,38 @@ Optional properties for the following compatibles:
- allwinner,leds-active-low: EPHY LEDs are active low
Required child node of emac:
-- mdio bus node: should be named mdio
+- mdio bus node: with compatible "snps,dwmac-mdio"
Required properties of the mdio node:
- #address-cells: shall be 1
- #size-cells: shall be 0
-The device node referenced by "phy" or "phy-handle" should be a child node
+The device node referenced by "phy" or "phy-handle" must be a child node
of the mdio node. See phy.txt for the generic PHY bindings.
-Required properties of the phy node with the following compatibles:
+The following compatibles require that the mdio node have a mdio-mux child
+node called "mdio-mux":
+ - "allwinner,sun8i-h3-emac"
+ - "allwinner,sun8i-v3s-emac":
+Required properties for the mdio-mux node:
+ - compatible = "mdio-mux"
+ - one child mdio for the integrated mdio
+ - one child mdio for the external mdio if present (V3s have none)
+Required properties for the mdio-mux children node:
+ - reg: 1 for internal MDIO bus, 2 for external MDIO bus
+
+The following compatibles require a PHY node representing the integrated
+PHY, under the integrated MDIO bus node if an mdio-mux node is used:
- "allwinner,sun8i-h3-emac",
- "allwinner,sun8i-v3s-emac":
+
+Required properties of the integrated phy node:
- clocks: a phandle to the reference clock for the EPHY
- resets: a phandle to the reset control for the EPHY
+- phy-is-integrated
+- Must be a child of the integrated mdio
-Example:
-
+Example with integrated PHY:
emac: ethernet@1c0b000 {
compatible = "allwinner,sun8i-h3-emac";
syscon = <&syscon>;
@@ -72,13 +87,112 @@ emac: ethernet@1c0b000 {
phy-handle = <&int_mii_phy>;
phy-mode = "mii";
allwinner,leds-active-low;
+
+ mdio0: mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "snps,dwmac-mdio";
+
+ mdio-mux {
+ compatible = "mdio-mux";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ int_mdio: mdio@1 {
+ reg = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ int_mii_phy: ethernet-phy@1 {
+ reg = <1>;
+ clocks = <&ccu CLK_BUS_EPHY>;
+ resets = <&ccu RST_BUS_EPHY>;
+ phy-is-integrated;
+ };
+ };
+ ext_mdio: mdio@2 {
+ reg = <2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+ };
+};
+
+Example with external PHY:
+emac: ethernet@1c0b000 {
+ compatible = "allwinner,sun8i-h3-emac";
+ syscon = <&syscon>;
+ reg = <0x01
[PATCH v6 04/11] net: stmmac: sun8i: Restore the compatibles
This patch restore compatibles about dwmac-sun8i
This reverts commit ad4540cc5aa3 ("net: stmmac: sun8i: Remove the compatibles")
Signed-off-by: Corentin Labbe
---
drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
index 39c2122a4f26..fffd6d5fc907 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
@@ -979,6 +979,14 @@ static int sun8i_dwmac_probe(struct platform_device *pdev)
}
static const struct of_device_id sun8i_dwmac_match[] = {
+ { .compatible = "allwinner,sun8i-h3-emac",
+ .data = &emac_variant_h3 },
+ { .compatible = "allwinner,sun8i-v3s-emac",
+ .data = &emac_variant_v3s },
+ { .compatible = "allwinner,sun8i-a83t-emac",
+ .data = &emac_variant_a83t },
+ { .compatible = "allwinner,sun50i-a64-emac",
+ .data = &emac_variant_a64 },
{ }
};
MODULE_DEVICE_TABLE(of, sun8i_dwmac_match);
--
2.13.5
[PATCH v6 00/11] net: stmmac: dwmac-sun8i: Handle integrated PHY
Hello The current way to find if the PHY is internal is to compare DT phy-mode and emac_variant/internal_phy. But it will negate a possible future SoC where an external PHY use the same phy mode than the integrated one. This patchs series adds a new way to find if the PHY is integrated, via the phy-is-integrated DT property. Since it exists both integrated and external ethernet-phy@1, they are merged in the final DTB and so share all properties. For avoiding this, and better represent the reality, we use a MDIO mux. The first try was to create a new MDIO mux "mdio-mux-syscon". mdio-mux-syscon working the same way than mdio-mux-mmioreg with the exception that the register is used via syscon/regmap. But this solution does not work for two reason: - changing the MDIO selection need the reset of MAC which cannot be done by the mdio-mux-syscon driver - There were driver loading order problem: - mdio-mux-syscon needing that stmmac register the parent MDIO - stmmac needing that child MDIO was registered just after registering parent MDIO So we cannot use any external MDIO-mux. The final solution was to represent a mdio-mux and let the MAC handle all things. Note that phy-is-integrated is still needed (even if we use a MDIO mux) since some properties apply only on integrated PHY and we need to know the final MDIO bus in mdio_mux_syscon_switch_fn(). Since DT bits was reverted in 4.13, this patch series include the revert of the revert. So - the first four patchs bring back DT/stmmac stuff that was in 4.13 (and reverted) - fifth patch document how DT MDIO mux is implemented - patch 6 and 7 modify DT - patch 8, 9, 10 Modify stmmac according to the new bindings I have let patch splited for easy review. (for seeing what's new) But the final serie could have some patch squashed if someone want. Like squashing patch and 2 and 5 (documentation) Since DT worked well in 4.13, could it be targeted for 4.14 ? If necessary I could split this serie in two: - bring back A64/A83T (patchs 1, 2, 4, 7, 9) - add MXIO-mux and H3 (patchs 3, 4, 5, 6, 8, 10) Regards Changes since v5: - reordered patch 1 and 2 - mdio-mux node is now a mdio's child - added patch 11 for removing unnecessary scan of mdio-mux Changes since v4: - Update documentation for new bindings - Added 4 patchs for bring back reverted stuff of 4.13 - dwmac-sun8i now handle mdio-mux - MDIO use now compatible = "snps,dwmac-mdio"; Changes since v3: - Added a patch for handling fixed-link - Updated documentation Changes since v2: - Add a MDIO mux for creating distinction between integrated and external MDIO. - phy-is-integrated is not set in dtsi. Changes since v1: - Dropped phy-is-integrated documentation patch since another same patch was already merged - Moved phy-is-integrated from SoC dtsi to final board DT. Corentin Labbe (11): dt-bindings: net: Restore sun8i dwmac binding arm: dts: sunxi: Restore EMAC changes arm64: dts: allwinner: Restore EMAC changes net: stmmac: sun8i: Restore the compatibles dt-bindings: net: dwmac-sun8i: update documentation about integrated PHY ARM: dts: sunxi: h3/h5: represent the mdio switch used by sun8i-h3-emac arm64: dts: allwinner: add snps,dwmac-mdio compatible to emac/mdio net: stmmac: snps,dwmac-mdio MDIOs are automatically registered net: stmmac: dwmac-sun8i: choose internal PHY via phy-is-integrated net: stmmac: dwmac-sun8i: Handle integrated/external MDIOs of: mdio: Prevent of_mdiobus_register from scanning mdio-mux nodes .../devicetree/bindings/net/dwmac-sun8i.txt| 198 + arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts | 9 + arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts| 19 ++ arch/arm/boot/dts/sun8i-h3-nanopi-neo.dts | 7 + arch/arm/boot/dts/sun8i-h3-orangepi-2.dts | 8 + arch/arm/boot/dts/sun8i-h3-orangepi-one.dts| 8 + arch/arm/boot/dts/sun8i-h3-orangepi-pc-plus.dts| 5 + arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts | 8 + arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts | 22 +++ arch/arm/boot/dts/sun8i-h3-orangepi-plus2e.dts | 16 ++ arch/arm/boot/dts/sunxi-h3-h5.dtsi | 45 + .../boot/dts/allwinner/sun50i-a64-bananapi-m64.dts | 16 ++ .../boot/dts/allwinner/sun50i-a64-pine64-plus.dts | 15 ++ .../arm64/boot/dts/allwinner/sun50i-a64-pine64.dts | 17 ++ .../dts/allwinner/sun50i-a64-sopine-baseboard.dts | 16 ++ arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 21 +++ .../boot/dts/allwinner/sun50i-h5-nanopi-neo2.dts | 17 ++ .../boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts | 17 ++ .../dts/allwinner/sun50i-h5-orangepi-prime.dts | 17 ++ drivers/net/ethernet/stmicro/stmmac/Kconfig| 1 + drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c | 140 --- .../net/ethernet/stmicro/stmmac/stmmac_platform.c | 4 - drivers/of/of_mdio.c |
[PATCH v6 01/11] dt-bindings: net: Restore sun8i dwmac binding
This patch restore dt-bindings documentation about dwmac-sun8i
This reverts commit 8aa33ec2f481 ("dt-bindings: net: Revert sun8i dwmac
binding")
Signed-off-by: Corentin Labbe
---
.../devicetree/bindings/net/dwmac-sun8i.txt| 84 ++
1 file changed, 84 insertions(+)
create mode 100644 Documentation/devicetree/bindings/net/dwmac-sun8i.txt
diff --git a/Documentation/devicetree/bindings/net/dwmac-sun8i.txt
b/Documentation/devicetree/bindings/net/dwmac-sun8i.txt
new file mode 100644
index ..725f3b187886
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/dwmac-sun8i.txt
@@ -0,0 +1,84 @@
+* Allwinner sun8i GMAC ethernet controller
+
+This device is a platform glue layer for stmmac.
+Please see stmmac.txt for the other unchanged properties.
+
+Required properties:
+- compatible: should be one of the following string:
+ "allwinner,sun8i-a83t-emac"
+ "allwinner,sun8i-h3-emac"
+ "allwinner,sun8i-v3s-emac"
+ "allwinner,sun50i-a64-emac"
+- reg: address and length of the register for the device.
+- interrupts: interrupt for the device
+- interrupt-names: should be "macirq"
+- clocks: A phandle to the reference clock for this device
+- clock-names: should be "stmmaceth"
+- resets: A phandle to the reset control for this device
+- reset-names: should be "stmmaceth"
+- phy-mode: See ethernet.txt
+- phy-handle: See ethernet.txt
+- #address-cells: shall be 1
+- #size-cells: shall be 0
+- syscon: A phandle to the syscon of the SoC with one of the following
+ compatible string:
+ - allwinner,sun8i-h3-system-controller
+ - allwinner,sun8i-v3s-system-controller
+ - allwinner,sun50i-a64-system-controller
+ - allwinner,sun8i-a83t-system-controller
+
+Optional properties:
+- allwinner,tx-delay-ps: TX clock delay chain value in ps. Range value is
0-700. Default is 0)
+- allwinner,rx-delay-ps: RX clock delay chain value in ps. Range value is
0-3100. Default is 0)
+Both delay properties need to be a multiple of 100. They control the delay for
+external PHY.
+
+Optional properties for the following compatibles:
+ - "allwinner,sun8i-h3-emac",
+ - "allwinner,sun8i-v3s-emac":
+- allwinner,leds-active-low: EPHY LEDs are active low
+
+Required child node of emac:
+- mdio bus node: should be named mdio
+
+Required properties of the mdio node:
+- #address-cells: shall be 1
+- #size-cells: shall be 0
+
+The device node referenced by "phy" or "phy-handle" should be a child node
+of the mdio node. See phy.txt for the generic PHY bindings.
+
+Required properties of the phy node with the following compatibles:
+ - "allwinner,sun8i-h3-emac",
+ - "allwinner,sun8i-v3s-emac":
+- clocks: a phandle to the reference clock for the EPHY
+- resets: a phandle to the reset control for the EPHY
+
+Example:
+
+emac: ethernet@1c0b000 {
+ compatible = "allwinner,sun8i-h3-emac";
+ syscon = <&syscon>;
+ reg = <0x01c0b000 0x104>;
+ interrupts = ;
+ interrupt-names = "macirq";
+ resets = <&ccu RST_BUS_EMAC>;
+ reset-names = "stmmaceth";
+ clocks = <&ccu CLK_BUS_EMAC>;
+ clock-names = "stmmaceth";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ phy-handle = <&int_mii_phy>;
+ phy-mode = "mii";
+ allwinner,leds-active-low;
+ mdio: mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ int_mii_phy: ethernet-phy@1 {
+ reg = <1>;
+ clocks = <&ccu CLK_BUS_EPHY>;
+ resets = <&ccu RST_BUS_EPHY>;
+ };
+ };
+};
--
2.13.5
Re: [PATCH v6 06/11] ARM: dts: sunxi: h3/h5: represent the mdio switch used by sun8i-h3-emac
On Wed, Sep 27, 2017 at 12:16:22PM +0200, Maxime Ripard wrote:
> On Wed, Sep 27, 2017 at 07:34:09AM +0000, Corentin Labbe wrote:
> > Since dwmac-sun8i could use either an integrated PHY or an external PHY
> > (which could be at same MDIO address), we need to represent this selection
> > by a MDIO switch.
> >
> > Signed-off-by: Corentin Labbe
> > ---
> > arch/arm/boot/dts/sunxi-h3-h5.dtsi | 31 +--
> > 1 file changed, 25 insertions(+), 6 deletions(-)
> >
> > diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi
> > b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
> > index 3b7d953429a6..a8e9b8f378ba 100644
> > --- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi
> > +++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
> > @@ -422,14 +422,33 @@
> > #size-cells = <0>;
> > status = "disabled";
> >
> > - mdio: mdio {
> > + mdio0: mdio {
> > #address-cells = <1>;
> > #size-cells = <0>;
> > - int_mii_phy: ethernet-phy@1 {
> > - compatible =
> > "ethernet-phy-ieee802.3-c22";
> > - reg = <1>;
> > - clocks = <&ccu CLK_BUS_EPHY>;
> > - resets = <&ccu RST_BUS_EPHY>;
> > + compatible = "snps,dwmac-mdio";
> > +
> > + mdio-mux {
> > + compatible = "mdio-mux";
> > + #address-cells = <1>;
> > + #size-cells = <0>;
>
> Newline
>
> > + /* Only one MDIO is usable at the time
> > */
> > + internal_mdio: mdio@1 {
> > + reg = <1>;
> > + #address-cells = <1>;
> > + #size-cells = <0>;
>
> Newline
>
> > + int_mii_phy: ethernet-phy@1 {
> > + compatible =
> > "ethernet-phy-ieee802.3-c22";
> > + reg = <1>;
> > + clocks = <&ccu
> > CLK_BUS_EPHY>;
> > + resets = <&ccu
> > RST_BUS_EPHY>;
> > + phy-is-integrated;
> > + };
> > + };
>
> Newline
>
> > + mdio: mdio@2 {
>
> This is quite confusing. Why not call the label external_mdio?
>
I will do it. (at origin I was not changing it for limiting changes on board
with external PHY, but now all DT are reverted, it will be easy)
Regards
Re: [PATCH v6 05/11] dt-bindings: net: dwmac-sun8i: update documentation about integrated PHY
On Wed, Sep 27, 2017 at 09:53:15PM -0700, Florian Fainelli wrote:
>
>
> On 09/27/2017 12:34 AM, Corentin Labbe wrote:
> > This patch add documentation about the MDIO switch used on sun8i-h3-emac
> > for integrated PHY.
> >
> > Signed-off-by: Corentin Labbe
> > ---
> > .../devicetree/bindings/net/dwmac-sun8i.txt| 138
> > +++--
> > 1 file changed, 126 insertions(+), 12 deletions(-)
> >
> > diff --git a/Documentation/devicetree/bindings/net/dwmac-sun8i.txt
> > b/Documentation/devicetree/bindings/net/dwmac-sun8i.txt
> > index 725f3b187886..e2ef4683df08 100644
> > --- a/Documentation/devicetree/bindings/net/dwmac-sun8i.txt
> > +++ b/Documentation/devicetree/bindings/net/dwmac-sun8i.txt
> > @@ -4,18 +4,18 @@ This device is a platform glue layer for stmmac.
> > Please see stmmac.txt for the other unchanged properties.
> >
> > Required properties:
> > -- compatible: should be one of the following string:
> > +- compatible: must be one of the following string:
> > "allwinner,sun8i-a83t-emac"
> > "allwinner,sun8i-h3-emac"
> > "allwinner,sun8i-v3s-emac"
> > "allwinner,sun50i-a64-emac"
> > - reg: address and length of the register for the device.
> > - interrupts: interrupt for the device
> > -- interrupt-names: should be "macirq"
> > +- interrupt-names: must be "macirq"
> > - clocks: A phandle to the reference clock for this device
> > -- clock-names: should be "stmmaceth"
> > +- clock-names: must be "stmmaceth"
> > - resets: A phandle to the reset control for this device
> > -- reset-names: should be "stmmaceth"
> > +- reset-names: must be "stmmaceth"
> > - phy-mode: See ethernet.txt
> > - phy-handle: See ethernet.txt
> > - #address-cells: shall be 1
> > @@ -39,23 +39,38 @@ Optional properties for the following compatibles:
> > - allwinner,leds-active-low: EPHY LEDs are active low
> >
> > Required child node of emac:
> > -- mdio bus node: should be named mdio
> > +- mdio bus node: with compatible "snps,dwmac-mdio"
> >
> > Required properties of the mdio node:
> > - #address-cells: shall be 1
> > - #size-cells: shall be 0
> >
> > -The device node referenced by "phy" or "phy-handle" should be a child node
> > +The device node referenced by "phy" or "phy-handle" must be a child node
> > of the mdio node. See phy.txt for the generic PHY bindings.
> >
> > -Required properties of the phy node with the following compatibles:
> > +The following compatibles require that the mdio node have a mdio-mux child
> > +node called "mdio-mux":
> > + - "allwinner,sun8i-h3-emac"
> > + - "allwinner,sun8i-v3s-emac":
> > +Required properties for the mdio-mux node:
> > + - compatible = "mdio-mux"
> > + - one child mdio for the integrated mdio
> > + - one child mdio for the external mdio if present (V3s have none)
> > +Required properties for the mdio-mux children node:
> > + - reg: 1 for internal MDIO bus, 2 for external MDIO bus
> > +
> > +The following compatibles require a PHY node representing the integrated
> > +PHY, under the integrated MDIO bus node if an mdio-mux node is used:
> >- "allwinner,sun8i-h3-emac",
> >- "allwinner,sun8i-v3s-emac":
> > +
> > +Required properties of the integrated phy node:
> > - clocks: a phandle to the reference clock for the EPHY
> > - resets: a phandle to the reset control for the EPHY
> > +- phy-is-integrated
> > +- Must be a child of the integrated mdio
> >
> > -Example:
> > -
> > +Example with integrated PHY:
> > emac: ethernet@1c0b000 {
> > compatible = "allwinner,sun8i-h3-emac";
> > syscon = <&syscon>;
> > @@ -72,13 +87,112 @@ emac: ethernet@1c0b000 {
> > phy-handle = <&int_mii_phy>;
> > phy-mode = "mii";
> > allwinner,leds-active-low;
> > +
> > + mdio0: mdio {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + compatible = "snps,dwmac-mdio";
> > +
> > + mdio-mux {
> > + compatible = "mdio-mux";
> > + #address-cells = <1>;
> > + #size-cells = <0>;
>
> Sorry for chiming in so late, but why don't we have the mdio-mux be the
> root node here in the mdio bus hierarchy? I understand that with this
> binding proposed here, we need to have patch 11 included (which btw,
> should come before any DTS change), but this does not seem to accurately
> model the HW.
>
> The mux itself is not a child node of the MDIO bus controller, it does
> not really belong in that address space although it does mangle the MDIO
> bus controller address space between the two ends of the mux.
>
> If this has been debated before, apologies for missing that part of the
> discussion.
>
I have done it as asked by Rob.
https://lkml.org/lkml/2017/9/13/422
https://lkml.org/lkml/2017/9/19/849
Regards
Re: [PATCH v6 05/11] dt-bindings: net: dwmac-sun8i: update documentation about integrated PHY
On Wed, Sep 27, 2017 at 04:02:10PM +0200, Andrew Lunn wrote: > Hi Corentin > > > +Required properties for the mdio-mux node: > > + - compatible = "mdio-mux" > > This is too generic. Please add a more specific compatible for this > particular mux. You can keep "mdio-mux", since that is what the MDIO > subsystem will look for. > I will add allwinner,sun8i-h3-mdio-mux > > +Required properties of the integrated phy node: > > - clocks: a phandle to the reference clock for the EPHY > > - resets: a phandle to the reset control for the EPHY > > +- phy-is-integrated > > So the last thing you said is that the mux is not the problem > here. Something else is locking up. Did you discover what? > > I really would like phy-is-integrated to go away. > I have found the problem: by enabling ephy clk/reset the timeout does not occur anymore. So we could remove phy-is-integrated by: Moving internal phy clk/reset handling in mdio_mux_syscon_switch_fn() But this means: - getting internalphy node always by manually get internal_mdio/internal_phy (and not by the given phyhandle) - doing some unnecessary tasks (enable/scan/disable) when external_phy is needed Regards
Re: [PATCH v6 05/11] dt-bindings: net: dwmac-sun8i: update documentation about integrated PHY
On Thu, Sep 28, 2017 at 09:37:08AM +0200, Corentin Labbe wrote: > On Wed, Sep 27, 2017 at 04:02:10PM +0200, Andrew Lunn wrote: > > Hi Corentin > > > > > +Required properties for the mdio-mux node: > > > + - compatible = "mdio-mux" > > > > This is too generic. Please add a more specific compatible for this > > particular mux. You can keep "mdio-mux", since that is what the MDIO > > subsystem will look for. > > > > I will add allwinner,sun8i-h3-mdio-mux > > > > +Required properties of the integrated phy node: > > > - clocks: a phandle to the reference clock for the EPHY > > > - resets: a phandle to the reset control for the EPHY > > > +- phy-is-integrated > > > > So the last thing you said is that the mux is not the problem > > here. Something else is locking up. Did you discover what? > > > > I really would like phy-is-integrated to go away. > > > > I have found the problem: by enabling ephy clk/reset the timeout does not > occur anymore. > So we could remove phy-is-integrated by: > Moving internal phy clk/reset handling in mdio_mux_syscon_switch_fn() > But this means: > - getting internalphy node always by manually get internal_mdio/internal_phy > (and not by the given phyhandle) > - doing some unnecessary tasks (enable/scan/disable) when external_phy is > needed > Hello I have get rid of phy-is-integrated, but mdio_mux_syscon_switch_fn need to enable/disable ephy clk/reset. And so access to internal PHY node. But current DT made this ugly: (need to find mdio-mux then internalmdio then internal PHY) Since MAC cannot reset/choose internal MDIO without ephy clk/rst, could we interpret this as thoses clk/rst must be set in emac node. This will simplify a lot the code. Regards
Re: [PATCH net 0/3] net: stmmac: Misc fixes
On Wed, Jan 30, 2019 at 03:54:18PM +0100, Jose Abreu wrote: > Some misc fixes for stmmac targeting -net. > > Cc: Joao Pinto > Cc: David S. Miller > Cc: Giuseppe Cavallaro > Cc: Alexandre Torgue > > Jose Abreu (3): > net: stmmac: Fallback to Platform Data clock in Watchdog conversion > net: stmmac: Send TSO packets always from Queue 0 > net: stmmac: Disable EEE mode earlier in XMIT callback > > drivers/net/ethernet/stmicro/stmmac/stmmac_ethtool.c | 14 ++ > drivers/net/ethernet/stmicro/stmmac/stmmac_main.c| 17 + > include/linux/stmmac.h | 1 + > 3 files changed, 24 insertions(+), 8 deletions(-) > > -- > 2.7.4 > Hello Could you CC linux-ker...@vger.kernel.org when you send patch. (as asked by get_maintainer.pl) By avoiding it, your patchset is not stored on lore nor is handled by all checkbots reading lkml. Thanks Regards
[BUG] net: sungem: device driver frees DMA memory with wrong function
Hello During a boot on a qemu machine, I hit the following problem: [ 21.613659] [ cut here ] [ 21.614039] DMA-API: gem :00:0f.0: device driver frees DMA memory with wrong function [device address=0x185c5402] [size=408 bytes] [mapped as page] [unmapped as single] [ 21.615960] WARNING: CPU: 0 PID: 206 at /linux-next/kernel/dma/debug.c:1085 check_unmap+0x1b0/0xd10 [ 21.616599] Modules linked in: [ 21.617344] CPU: 0 PID: 206 Comm: dhcpcd Not tainted 4.20.0-rc6-next-20181217+ #12 [ 21.617735] NIP: c00ad4e0 LR: c00ad4e0 CTR: c058a710 [ 21.618068] REGS: dfff7cb0 TRAP: 0700 Not tainted (4.20.0-rc6-next-20181217+) [ 21.618404] MSR: 00021032 CR: 28008264 XER: [ 21.618789] [ 21.618789] GPR00: c00ad4e0 dfff7d60 d85924c0 00a8 0102 0101 00fe 5d205b6d [ 21.618789] GPR08: 0007 00fe 22008864 100581b4 dfff7f1c de019508 [ 21.618789] GPR16: de019000 0001 c0a67f00 0004 c0b44018 c0a31fc4 c0b43bdc [ 21.618789] GPR24: 9032 c0dadedc c0db c0da999c c0b43bdc c0c0b178 dfff7de0 de076ce8 [ 21.620219] NIP [c00ad4e0] check_unmap+0x1b0/0xd10 [ 21.620478] LR [c00ad4e0] check_unmap+0x1b0/0xd10 [ 21.620703] Call Trace: [ 21.620963] [dfff7d60] [c00ad4e0] check_unmap+0x1b0/0xd10 (unreliable) [ 21.621379] [dfff7dd0] [c00ae128] debug_dma_unmap_page+0xe8/0x120 [ 21.621656] [dfff7e40] [c05a865c] gem_poll+0x1000/0x18fc [ 21.621863] [dfff7f00] [c071f044] net_rx_action+0x1b8/0x41c [ 21.622242] [dfff7f80] [c08a287c] __do_softirq+0x17c/0x3b0 [ 21.622495] [dfff7ff0] [c0011378] call_do_softirq+0x24/0x3c [ 21.622697] [d86c9c20] [c000724c] do_softirq_own_stack+0x3c/0x7c [ 21.623008] [d86c9c40] [c004e800] do_softirq.part.1+0x64/0x7c [ 21.623292] [d86c9c60] [c004e8d4] __local_bh_enable_ip+0xbc/0x138 [ 21.623526] [d86c9c80] [c071c9b4] __dev_queue_xmit+0x28c/0x874 [ 21.623776] [d86c9cf0] [c083ebe8] packet_snd+0x4f8/0x988 [ 21.624057] [d86c9d80] [c06eddb8] sock_sendmsg+0x20/0x40 [ 21.624410] [d86c9d90] [c06ede94] sock_write_iter+0xbc/0x138 [ 21.624636] [d86c9df0] [c018f50c] do_iter_readv_writev+0x1dc/0x1f4 [ 21.624872] [d86c9e40] [c01925a8] do_iter_write+0xb4/0x350 [ 21.625143] [d86c9e80] [c01928f4] vfs_writev+0x88/0x140 [ 21.625446] [d86c9f00] [c0192a1c] do_writev+0x70/0x104 [ 21.625621] [d86c9f40] [c001912c] ret_from_syscall+0x0/0x38 [ 21.626001] --- interrupt: c01 at 0xfedbd08 [ 21.626001] LR = 0xffbc1f8 [ 21.626357] Instruction dump: [ 21.626719] 7eb5ba14 7e95a214 2b940014 419d0970 92c10008 7efcba14 3c60c0a1 7e649b78 [ 21.627152] 38637cac 80d7043c 90c1000c 4bf9d36d <0fe0> 8261003c 82810040 82a10044 [ 21.627665] ---[ end trace fd53714bd2a5fd06 ]--- After some pr_info, I found that the function triggering this is the pci_unmap_page() in gem_tx(). So clearly this WARNING() is strange since it says "unmapped as single". The qemu is ran with: qemu-system-ppc -machine mac99,via=pmu -nographic -net nic,model=sungem,macaddr=52:54:00:12:34:58 -net tap -m 512 -monitor none -append "console=ttyPZ0 root=/dev/ram0" -kernel vmlinux -initrd rootfs.cpio.gz -drive format=qcow2,file=lava-guest.qcow2,media=disk,id=test,if=ide Regards
Re: [BUG] net: sungem: device driver frees DMA memory with wrong function
On Fri, Dec 28, 2018 at 12:36:21AM -0800, Christoph Hellwig wrote:
> Please try this patch:
>
The error type change to "DMA-API: gem :00:0f.0: device driver failed to
check map error" (I will send patch for fixing this).
Note that I used the patch from your just sent DMA series (since the patch
below is included in).
So you can add my
Tested-by: LABBE Corentin
Thanks
> diff --git a/include/linux/dma-mapping.h b/include/linux/dma-mapping.h
> index a52c6409bdc2..f454e0ed1398 100644
> --- a/include/linux/dma-mapping.h
> +++ b/include/linux/dma-mapping.h
> @@ -284,32 +284,25 @@ static inline void dma_direct_sync_sg_for_cpu(struct
> device *dev,
> }
> #endif
>
> -static inline dma_addr_t dma_map_single_attrs(struct device *dev, void *ptr,
> - size_t size,
> - enum dma_data_direction dir,
> - unsigned long attrs)
> +static inline dma_addr_t dma_map_page_attrs(struct device *dev,
> + struct page *page, size_t offset, size_t size,
> + enum dma_data_direction dir, unsigned long attrs)
> {
> const struct dma_map_ops *ops = get_dma_ops(dev);
> dma_addr_t addr;
>
> BUG_ON(!valid_dma_direction(dir));
> - debug_dma_map_single(dev, ptr, size);
> if (dma_is_direct(ops))
> - addr = dma_direct_map_page(dev, virt_to_page(ptr),
> - offset_in_page(ptr), size, dir, attrs);
> + addr = dma_direct_map_page(dev, page, offset, size, dir, attrs);
> else
> - addr = ops->map_page(dev, virt_to_page(ptr),
> - offset_in_page(ptr), size, dir, attrs);
> - debug_dma_map_page(dev, virt_to_page(ptr),
> -offset_in_page(ptr), size,
> -dir, addr, true);
> + addr = ops->map_page(dev, page, offset, size, dir, attrs);
> + debug_dma_map_page(dev, page, offset, size, dir, addr, false);
> +
> return addr;
> }
>
> -static inline void dma_unmap_single_attrs(struct device *dev, dma_addr_t
> addr,
> - size_t size,
> - enum dma_data_direction dir,
> - unsigned long attrs)
> +static inline void dma_unmap_page_attrs(struct device *dev, dma_addr_t addr,
> + size_t size, enum dma_data_direction dir, unsigned long attrs)
> {
> const struct dma_map_ops *ops = get_dma_ops(dev);
>
> @@ -321,12 +314,6 @@ static inline void dma_unmap_single_attrs(struct device
> *dev, dma_addr_t addr,
> debug_dma_unmap_page(dev, addr, size, dir, true);
> }
>
> -static inline void dma_unmap_page_attrs(struct device *dev, dma_addr_t addr,
> - size_t size, enum dma_data_direction dir, unsigned long attrs)
> -{
> - return dma_unmap_single_attrs(dev, addr, size, dir, attrs);
> -}
> -
> /*
> * dma_maps_sg_attrs returns 0 on error and > 0 on success.
> * It should never return a value < 0.
> @@ -363,25 +350,6 @@ static inline void dma_unmap_sg_attrs(struct device
> *dev, struct scatterlist *sg
> ops->unmap_sg(dev, sg, nents, dir, attrs);
> }
>
> -static inline dma_addr_t dma_map_page_attrs(struct device *dev,
> - struct page *page,
> - size_t offset, size_t size,
> - enum dma_data_direction dir,
> - unsigned long attrs)
> -{
> - const struct dma_map_ops *ops = get_dma_ops(dev);
> - dma_addr_t addr;
> -
> - BUG_ON(!valid_dma_direction(dir));
> - if (dma_is_direct(ops))
> - addr = dma_direct_map_page(dev, page, offset, size, dir, attrs);
> - else
> - addr = ops->map_page(dev, page, offset, size, dir, attrs);
> - debug_dma_map_page(dev, page, offset, size, dir, addr, false);
> -
> - return addr;
> -}
> -
> static inline dma_addr_t dma_map_resource(struct device *dev,
> phys_addr_t phys_addr,
> size_t size,
> @@ -488,6 +456,19 @@ dma_sync_sg_for_device(struct device *dev, struct
> scatterlist *sg,
>
> }
>
> +static inline dma_addr_t dma_map_single_attrs(struct device *dev, void *ptr,
> + size_t size, enum dma_data_direction dir, unsigned long attrs)
> +{
> + return dma_map_page_attrs(dev, virt_to_page(ptr), offset_in_page(ptr),
> + size, dir, attrs);
> +}
> +
> +static inline void dma_unmap_single_attrs(struct device *dev, dma_addr_t
> addr,
> + size_t size, enum dma_data_direction dir, unsigned long attrs)
> +{
> + return dma_unmap_page_attrs(dev, addr, size, dir, attrs);
> +}
> +
> #define dma_map_single(d, a, s, r) dma_map_single_attrs(d, a, s, r, 0)
> #define dma_unmap_single(d, a, s, r) dma_unma
[BUG] net: stmmac: dwmac-sun8i broken in linux-next
Hello
The dwmac-sun8i driver is broken in next-20180515, symptom are no RX and TX
errors as shown by ifconfig:
eth0: flags=4163 mtu 1500
inet 192.168.1.204 netmask 255.255.255.0 broadcast 192.168.1.255
ether 96:75:ff:0d:f6:d8 txqueuelen 1000 (Ethernet)
RX packets 0 bytes 0 (0.0 B)
RX errors 0 dropped 0 overruns 0 frame 0
TX packets 0 bytes 4956 (4.8 KiB)
TX errors 118 dropped 0 overruns 0 carrier 0 collisions 0
Reverting the following commit made the driver working:
4dbbe8dde8485b89bce8bbbe7564337fd7eed69f ("net: stmmac: Add support for U32 TC
filter using Flexible RX Parser")
5f0456b43140af9413397cc11d03d18b9f2fc2fc ("net: stmmac: Implement logic to
automatically select HW Interface")
Note that reverting only 4dbbe8dde8485b89bce8bbbe7564337fd7eed69f lead to crash:
[ 31.385110] Backtrace:
[ 31.387576] [] (stmmac_open) from []
(__dev_open+0xe4/0x180)
[ 31.394972] r10:ed447d04 r9:edc5d010 r8:ef02002c r7:c08670a4 r6:
r5:c0c08488
[ 31.402793] r4:ef02
[ 31.405335] [] (__dev_open) from []
(__dev_change_flags+0x190/0x1e8)
[ 31.413421] r8:1002 r7:c0c08488 r6:1003 r5:0001 r4:ef02
[ 31.420122] [] (__dev_change_flags) from []
(dev_change_flags+0x20/0x50)
[ 31.428555] r9:edc5d010 r8:ed447c18 r7:ef020134 r6: r5:1002
r4:ef02
[ 31.436300] [] (dev_change_flags) from []
(do_setlink+0x28c/0xbdc)
[ 31.444213] r9:edc5d010 r8:ed447c18 r7: r6:c0c08488 r5:ed447b50
r4:ef02
[ 31.451955] [] (do_setlink) from []
(rtnl_newlink+0x54c/0x7a8)
[ 31.459522] r10:ed447d04 r9: r8: r7: r6:
r5:
[ 31.467343] r4:ef02
[ 31.469885] [] (rtnl_newlink) from []
(rtnetlink_rcv_msg+0x38c/0x544)
[ 31.478058] r10:ed447d04 r9: r8:ee242840 r7: r6:edc5d000
r5:c0c08488
[ 31.485879] r4:
[ 31.488422] [] (rtnetlink_rcv_msg) from []
(netlink_rcv_skb+0xc0/0x118)
[ 31.496768] r10:c0c08488 r9: r8:0020 r7:edc5d000 r6:c064466c
r5:c0c08488
[ 31.504589] r4:ee242840
[ 31.507129] [] (netlink_rcv_skb) from []
(rtnetlink_rcv+0x18/0x1c)
[ 31.515042] r8:ed447d60 r7:ee242840 r6:0020 r5:ee37d800 r4:ee5fac00
[ 31.521742] [] (rtnetlink_rcv) from []
(netlink_unicast+0x190/0x1fc)
[ 31.529829] [] (netlink_unicast) from []
(netlink_sendmsg+0x3cc/0x410)
[ 31.538089] r10: r9:0020 r8:014000c0 r7:ee242840 r6:ee37d800
r5:c0c08488
[ 31.545910] r4:ed447f44
[ 31.548452] [] (netlink_sendmsg) from []
(sock_sendmsg+0x1c/0x2c)
[ 31.556279] r10: r9:ed447edc r8: r7:eefce640 r6:
r5:c0c08488
[ 31.564100] r4:ed447f44
[ 31.566640] [] (sock_sendmsg) from []
(___sys_sendmsg+0x250/0x264)
[ 31.574555] [] (___sys_sendmsg) from []
(__sys_sendmsg+0x58/0x94)
[ 31.582382] r10: r9:ed446000 r8:c01011c4 r7:eefce640 r6:
r5:bec25150
[ 31.590203] r4:c0c08488
[ 31.592743] [] (__sys_sendmsg) from []
(sys_sendmsg+0x14/0x18)
[ 31.600307] r7:0128 r6:bec2d17c r5:bec25144 r4:00093ee0
[ 31.605969] [] (sys_sendmsg) from []
(ret_fast_syscall+0x0/0x28)
[ 31.613704] Exception stack(0xed447fa8 to 0xed447ff0)
[ 31.618756] 7fa0: 00093ee0 bec25144 0003 bec25150
85ce
[ 31.626929] 7fc0: 00093ee0 bec25144 bec2d17c 0128 000942a8 5afc783a
00094000 bec25150
[ 31.635099] 7fe0: bec250f0 012c b6e10b5c
[ 31.640152] Code: e59a261c e59a013c e50b306c e592300c (e593300c)
[ 31.646632] ---[ end trace 407964b7deb937bf ]---
For the moment, I stil didnt find the issue.
What to we do now ? do you want that I send revert patchs ?
Regards
Re: [PATCH v3 net-next 00/12] net: stmmac: Clean-up and tune-up
On Fri, May 18, 2018 at 02:55:57PM +0100, Jose Abreu wrote:
> This targets to uniformize the handling of the different GMAC versions in
> stmmac_main.c file and also tune-up the HW.
>
> Currently there are some if/else conditions in the main source file which
> calls different callbacks depending on the ID of GMAC.
>
> With the introducion of a generic HW interface handling which automatically
> selects the GMAC callbacks to be used, it is now unpleasant to see if
> conditions in the main code because this should be completely agnostic of the
> GMAC version.
>
> This series removes most of these conditions. There are some if conditions
> that remain untouched but the callbacks handling are now uniformized.
>
> Tested in GMAC5, hope I didn't break any previous versions.
>
> Please check [1] for performance analisys of patches 3-12.
>
> ---
> David,
>
> This will probably generate a merge conflict with [2] (which was not merged
> yet). I'm waiting for Corentin input and then, if this series is merged
> before, I will rebase [2]. Or the other way around if you prefer :D
>
> Thanks
> ---
>
> Cc: David S. Miller
> Cc: Joao Pinto
> Cc: Vitor Soares
> Cc: Giuseppe Cavallaro
> Cc: Alexandre Torgue
>
> [1] https://marc.info/?l=linux-netdev&m=152656352607905&w=2
> [2] https://patchwork.ozlabs.org/patch/915286/
>
> Jose Abreu (12):
> net: stmmac: Enable OSP for GMAC4
> net: stmmac: Do not keep rearming the coalesce timer in stmmac_xmit
> net: stmmac: Let descriptor code set skbuff address
> net: stmmac: Let descriptor code clear the descriptor
> net: stmmac: Uniformize the use of dma_{rx/tx}_mode callbacks
> net: stmmac: Remove uneeded checks for GMAC version
> net: stmmac: Move PTP and MMC base address calculation to hwif.c
> net: stmmac: Uniformize the use of dma_init_* callbacks
> net: stmmac: Remove uneeded check for GMAC version in stmmac_xmit
> net: stmmac: Uniformize set_rx_owner()
> net: stmmac: Let descriptor code get skbuff address
> net: stmmac: Remove if condition by taking advantage of hwif return
> code
>
> drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c | 82 +---
> .../net/ethernet/stmicro/stmmac/dwmac1000_dma.c| 92 ++
> drivers/net/ethernet/stmicro/stmmac/dwmac100_dma.c | 35 +++--
> drivers/net/ethernet/stmicro/stmmac/dwmac4_descs.c | 34 +++-
> drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c |7 +-
> drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.h |1 -
> drivers/net/ethernet/stmicro/stmmac/enh_desc.c | 20 ++-
> drivers/net/ethernet/stmicro/stmmac/hwif.c | 34
> drivers/net/ethernet/stmicro/stmmac/hwif.h | 27 ++-
> drivers/net/ethernet/stmicro/stmmac/norm_desc.c| 20 ++-
> drivers/net/ethernet/stmicro/stmmac/stmmac.h |1 +
> drivers/net/ethernet/stmicro/stmmac/stmmac_main.c | 198
> +++-
> 12 files changed, 323 insertions(+), 228 deletions(-)
>
>
Hello
You didnt have put in CC linux-ker...@vger.kernel.org as required by
get_maintener.pl letting more people to see this series.
Since this series touch dwmac-sun8i.c you should have also added Chen-Yu
Tsai/Maxime Ripard (as also asked by get_maintainer).
Regards
Re: [PATCH net-next] net: stmmac: Populate missing callbacks in HWIF initialization
On Thu, May 17, 2018 at 10:57:28AM +0100, Jose Abreu wrote:
> Some HW specific setusp, like sun8i, do not populate all the necessary
> callbacks, which is what HWIF helpers were expecting.
>
> Fix this by always trying to get the generic helpers and populate them
> if they were not previously populated by HW specific setup.
>
> Signed-off-by: Jose Abreu
> Fixes: 5f0456b43140 ("net: stmmac: Implement logic to automatically
> select HW Interface")
> Reported-by: Corentin Labbe
> Cc: Corentin Labbe
> Cc: David S. Miller
> Cc: Joao Pinto
> Cc: Giuseppe Cavallaro
> Cc: Alexandre Torgue
> ---
> Hi Corentin,
>
> Please check if this patch makes sun8i work again.
>
> Thanks and Best Regards,
> Jose Miguel Abreu
> ---
Hello
Tested-by: Corentin Labbe
Thanks for the quick fix.
Note that this patch conflict with your next v3 serie
Regards
Re: [PATCH v3 net-next 00/12] net: stmmac: Clean-up and tune-up
On Fri, May 18, 2018 at 03:23:44PM +0100, Jose Abreu wrote:
> Hi Corentin,
>
> On 18-05-2018 15:12, Corentin Labbe wrote:
> > On Fri, May 18, 2018 at 02:55:57PM +0100, Jose Abreu wrote:
> >> This targets to uniformize the handling of the different GMAC versions in
> >> stmmac_main.c file and also tune-up the HW.
> >>
> >> Currently there are some if/else conditions in the main source file which
> >> calls different callbacks depending on the ID of GMAC.
> >>
> >> With the introducion of a generic HW interface handling which automatically
> >> selects the GMAC callbacks to be used, it is now unpleasant to see if
> >> conditions in the main code because this should be completely agnostic of
> >> the
> >> GMAC version.
> >>
> >> This series removes most of these conditions. There are some if conditions
> >> that remain untouched but the callbacks handling are now uniformized.
> >>
> >> Tested in GMAC5, hope I didn't break any previous versions.
> >>
> >> Please check [1] for performance analisys of patches 3-12.
> >>
> >> ---
> >> David,
> >>
> >> This will probably generate a merge conflict with [2] (which was not merged
> >> yet). I'm waiting for Corentin input and then, if this series is merged
> >> before, I will rebase [2]. Or the other way around if you prefer :D
> >>
> >> Thanks
> >> ---
> >>
> >> Cc: David S. Miller
> >> Cc: Joao Pinto
> >> Cc: Vitor Soares
> >> Cc: Giuseppe Cavallaro
> >> Cc: Alexandre Torgue
> >>
> >> [1]
> >> https://urldefense.proofpoint.com/v2/url?u=https-3A__marc.info_-3Fl-3Dlinux-2Dnetdev-26m-3D152656352607905-26w-3D2&d=DwIBAg&c=DPL6_X_6JkXFx7AXWqB0tg&r=WHDsc6kcWAl4i96Vm5hJ_19IJiuxx_p_Rzo2g-uHDKw&m=a7bgrSQpisaMSa5fT-je94smZ_TM7QTxNFKqkvI5Nns&s=Tr23Xj_UCR_PaJp8AYiy18hfhbILnsaCsKDT5_4m2z4&e=
> >> [2]
> >> https://urldefense.proofpoint.com/v2/url?u=https-3A__patchwork.ozlabs.org_patch_915286_&d=DwIBAg&c=DPL6_X_6JkXFx7AXWqB0tg&r=WHDsc6kcWAl4i96Vm5hJ_19IJiuxx_p_Rzo2g-uHDKw&m=a7bgrSQpisaMSa5fT-je94smZ_TM7QTxNFKqkvI5Nns&s=Q0SV-ZR35zIJWjiaLNXqlOWchppQ2CsO-Fh-BFCjCB8&e=
> >>
> >> Jose Abreu (12):
> >> net: stmmac: Enable OSP for GMAC4
> >> net: stmmac: Do not keep rearming the coalesce timer in stmmac_xmit
> >> net: stmmac: Let descriptor code set skbuff address
> >> net: stmmac: Let descriptor code clear the descriptor
> >> net: stmmac: Uniformize the use of dma_{rx/tx}_mode callbacks
> >> net: stmmac: Remove uneeded checks for GMAC version
> >> net: stmmac: Move PTP and MMC base address calculation to hwif.c
> >> net: stmmac: Uniformize the use of dma_init_* callbacks
> >> net: stmmac: Remove uneeded check for GMAC version in stmmac_xmit
> >> net: stmmac: Uniformize set_rx_owner()
> >> net: stmmac: Let descriptor code get skbuff address
> >> net: stmmac: Remove if condition by taking advantage of hwif return
> >> code
> >>
> >> drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c | 82 +---
> >> .../net/ethernet/stmicro/stmmac/dwmac1000_dma.c| 92 ++
> >> drivers/net/ethernet/stmicro/stmmac/dwmac100_dma.c | 35 +++--
> >> drivers/net/ethernet/stmicro/stmmac/dwmac4_descs.c | 34 +++-
> >> drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c |7 +-
> >> drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.h |1 -
> >> drivers/net/ethernet/stmicro/stmmac/enh_desc.c | 20 ++-
> >> drivers/net/ethernet/stmicro/stmmac/hwif.c | 34
> >> drivers/net/ethernet/stmicro/stmmac/hwif.h | 27 ++-
> >> drivers/net/ethernet/stmicro/stmmac/norm_desc.c| 20 ++-
> >> drivers/net/ethernet/stmicro/stmmac/stmmac.h |1 +
> >> drivers/net/ethernet/stmicro/stmmac/stmmac_main.c | 198
> >> +++-
> >> 12 files changed, 323 insertions(+), 228 deletions(-)
> >>
> >>
> > Hello
> >
> > You didnt have put in CC linux-ker...@vger.kernel.org as required by
> > get_maintener.pl letting more people to see this series.
> > Since this series touch dwmac-sun8i.c you should have also added Chen-Yu
> > Tsai/Maxime Ripard (as also asked by get_maintainer).
>
> Usually I just cc according to MAINTAINERS file but thanks for
> noticing. Added in cc now.
>
./scripts/get_maintainer.pl does this for you (and it use MAINTAINERS).
You have to use it at least, since it handle regex that could be easily unseen
like for dwmac-sun8i.
[PATCH] net: stmmac: dwmac-sun8i: fix allwinner,leds-active-low handling
The driver expect "allwinner,leds-active-low" to be in PHY node, but
the binding doc expect it to be in MAC node.
Since all board DT use it also in MAC node, the driver need to search
allwinner,leds-active-low in MAC node.
Signed-off-by: Corentin Labbe
---
drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
index e5ff734d4f9b..9eb7f65d8000 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
@@ -808,8 +808,7 @@ static int sun8i_dwmac_set_syscon(struct stmmac_priv *priv)
val, reg);
if (gmac->variant->soc_has_internal_phy) {
- if (of_property_read_bool(priv->plat->phy_node,
- "allwinner,leds-active-low"))
+ if (of_property_read_bool(node, "allwinner,leds-active-low"))
reg |= H3_EPHY_LED_POL;
else
reg &= ~H3_EPHY_LED_POL;
--
2.13.6
Re: [PATCH] net: stmmac: dwmac-sun8i: fix allwinner,leds-active-low handling
On Tue, Nov 28, 2017 at 06:38:26PM +0100, Andrew Lunn wrote: > On Tue, Nov 28, 2017 at 05:48:22PM +0100, Corentin Labbe wrote: > > The driver expect "allwinner,leds-active-low" to be in PHY node, but > > the binding doc expect it to be in MAC node. > > > > Since all board DT use it also in MAC node, the driver need to search > > allwinner,leds-active-low in MAC node. > > Hi Corentin > > I'm having trouble working out how this worked before. This is code > you moved around, when adding external/internal MDIOs. But the very > first version of this driver code used priv->plat->phy_node. Did that > somehow point to the MAC node when the internal PHY is used? Or has it > been broken all the time? > Hello Since this feature control only when the activity LED need to blink, nobody see that it was broken. It is indepedant of other internal PHY stuff. Regards
[PATCH] net: cadence: macb: disable NAPI on error
When the PHY is not working, the macb driver crash on a second try to
setup it.
[ 78.545994] macb e000b000.ethernet eth0: Could not attach PHY (-19)
ifconfig: SIOCSIFFLAGS: No such device
[ 78.655457] [ cut here ]
[ 78.656014] kernel BUG at /linux-next/include/linux/netdevice.h:521!
[ 78.656504] Internal error: Oops - BUG: 0 [#1] SMP ARM
[ 78.657079] Modules linked in:
[ 78.657795] CPU: 0 PID: 122 Comm: ifconfig Not tainted 5.7.0-next-20200609 #1
[ 78.658202] Hardware name: Xilinx Zynq Platform
[ 78.659632] PC is at macb_open+0x220/0x294
[ 78.660160] LR is at 0x0
[ 78.660373] pc : []lr : [<>]psr: 6013
[ 78.660716] sp : c89ffd70 ip : c8a28800 fp : c199bac0
[ 78.661040] r10: r9 : c8838540 r8 : c8838568
[ 78.661362] r7 : 0001 r6 : c8838000 r5 : c883c000 r4 :
[ 78.661724] r3 : 0010 r2 : r1 : r0 :
[ 78.662187] Flags: nZCv IRQs on FIQs on Mode SVC_32 ISA ARM Segment none
[ 78.662635] Control: 10c5387d Table: 08b64059 DAC: 0051
[ 78.663035] Process ifconfig (pid: 122, stack limit = 0x(ptrval))
[ 78.663476] Stack: (0xc89ffd70 to 0xc8a0)
[ 78.664121] fd60: c89fe000
c8838000 c89fe000
[ 78.664866] fd80: c11ff9ac c8838028 c0de6f2c
0001 c1804eec
[ 78.665579] fda0: c19b8178 c8838000 ca760866 c8838000 0001
1043 c89fe000
[ 78.666355] fdc0: 1002 c0de72f4 c89fe000 c0de8dc0 8914 c89fe000
c199bac0 ca760866
[ 78.667111] fde0: c89ffddc c8838000 1002 c8838138 c881010c
8914 c0de7364
[ 78.667862] fe00: c89ffe70 c89fe000 c881010c c0e8bd48
0003
[ 78.668601] fe20: c8838000 c8810100 39c1118f 00039c11 c89a0960 1043
000a26d0
[ 78.669343] fe40: b6f43000 ca760866 c89a0960 0051 befe6c50 8914
c8b2a3c0 befe6c50
[ 78.670086] fe60: 0003 ee610500 c0e8ef58 30687465
[ 78.670865] fe80: 1043 000a26d0 b6f43000 c89a0600 ee40ae7c
c8870d00 c0ddabf4
[ 78.671593] fea0: c89ffeec c0ddabf4 c89ffeec c199bac0 8913 c0ddac48
c89ffeec c89fe000
[ 78.672324] fec0: befe6c50 ca760866 befe6c50 8914 c89fe000 befe6c50
c8b2a3c0 c0dc00e4
[ 78.673088] fee0: c89a0480 0201 0cc0 30687465
1002
[ 78.673822] ff00: 000a26d0 b6f43000 ca760866 8914 c8b2a3c0
000a0ec4 c8b2a3c0
[ 78.674576] ff20: befe6c50 c04b21bc 000d5004 0817 c89a0480 c0315f94
0003
[ 78.675415] ff40: c19a2bc8 c8a3cc00 c89fe000 0255
000d5000
[ 78.676182] ff60: 000f6000 c180b2a0 0817 c0315e64 000d5004 c89fffb0
b6ec0c30 ca760866
[ 78.676928] ff80: 000b609b befe6c50 000a0ec4 0036 c03002c4
c89fe000 0036
[ 78.677673] ffa0: c03000c0 000b609b befe6c50 0003 8914
befe6c50 000b609b
[ 78.678415] ffc0: 000b609b befe6c50 000a0ec4 0036 befe6e0c befe6f1a
000d5150
[ 78.679154] ffe0: 000d41e4 befe6bf4 00019648 b6e4509c 2010 0003
[ 78.681059] [] (macb_open) from []
(__dev_open+0xd0/0x154)
[ 78.681571] [] (__dev_open) from []
(__dev_change_flags+0x16c/0x1c4)
[ 78.682015] [] (__dev_change_flags) from []
(dev_change_flags+0x18/0x48)
[ 78.682493] [] (dev_change_flags) from []
(devinet_ioctl+0x5e4/0x75c)
[ 78.682945] [] (devinet_ioctl) from []
(inet_ioctl+0x1f0/0x3b4)
[ 78.683381] [] (inet_ioctl) from []
(sock_ioctl+0x39c/0x664)
[ 78.683818] [] (sock_ioctl) from []
(ksys_ioctl+0x2d8/0x9c0)
[ 78.684343] [] (ksys_ioctl) from []
(ret_fast_syscall+0x0/0x54)
[ 78.684789] Exception stack(0xc89fffa8 to 0xc890)
[ 78.685346] ffa0: 000b609b befe6c50 0003 8914
befe6c50 000b609b
[ 78.686106] ffc0: 000b609b befe6c50 000a0ec4 0036 befe6e0c befe6f1a
000d5150
[ 78.686710] ffe0: 000d41e4 befe6bf4 00019648 b6e4509c
[ 78.687582] Code: 9a03 e5983078 e3130001 1aef (e7f001f2)
[ 78.688788] ---[ end trace e3f2f6ab69754eae ]---
This is due to NAPI left enabled if macb_phylink_connect() fail.
Fixes: 7897b071ac3b ("net: macb: convert to phylink")
Signed-off-by: Corentin Labbe
---
drivers/net/ethernet/cadence/macb_main.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/net/ethernet/cadence/macb_main.c
b/drivers/net/ethernet/cadence/macb_main.c
index 36290a8e2a84..5b9d7c60eebc 100644
--- a/drivers/net/ethernet/cadence/macb_main.c
+++ b/drivers/net/ethernet/cadence/macb_main.c
@@ -2558,13 +2558,16 @@ static int macb_open(struct net_device *dev)
err = macb_phylink_connect(bp);
if (err)
- goto pm_exit;
+ goto napi_exit;
netif_tx_start_all_queues(dev);
if (bp->ptp_info)
bp->ptp_info->ptp_init(dev);
+napi_exit:
+ for (
Re: [linux-sunxi] [PATCH 4/5] arm64: allwinner: h6: add EMAC device nodes
On Sun, Jul 22, 2018 at 01:39:54PM +0800, Icenowy Zheng wrote:
> Allwinner H6 SoC has an EMAC like the one in A64.
>
> Add device tree nodes for the H6 DTSI file.
>
> Signed-off-by: Icenowy Zheng
> ---
> arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 30
> 1 file changed, 30 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
> b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
> index 3ab6cf0256ca..c65311de301a 100644
> --- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
> +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
> @@ -149,6 +149,14 @@
> interrupt-controller;
> #interrupt-cells = <3>;
>
> + ext_rgmii_pins: rgmii_pins {
> + pins = "PD0", "PD1", "PD2", "PD3", "PD4",
> +"PD5", "PD7", "PD8", "PD9", "PD10",
> +"PD11", "PD12", "PD13", "PD19", "PD20";
> + function = "emac";
> + drive-strength = <40>;
> + };
> +
> mmc0_pins: mmc0-pins {
> pins = "PF0", "PF1", "PF2", "PF3",
> "PF4", "PF5";
> @@ -258,6 +266,28 @@
> status = "disabled";
> };
>
> + emac: ethernet@502 {
> + compatible = "allwinner,sun50i-a64-emac",
> + "allwinner,sun50i-h6-emac";
> + syscon = <&syscon>;
> + reg = <0x0502 0x1>;
> + interrupts = ;
> + interrupt-names = "macirq";
> + resets = <&ccu RST_BUS_EMAC>;
> + reset-names = "stmmaceth";
> + clocks = <&ccu CLK_BUS_EMAC>;
> + clock-names = "stmmaceth";
> + status = "disabled";
> + #address-cells = <1>;
> + #size-cells = <0>;
#address-cells and #size-cells is unnecessary in emac node.
Regards
Re: [PATCH v6 05/21] net-next: stmmac: Add dwmac-sun8i
On Tue, Jun 27, 2017 at 04:11:21PM +0800, Chen-Yu Tsai wrote: > On Tue, Jun 27, 2017 at 4:05 PM, Corentin Labbe > wrote: > > On Mon, Jun 26, 2017 at 01:18:23AM +0100, André Przywara wrote: > >> On 31/05/17 08:18, Corentin Labbe wrote: > >> > The dwmac-sun8i is a heavy hacked version of stmmac hardware by > >> > allwinner. > >> > In fact the only common part is the descriptor management and the first > >> > register function. > >> > >> Hi, > >> > >> I know I am a bit late with this, but while adapting the U-Boot driver > >> to the new binding I was wondering about the internal PHY detection: > >> > >> > >> So here you seem to deduce the usage of the internal PHY by the PHY > >> interface specified in the DT (MII = internal, RGMII = external). > >> I think I raised this question before, but isn't it perfectly legal for > >> a board to use MII with an external PHY even on those SoCs that feature > >> an internal PHY? > >> On the first glance that does not make too much sense, but apart from > >> not being the correct binding to describe all of the SoCs features I see > >> two scenarios: > >> 1) A board vendor might choose to not use the internal PHY because it > >> has bugs, lacks features (configurability) or has other issues. For > >> instance I have heard reports that the internal PHY makes the SoC go > >> rather hot, possibly limiting the CPU frequency. By using an external > >> MII PHY (which are still cheaper than RGMII PHYs) this can be avoided. > >> 2) A PHY does not necessarily need to be directly connected to > >> magnetics. Indeed quite some boards use (RG)MII to connect to a switch > >> IC or some other network circuitry, for instance fibre connectors. > >> > >> So I was wondering if we would need an explicit: > >> allwinner,use-internal-phy; > >> boolean DT property to signal the usage of the internal PHY? > >> Alternatively we could go with the negative version: > >> allwinner,disable-internal-phy; > >> > >> Or what about introducing a new "allwinner,internal-mii-phy" compatible > >> string for the *PHY* node and use that? > >> > >> I just want to avoid that we introduce a binding that causes us > >> headaches later. I think we can still fix this with a followup patch > >> before the driver and its binding hit a release kernel. > >> > >> Cheers, > >> Andre. > >> > > > > I just see some patch, where "phy-mode = internal" is valid. > > I will try to find a way to use it > > Can you provide a link? https://lkml.org/lkml/2017/6/23/479 > > I'm not a fan of using phy-mode for this. There's no guarantee what > mode the internal PHY uses. That's what phy-mode is for. For each soc the internal PHY mode is know and setted in emac_variant/internal_phy So its not a problem. Patch comming soon
Re: [PATCH v6 05/21] net-next: stmmac: Add dwmac-sun8i
On Mon, Jun 26, 2017 at 01:18:23AM +0100, André Przywara wrote: > On 31/05/17 08:18, Corentin Labbe wrote: > > The dwmac-sun8i is a heavy hacked version of stmmac hardware by > > allwinner. > > In fact the only common part is the descriptor management and the first > > register function. > > Hi, > > I know I am a bit late with this, but while adapting the U-Boot driver > to the new binding I was wondering about the internal PHY detection: > > > So here you seem to deduce the usage of the internal PHY by the PHY > interface specified in the DT (MII = internal, RGMII = external). > I think I raised this question before, but isn't it perfectly legal for > a board to use MII with an external PHY even on those SoCs that feature > an internal PHY? > On the first glance that does not make too much sense, but apart from > not being the correct binding to describe all of the SoCs features I see > two scenarios: > 1) A board vendor might choose to not use the internal PHY because it > has bugs, lacks features (configurability) or has other issues. For > instance I have heard reports that the internal PHY makes the SoC go > rather hot, possibly limiting the CPU frequency. By using an external > MII PHY (which are still cheaper than RGMII PHYs) this can be avoided. > 2) A PHY does not necessarily need to be directly connected to > magnetics. Indeed quite some boards use (RG)MII to connect to a switch > IC or some other network circuitry, for instance fibre connectors. > > So I was wondering if we would need an explicit: > allwinner,use-internal-phy; > boolean DT property to signal the usage of the internal PHY? > Alternatively we could go with the negative version: > allwinner,disable-internal-phy; > > Or what about introducing a new "allwinner,internal-mii-phy" compatible > string for the *PHY* node and use that? > > I just want to avoid that we introduce a binding that causes us > headaches later. I think we can still fix this with a followup patch > before the driver and its binding hit a release kernel. > > Cheers, > Andre. > I just see some patch, where "phy-mode = internal" is valid. I will try to find a way to use it Regards
[PATCH 5/6] arm: sun8i: nanopi-neo: use internal phy-mode
Since the PHY used is internal, simply set phy-mode as internal.
Signed-off-by: Corentin Labbe
---
arch/arm/boot/dts/sun8i-h3-nanopi-neo.dts | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/sun8i-h3-nanopi-neo.dts
b/arch/arm/boot/dts/sun8i-h3-nanopi-neo.dts
index 78f6c24952dd..5c5ba806e2f1 100644
--- a/arch/arm/boot/dts/sun8i-h3-nanopi-neo.dts
+++ b/arch/arm/boot/dts/sun8i-h3-nanopi-neo.dts
@@ -49,7 +49,7 @@
&emac {
phy-handle = <&int_mii_phy>;
- phy-mode = "mii";
+ phy-mode = "internal";
allwinner,leds-active-low;
status = "okay";
};
--
2.13.0
[PATCH 3/6] arm: sun8i: orangepi-zero: use internal phy-mode
Since the PHY used is internal, simply set phy-mode as internal.
Signed-off-by: Corentin Labbe
---
arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts
b/arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts
index 6713d0f2b3f4..7c154b845baa 100644
--- a/arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts
+++ b/arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts
@@ -106,7 +106,7 @@
&emac {
phy-handle = <&int_mii_phy>;
- phy-mode = "mii";
+ phy-mode = "internal";
allwinner,leds-active-low;
status = "okay";
};
--
2.13.0
[PATCH 6/6] arm: sun8i: orangepi-2: use internal phy-mode
Since the PHY used is internal, simply set phy-mode as internal.
Signed-off-by: Corentin Labbe
---
arch/arm/boot/dts/sun8i-h3-orangepi-2.dts | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts
b/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts
index 17cdeae19c6f..a2a2b11dfeed 100644
--- a/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts
+++ b/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts
@@ -120,7 +120,7 @@
&emac {
phy-handle = <&int_mii_phy>;
- phy-mode = "mii";
+ phy-mode = "internal";
allwinner,leds-active-low;
status = "okay";
};
--
2.13.0
[PATCH 4/6] arm: sun8i: orangepi-one: use internal phy-mode
Since the PHY used is internal, simply set phy-mode as internal.
Signed-off-by: Corentin Labbe
---
arch/arm/boot/dts/sun8i-h3-orangepi-one.dts | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-one.dts
b/arch/arm/boot/dts/sun8i-h3-orangepi-one.dts
index 6880268e8b87..27e7ef4e42f2 100644
--- a/arch/arm/boot/dts/sun8i-h3-orangepi-one.dts
+++ b/arch/arm/boot/dts/sun8i-h3-orangepi-one.dts
@@ -100,7 +100,7 @@
&emac {
phy-handle = <&int_mii_phy>;
- phy-mode = "mii";
+ phy-mode = "internal";
allwinner,leds-active-low;
status = "okay";
};
--
2.13.0
[PATCH 1/6] net: stmmac: support future possible different internal phy mode
The current way to find if the phy is internal is to compare DT phy-mode
and emac_variant/internal_phy.
But it will negate a possible future SoC where an external PHY use the
same phy mode than the internal one.
By using phy-mode = "internal" we permit to have an external PHY with
the same mode than the internal one.
Reported-by: André Przywara
Signed-off-by: Corentin Labbe
---
drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c | 10 +++---
1 file changed, 7 insertions(+), 3 deletions(-)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
index fffd6d5fc907..6c2d1da05588 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
@@ -638,7 +638,7 @@ static int sun8i_dwmac_set_syscon(struct stmmac_priv *priv)
{
struct sunxi_priv_data *gmac = priv->plat->bsp_priv;
struct device_node *node = priv->device->of_node;
- int ret;
+ int ret, phy_interface;
u32 reg, val;
regmap_read(gmac->regmap, SYSCON_EMAC_REG, &val);
@@ -718,7 +718,11 @@ static int sun8i_dwmac_set_syscon(struct stmmac_priv *priv)
if (gmac->variant->support_rmii)
reg &= ~SYSCON_RMII_EN;
- switch (priv->plat->interface) {
+ phy_interface = priv->plat->interface;
+ /* if PHY is internal, select the mode (xMII) used by the SoC */
+ if (gmac->use_internal_phy)
+ phy_interface = gmac->variant->internal_phy;
+ switch (phy_interface) {
case PHY_INTERFACE_MODE_MII:
/* default */
break;
@@ -932,7 +936,7 @@ static int sun8i_dwmac_probe(struct platform_device *pdev)
}
plat_dat->interface = of_get_phy_mode(dev->of_node);
- if (plat_dat->interface == gmac->variant->internal_phy) {
+ if (plat_dat->interface == PHY_INTERFACE_MODE_INTERNAL) {
dev_info(&pdev->dev, "Will use internal PHY\n");
gmac->use_internal_phy = true;
gmac->ephy_clk = of_clk_get(plat_dat->phy_node, 0);
--
2.13.0
[PATCH 2/6] arm: sun8i: orangepipc: use internal phy-mode
Since the PHY used is internal, simply set phy-mode as internal.
Signed-off-by: Corentin Labbe
---
arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts
b/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts
index f5f0f15a2088..94edeb889e55 100644
--- a/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts
+++ b/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts
@@ -120,7 +120,7 @@
&emac {
phy-handle = <&int_mii_phy>;
- phy-mode = "mii";
+ phy-mode = "internal";
allwinner,leds-active-low;
status = "okay";
};
--
2.13.0
Re: [PATCH v6 05/21] net-next: stmmac: Add dwmac-sun8i
On Tue, Jun 27, 2017 at 11:33:56AM +0100, Andre Przywara wrote: > Hi, > > On 27/06/17 11:23, Icenowy Zheng wrote: > > > > > > 于 2017年6月27日 GMT+08:00 下午6:15:58, Andre Przywara > > 写到: > >> Hi, > >> > >> On 27/06/17 10:41, Maxime Ripard wrote: > >>> On Tue, Jun 27, 2017 at 10:02:45AM +0100, Andre Przywara wrote: > >>>> Hi, > >>>> > >>>> (CC:ing some people from that Rockchip dmwac series) > >>>> > >>>> On 27/06/17 09:21, Corentin Labbe wrote: > >>>>> On Tue, Jun 27, 2017 at 04:11:21PM +0800, Chen-Yu Tsai wrote: > >>>>>> On Tue, Jun 27, 2017 at 4:05 PM, Corentin Labbe > >>>>>> wrote: > >>>>>>> On Mon, Jun 26, 2017 at 01:18:23AM +0100, André Przywara wrote: > >>>>>>>> On 31/05/17 08:18, Corentin Labbe wrote: > >>>>>>>>> The dwmac-sun8i is a heavy hacked version of stmmac hardware by > >>>>>>>>> allwinner. > >>>>>>>>> In fact the only common part is the descriptor management and > >> the first > >>>>>>>>> register function. > >>>>>>>> > >>>>>>>> Hi, > >>>>>>>> > >>>>>>>> I know I am a bit late with this, but while adapting the U-Boot > >> driver > >>>>>>>> to the new binding I was wondering about the internal PHY > >> detection: > >>>>>>>> > >>>>>>>> > >>>>>>>> So here you seem to deduce the usage of the internal PHY by the > >> PHY > >>>>>>>> interface specified in the DT (MII = internal, RGMII = > >> external). > >>>>>>>> I think I raised this question before, but isn't it perfectly > >> legal for > >>>>>>>> a board to use MII with an external PHY even on those SoCs that > >> feature > >>>>>>>> an internal PHY? > >>>>>>>> On the first glance that does not make too much sense, but apart > >> from > >>>>>>>> not being the correct binding to describe all of the SoCs > >> features I see > >>>>>>>> two scenarios: > >>>>>>>> 1) A board vendor might choose to not use the internal PHY > >> because it > >>>>>>>> has bugs, lacks features (configurability) or has other issues. > >> For > >>>>>>>> instance I have heard reports that the internal PHY makes the > >> SoC go > >>>>>>>> rather hot, possibly limiting the CPU frequency. By using an > >> external > >>>>>>>> MII PHY (which are still cheaper than RGMII PHYs) this can be > >> avoided. > >>>>>>>> 2) A PHY does not necessarily need to be directly connected to > >>>>>>>> magnetics. Indeed quite some boards use (RG)MII to connect to a > >> switch > >>>>>>>> IC or some other network circuitry, for instance fibre > >> connectors. > >>>>>>>> > >>>>>>>> So I was wondering if we would need an explicit: > >>>>>>>> allwinner,use-internal-phy; > >>>>>>>> boolean DT property to signal the usage of the internal PHY? > >>>>>>>> Alternatively we could go with the negative version: > >>>>>>>> allwinner,disable-internal-phy; > >>>>>>>> > >>>>>>>> Or what about introducing a new "allwinner,internal-mii-phy" > >> compatible > >>>>>>>> string for the *PHY* node and use that? > >>>>>>>> > >>>>>>>> I just want to avoid that we introduce a binding that causes us > >>>>>>>> headaches later. I think we can still fix this with a followup > >> patch > >>>>>>>> before the driver and its binding hit a release kernel. > >>>>>>>> > >>>>>>>> Cheers, > >>>>>>>> Andre. > >>>>>>>> > >>>>>>> > >>>>>>> I just see some patch, where "phy-mode = internal" is valid. > >>>>>>> I will try to find a way to u
Re: [PATCH v6 05/21] net-next: stmmac: Add dwmac-sun8i
On Tue, Jun 27, 2017 at 07:29:37PM +0200, Maxime Ripard wrote: > On Tue, Jun 27, 2017 at 02:37:48PM +0200, Corentin Labbe wrote: > > On Tue, Jun 27, 2017 at 11:33:56AM +0100, Andre Przywara wrote: > > > Hi, > > > > > > On 27/06/17 11:23, Icenowy Zheng wrote: > > > > > > > > > > > > 于 2017年6月27日 GMT+08:00 下午6:15:58, Andre Przywara > > > > 写到: > > > >> Hi, > > > >> > > > >> On 27/06/17 10:41, Maxime Ripard wrote: > > > >>> On Tue, Jun 27, 2017 at 10:02:45AM +0100, Andre Przywara wrote: > > > >>>> Hi, > > > >>>> > > > >>>> (CC:ing some people from that Rockchip dmwac series) > > > >>>> > > > >>>> On 27/06/17 09:21, Corentin Labbe wrote: > > > >>>>> On Tue, Jun 27, 2017 at 04:11:21PM +0800, Chen-Yu Tsai wrote: > > > >>>>>> On Tue, Jun 27, 2017 at 4:05 PM, Corentin Labbe > > > >>>>>> wrote: > > > >>>>>>> On Mon, Jun 26, 2017 at 01:18:23AM +0100, André Przywara wrote: > > > >>>>>>>> On 31/05/17 08:18, Corentin Labbe wrote: > > > >>>>>>>>> The dwmac-sun8i is a heavy hacked version of stmmac hardware by > > > >>>>>>>>> allwinner. > > > >>>>>>>>> In fact the only common part is the descriptor management and > > > >> the first > > > >>>>>>>>> register function. > > > >>>>>>>> > > > >>>>>>>> Hi, > > > >>>>>>>> > > > >>>>>>>> I know I am a bit late with this, but while adapting the U-Boot > > > >> driver > > > >>>>>>>> to the new binding I was wondering about the internal PHY > > > >> detection: > > > >>>>>>>> > > > >>>>>>>> > > > >>>>>>>> So here you seem to deduce the usage of the internal PHY by the > > > >> PHY > > > >>>>>>>> interface specified in the DT (MII = internal, RGMII = > > > >> external). > > > >>>>>>>> I think I raised this question before, but isn't it perfectly > > > >> legal for > > > >>>>>>>> a board to use MII with an external PHY even on those SoCs that > > > >> feature > > > >>>>>>>> an internal PHY? > > > >>>>>>>> On the first glance that does not make too much sense, but apart > > > >> from > > > >>>>>>>> not being the correct binding to describe all of the SoCs > > > >> features I see > > > >>>>>>>> two scenarios: > > > >>>>>>>> 1) A board vendor might choose to not use the internal PHY > > > >> because it > > > >>>>>>>> has bugs, lacks features (configurability) or has other issues. > > > >> For > > > >>>>>>>> instance I have heard reports that the internal PHY makes the > > > >> SoC go > > > >>>>>>>> rather hot, possibly limiting the CPU frequency. By using an > > > >> external > > > >>>>>>>> MII PHY (which are still cheaper than RGMII PHYs) this can be > > > >> avoided. > > > >>>>>>>> 2) A PHY does not necessarily need to be directly connected to > > > >>>>>>>> magnetics. Indeed quite some boards use (RG)MII to connect to a > > > >> switch > > > >>>>>>>> IC or some other network circuitry, for instance fibre > > > >> connectors. > > > >>>>>>>> > > > >>>>>>>> So I was wondering if we would need an explicit: > > > >>>>>>>> allwinner,use-internal-phy; > > > >>>>>>>> boolean DT property to signal the usage of the internal PHY? > > > >>>>>>>> Alternatively we could go with the negative version: > > > >>>>>>>> allwinner,disable-internal-phy; > > > >>>>>>>> > > > >>>>>>>> Or what about introducing a new &q
Re: [PATCH 1/6] net: stmmac: support future possible different internal phy mode
On Thu, Jun 29, 2017 at 12:23:49PM -0400, David Miller wrote: > From: Corentin Labbe > Date: Tue, 27 Jun 2017 11:28:01 +0200 > > > The current way to find if the phy is internal is to compare DT phy-mode > > and emac_variant/internal_phy. > > But it will negate a possible future SoC where an external PHY use the > > same phy mode than the internal one. > > > > By using phy-mode = "internal" we permit to have an external PHY with > > the same mode than the internal one. > > > > Reported-by: André Przywara > > Signed-off-by: Corentin Labbe > > Series applied. > > Please provide a proper "[PATCH 0/n] " header posting next time. Sorry could you wait for applying, there are a parallel thread (http://www.spinics.net/lists/devicetree/msg183520.html) and it seems finaly that internal could not be the good way to do it. Regards Sorry again, I should have sent a comment for waiting.
Re: [PATCH v2] selftests: add a generic testsuite for ethernet device
On Thu, Jun 29, 2017 at 11:26:40AM +0300, Fathi Boudra wrote:
> On 4 April 2017 at 16:32, Corentin Labbe wrote:
> > This patch add a generic testsuite for testing ethernet network device
> > driver.
> >
> > Signed-off-by: Corentin Labbe
> > ---
> >
> > Changes since v1:
> > - Test for starting master interface
> > - Changed printing format to "RESULT: $netdev: line"
> > - Use "ip link" to get device list
> >
> > tools/testing/selftests/net/Makefile | 2 +-
> > tools/testing/selftests/net/netdevice.sh | 200
> > +++
> > 2 files changed, 201 insertions(+), 1 deletion(-)
> > create mode 100755 tools/testing/selftests/net/netdevice.sh
> >
> > diff --git a/tools/testing/selftests/net/Makefile
> > b/tools/testing/selftests/net/Makefile
> > index fbfe5d0..35cbb4c 100644
> > --- a/tools/testing/selftests/net/Makefile
> > +++ b/tools/testing/selftests/net/Makefile
> > @@ -5,7 +5,7 @@ CFLAGS += -I../../../../usr/include/
> >
> > reuseport_bpf_numa: LDFLAGS += -lnuma
> >
> > -TEST_PROGS := run_netsocktests run_afpackettests test_bpf.sh
> > +TEST_PROGS := run_netsocktests run_afpackettests test_bpf.sh netdevice.sh
> > TEST_GEN_FILES = socket
> > TEST_GEN_FILES += psock_fanout psock_tpacket
> > TEST_GEN_FILES += reuseport_bpf reuseport_bpf_cpu reuseport_bpf_numa
> > diff --git a/tools/testing/selftests/net/netdevice.sh
> > b/tools/testing/selftests/net/netdevice.sh
> > new file mode 100755
> > index 000..4e00568
> > --- /dev/null
> > +++ b/tools/testing/selftests/net/netdevice.sh
> > @@ -0,0 +1,200 @@
> > +#!/bin/sh
> > +#
> > +# This test is for checking network interface
> > +# For the moment it tests only ethernet interface (but wifi could be
> > easily added)
> > +#
> > +# We assume that all network driver are loaded
> > +# if not they probably have failed earlier in the boot process and their
> > logged error will be catched by another test
> > +#
> > +
> > +# this function will try to up the interface
> > +# if already up, nothing done
> > +# arg1: network interface name
> > +kci_net_start()
> > +{
> > + netdev=$1
> > +
> > + ip link show "$netdev" |grep -q UP
> > + if [ $? -eq 0 ];then
> > + echo "SKIP: $netdev: interface already up"
> > + return 0
> > + fi
> > +
> > + ip link set "$netdev" up
> > + if [ $? -ne 0 ];then
> > + echo "FAIL: $netdev: Fail to up interface"
> > + return 1
> > + else
> > + echo "PASS: $netdev: set interface up"
> > + NETDEV_STARTED=1
> > + fi
> > + return 0
> > +}
> > +
> > +# this function will try to setup an IP and MAC address on a network
> > interface
> > +# Doing nothing if the interface was already up
> > +# arg1: network interface name
> > +kci_net_setup()
> > +{
> > + netdev=$1
> > +
> > + # do nothing if the interface was already up
> > + if [ $NETDEV_STARTED -eq 0 ];then
> > + return 0
> > + fi
> > +
> > + MACADDR='02:03:04:05:06:07'
> > + ip link set dev $netdev address "$MACADDR"
> > + if [ $? -ne 0 ];then
> > + echo "FAIL: $netdev: Cannot set MAC address"
> > + else
> > + ip link show $netdev |grep -q "$MACADDR"
> > + if [ $? -eq 0 ];then
> > + echo "PASS: $netdev: set MAC address"
> > + else
> > + echo "FAIL: $netdev: Cannot set MAC address"
> > + fi
> > + fi
> > +
> > + #check that the interface did not already have an IP
> > + ip address show "$netdev" |grep '^[[:space:]]*inet'
> > + if [ $? -eq 0 ];then
> > + echo "SKIP: $netdev: already have an IP"
> > + return 0
> > + fi
> > +
> > + # TODO what ipaddr to set ? DHCP ?
> > + echo "SKIP: $netdev: set IP address"
> > + return 0
> > +}
> > +
> > +# test an ethtool command
> > +# arg1: return code for not supported (see ethtool code source)
> > +# arg2: summary of the command
> > +# arg3: command to execute
> > +kci_netdev_ethtool
Re: [PATCH v6 05/21] net-next: stmmac: Add dwmac-sun8i
On Tue, Jun 27, 2017 at 10:37:34AM -0700, Florian Fainelli wrote: > On 06/27/2017 10:29 AM, Maxime Ripard wrote: > > On Tue, Jun 27, 2017 at 02:37:48PM +0200, Corentin Labbe wrote: > >> On Tue, Jun 27, 2017 at 11:33:56AM +0100, Andre Przywara wrote: > >>> Hi, > >>> > >>> On 27/06/17 11:23, Icenowy Zheng wrote: > >>>> > >>>> > >>>> 于 2017年6月27日 GMT+08:00 下午6:15:58, Andre Przywara > >>>> 写到: > >>>>> Hi, > >>>>> > >>>>> On 27/06/17 10:41, Maxime Ripard wrote: > >>>>>> On Tue, Jun 27, 2017 at 10:02:45AM +0100, Andre Przywara wrote: > >>>>>>> Hi, > >>>>>>> > >>>>>>> (CC:ing some people from that Rockchip dmwac series) > >>>>>>> > >>>>>>> On 27/06/17 09:21, Corentin Labbe wrote: > >>>>>>>> On Tue, Jun 27, 2017 at 04:11:21PM +0800, Chen-Yu Tsai wrote: > >>>>>>>>> On Tue, Jun 27, 2017 at 4:05 PM, Corentin Labbe > >>>>>>>>> wrote: > >>>>>>>>>> On Mon, Jun 26, 2017 at 01:18:23AM +0100, André Przywara wrote: > >>>>>>>>>>> On 31/05/17 08:18, Corentin Labbe wrote: > >>>>>>>>>>>> The dwmac-sun8i is a heavy hacked version of stmmac hardware by > >>>>>>>>>>>> allwinner. > >>>>>>>>>>>> In fact the only common part is the descriptor management and > >>>>> the first > >>>>>>>>>>>> register function. > >>>>>>>>>>> > >>>>>>>>>>> Hi, > >>>>>>>>>>> > >>>>>>>>>>> I know I am a bit late with this, but while adapting the U-Boot > >>>>> driver > >>>>>>>>>>> to the new binding I was wondering about the internal PHY > >>>>> detection: > >>>>>>>>>>> > >>>>>>>>>>> > >>>>>>>>>>> So here you seem to deduce the usage of the internal PHY by the > >>>>> PHY > >>>>>>>>>>> interface specified in the DT (MII = internal, RGMII = > >>>>> external). > >>>>>>>>>>> I think I raised this question before, but isn't it perfectly > >>>>> legal for > >>>>>>>>>>> a board to use MII with an external PHY even on those SoCs that > >>>>> feature > >>>>>>>>>>> an internal PHY? > >>>>>>>>>>> On the first glance that does not make too much sense, but apart > >>>>> from > >>>>>>>>>>> not being the correct binding to describe all of the SoCs > >>>>> features I see > >>>>>>>>>>> two scenarios: > >>>>>>>>>>> 1) A board vendor might choose to not use the internal PHY > >>>>> because it > >>>>>>>>>>> has bugs, lacks features (configurability) or has other issues. > >>>>> For > >>>>>>>>>>> instance I have heard reports that the internal PHY makes the > >>>>> SoC go > >>>>>>>>>>> rather hot, possibly limiting the CPU frequency. By using an > >>>>> external > >>>>>>>>>>> MII PHY (which are still cheaper than RGMII PHYs) this can be > >>>>> avoided. > >>>>>>>>>>> 2) A PHY does not necessarily need to be directly connected to > >>>>>>>>>>> magnetics. Indeed quite some boards use (RG)MII to connect to a > >>>>> switch > >>>>>>>>>>> IC or some other network circuitry, for instance fibre > >>>>> connectors. > >>>>>>>>>>> > >>>>>>>>>>> So I was wondering if we would need an explicit: > >>>>>>>>>>> allwinner,use-internal-phy; > >>>>>>>>>>> boolean DT property to signal the usage of the internal PHY? > >>>>>>>>>>> Alternatively we could go with the negative version: > &
Re: [PATCH v6 05/21] net-next: stmmac: Add dwmac-sun8i
On Sat, Jul 01, 2017 at 02:42:14PM -0700, Florian Fainelli wrote: > On 30/06/2017 23:53, Corentin Labbe wrote: > > On Tue, Jun 27, 2017 at 10:37:34AM -0700, Florian Fainelli wrote: > >> On 06/27/2017 10:29 AM, Maxime Ripard wrote: > >>> On Tue, Jun 27, 2017 at 02:37:48PM +0200, Corentin Labbe wrote: > >>>> On Tue, Jun 27, 2017 at 11:33:56AM +0100, Andre Przywara wrote: > >>>>> Hi, > >>>>> > >>>>> On 27/06/17 11:23, Icenowy Zheng wrote: > >>>>>> > >>>>>> > >>>>>> 于 2017年6月27日 GMT+08:00 下午6:15:58, Andre Przywara > >>>>>> 写到: > >>>>>>> Hi, > >>>>>>> > >>>>>>> On 27/06/17 10:41, Maxime Ripard wrote: > >>>>>>>> On Tue, Jun 27, 2017 at 10:02:45AM +0100, Andre Przywara wrote: > >>>>>>>>> Hi, > >>>>>>>>> > >>>>>>>>> (CC:ing some people from that Rockchip dmwac series) > >>>>>>>>> > >>>>>>>>> On 27/06/17 09:21, Corentin Labbe wrote: > >>>>>>>>>> On Tue, Jun 27, 2017 at 04:11:21PM +0800, Chen-Yu Tsai wrote: > >>>>>>>>>>> On Tue, Jun 27, 2017 at 4:05 PM, Corentin Labbe > >>>>>>>>>>> wrote: > >>>>>>>>>>>> On Mon, Jun 26, 2017 at 01:18:23AM +0100, André Przywara wrote: > >>>>>>>>>>>>> On 31/05/17 08:18, Corentin Labbe wrote: > >>>>>>>>>>>>>> The dwmac-sun8i is a heavy hacked version of stmmac hardware by > >>>>>>>>>>>>>> allwinner. > >>>>>>>>>>>>>> In fact the only common part is the descriptor management and > >>>>>>> the first > >>>>>>>>>>>>>> register function. > >>>>>>>>>>>>> > >>>>>>>>>>>>> Hi, > >>>>>>>>>>>>> > >>>>>>>>>>>>> I know I am a bit late with this, but while adapting the U-Boot > >>>>>>> driver > >>>>>>>>>>>>> to the new binding I was wondering about the internal PHY > >>>>>>> detection: > >>>>>>>>>>>>> > >>>>>>>>>>>>> > >>>>>>>>>>>>> So here you seem to deduce the usage of the internal PHY by the > >>>>>>> PHY > >>>>>>>>>>>>> interface specified in the DT (MII = internal, RGMII = > >>>>>>> external). > >>>>>>>>>>>>> I think I raised this question before, but isn't it perfectly > >>>>>>> legal for > >>>>>>>>>>>>> a board to use MII with an external PHY even on those SoCs that > >>>>>>> feature > >>>>>>>>>>>>> an internal PHY? > >>>>>>>>>>>>> On the first glance that does not make too much sense, but apart > >>>>>>> from > >>>>>>>>>>>>> not being the correct binding to describe all of the SoCs > >>>>>>> features I see > >>>>>>>>>>>>> two scenarios: > >>>>>>>>>>>>> 1) A board vendor might choose to not use the internal PHY > >>>>>>> because it > >>>>>>>>>>>>> has bugs, lacks features (configurability) or has other issues. > >>>>>>> For > >>>>>>>>>>>>> instance I have heard reports that the internal PHY makes the > >>>>>>> SoC go > >>>>>>>>>>>>> rather hot, possibly limiting the CPU frequency. By using an > >>>>>>> external > >>>>>>>>>>>>> MII PHY (which are still cheaper than RGMII PHYs) this can be > >>>>>>> avoided. > >>>>>>>>>>>>> 2) A PHY does not necessarily need to be directly connected to > >>>>>>>>>>>>> magnetics. Indeed quite some boards use (RG)MII to connect to a &
[PATCH 3/6] arm: sun8i: orangepi-one: revert "use internal phy-mode"
Since internal phy-mode is reserved for non-xMII protocol we cannot use
it with dwmac-sun8i
This reverts commit 4ac57180eab2 ("arm: sun8i: orangepi-one: use internal
phy-mode")
Signed-off-by: Corentin Labbe
---
arch/arm/boot/dts/sun8i-h3-orangepi-one.dts | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-one.dts
b/arch/arm/boot/dts/sun8i-h3-orangepi-one.dts
index 27e7ef4e42f2..6880268e8b87 100644
--- a/arch/arm/boot/dts/sun8i-h3-orangepi-one.dts
+++ b/arch/arm/boot/dts/sun8i-h3-orangepi-one.dts
@@ -100,7 +100,7 @@
&emac {
phy-handle = <&int_mii_phy>;
- phy-mode = "internal";
+ phy-mode = "mii";
allwinner,leds-active-low;
status = "okay";
};
--
2.13.0
[PATCH 1/6] arm: sun8i: nanopi-neo: revert use internal phy-mode
Since internal phy-mode is reserved for non-xMII protocol we cannot use
it with dwmac-sun8i
This reverts commit bdcc005beac9 ("arm: sun8i: nanopi-neo: use internal
phy-mode")
Signed-off-by: Corentin Labbe
---
arch/arm/boot/dts/sun8i-h3-nanopi-neo.dts | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/sun8i-h3-nanopi-neo.dts
b/arch/arm/boot/dts/sun8i-h3-nanopi-neo.dts
index 5c5ba806e2f1..78f6c24952dd 100644
--- a/arch/arm/boot/dts/sun8i-h3-nanopi-neo.dts
+++ b/arch/arm/boot/dts/sun8i-h3-nanopi-neo.dts
@@ -49,7 +49,7 @@
&emac {
phy-handle = <&int_mii_phy>;
- phy-mode = "internal";
+ phy-mode = "mii";
allwinner,leds-active-low;
status = "okay";
};
--
2.13.0
[PATCH 4/6] arm: sun8i: orangepi-zero: revert "use internal phy-mode"
Since internal phy-mode is reserved for non-xMII protocol we cannot use
it with dwmac-sun8i
This reverts commit 6066de6848d4 ("arm: sun8i: orangepi-zero: use internal
phy-mode")
Signed-off-by: Corentin Labbe
---
arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts
b/arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts
index 7c154b845baa..6713d0f2b3f4 100644
--- a/arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts
+++ b/arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts
@@ -106,7 +106,7 @@
&emac {
phy-handle = <&int_mii_phy>;
- phy-mode = "internal";
+ phy-mode = "mii";
allwinner,leds-active-low;
status = "okay";
};
--
2.13.0
[PATCH 6/6] net: stmmac: revert "support future possible different internal phy mode"
Since internal phy-mode is reserved for non-xMII protocol we cannot use
it with dwmac-sun8i
This reverts commit 1c2fa5f84683 ("net: stmmac: support future possible
different internal phy mode")
Signed-off-by: Corentin Labbe
---
drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c | 10 +++---
1 file changed, 3 insertions(+), 7 deletions(-)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
index 6c2d1da05588..fffd6d5fc907 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
@@ -638,7 +638,7 @@ static int sun8i_dwmac_set_syscon(struct stmmac_priv *priv)
{
struct sunxi_priv_data *gmac = priv->plat->bsp_priv;
struct device_node *node = priv->device->of_node;
- int ret, phy_interface;
+ int ret;
u32 reg, val;
regmap_read(gmac->regmap, SYSCON_EMAC_REG, &val);
@@ -718,11 +718,7 @@ static int sun8i_dwmac_set_syscon(struct stmmac_priv *priv)
if (gmac->variant->support_rmii)
reg &= ~SYSCON_RMII_EN;
- phy_interface = priv->plat->interface;
- /* if PHY is internal, select the mode (xMII) used by the SoC */
- if (gmac->use_internal_phy)
- phy_interface = gmac->variant->internal_phy;
- switch (phy_interface) {
+ switch (priv->plat->interface) {
case PHY_INTERFACE_MODE_MII:
/* default */
break;
@@ -936,7 +932,7 @@ static int sun8i_dwmac_probe(struct platform_device *pdev)
}
plat_dat->interface = of_get_phy_mode(dev->of_node);
- if (plat_dat->interface == PHY_INTERFACE_MODE_INTERNAL) {
+ if (plat_dat->interface == gmac->variant->internal_phy) {
dev_info(&pdev->dev, "Will use internal PHY\n");
gmac->use_internal_phy = true;
gmac->ephy_clk = of_clk_get(plat_dat->phy_node, 0);
--
2.13.0
[PATCH 2/6] arm: sun8i: orangepi-2: revert "use internal phy-mode"
Since internal phy-mode is reserved for non-xMII protocol we cannot use
it with dwmac-sun8i
This reverts commit 5a79b4f2a5e7 ("arm: sun8i: orangepi-2: use internal
phy-mode")
Signed-off-by: Corentin Labbe
---
arch/arm/boot/dts/sun8i-h3-orangepi-2.dts | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts
b/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts
index a2a2b11dfeed..17cdeae19c6f 100644
--- a/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts
+++ b/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts
@@ -120,7 +120,7 @@
&emac {
phy-handle = <&int_mii_phy>;
- phy-mode = "internal";
+ phy-mode = "mii";
allwinner,leds-active-low;
status = "okay";
};
--
2.13.0
[PATCH 5/6] arm: sun8i: orangepipc: revert "use internal phy-mode"
Since internal phy-mode is reserved for non-xMII protocol we cannot use
it with dwmac-sun8i
This reverts commit 3432a86e641c ("arm: sun8i: orangepipc: use internal
phy-mode")
Signed-off-by: Corentin Labbe
---
arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts
b/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts
index 94edeb889e55..f5f0f15a2088 100644
--- a/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts
+++ b/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts
@@ -120,7 +120,7 @@
&emac {
phy-handle = <&int_mii_phy>;
- phy-mode = "internal";
+ phy-mode = "mii";
allwinner,leds-active-low;
status = "okay";
};
--
2.13.0
[PATCH 0/6] net: stmmac: revert "support future possible different internal phy mode"
Hello The current way to find if the phy is internal is to compare DT phy-mode and emac_variant/internal_phy. But it will negate a possible future SoC where an external PHY use the same phy mode than the internal one. My first idea was to use phy-mode = "internal" but since internal phy-mode is reserved for non-xMII protocol we cannot use it with dwmac-sun8i I will send an additionnal patch for documenting more phy-mode = "internal" Corentin Labbe (6): arm: sun8i: nanopi-neo: revert use internal phy-mode arm: sun8i: orangepi-2: revert "use internal phy-mode" arm: sun8i: orangepi-one: revert "use internal phy-mode" arm: sun8i: orangepi-zero: revert "use internal phy-mode" arm: sun8i: orangepipc: revert "use internal phy-mode" net: stmmac: revert "support future possible different internal phy mode" arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts | 2 +- arch/arm/boot/dts/sun8i-h3-nanopi-neo.dts | 2 +- arch/arm/boot/dts/sun8i-h3-orangepi-2.dts | 2 +- arch/arm/boot/dts/sun8i-h3-orangepi-one.dts | 2 +- arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts| 2 +- drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c | 10 +++--- 6 files changed, 8 insertions(+), 12 deletions(-) -- 2.13.0
