[Mesa-dev] [Bug 111150] [BRW] WRC 5 asserts with gallium nine and iris.
https://bugs.freedesktop.org/show_bug.cgi?id=50 --- Comment #9 from Illia Iorin --- (In reply to Nanley Chery from comment #7) > I just updated the MR to fix the issue in iris. Please let me know if it > still helps. Updated MR fixes assert in WRC5. -- You are receiving this mail because: You are the QA Contact for the bug. You are the assignee for the bug.___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [Bug 111141] [REGRESSION] [BISECTED] [DXVK] 1-bit booleans and Elite Dangerous shader mis-optimization
https://bugs.freedesktop.org/show_bug.cgi?id=41 --- Comment #17 from Connor Abbott --- No, crashing when replaying is definitely not expected, although the result of some bug could definitely be a GPU hang. It's really strange, though, since I can replay it just fine on my machine with a similar card. Can you get the dmesg from before it crashes? One other thing you can try is to build mesa with -Dbuildtype=debug (i.e. with assertions enabled and no optimizations) and see if there's an assertion fail somewhere, or if it magically fixes itself. The only other thing I can think of would be to replay the trace with "RADV_DEBUG=shaders renderdoccmd replay ..." and uploading the output so I can diff it. I don't know if renderdoc compiles shaders in parallel, so you might need to force it to use one thread with e.g. numactl in order to get a consistent output. -- You are receiving this mail because: You are the QA Contact for the bug. You are the assignee for the bug.___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH v2] radv/gfx10: fix intensity formats by setting ALPHA_IS_ON_MSB
On Wed, Jul 24, 2019 at 4:47 PM Samuel Pitoiset
wrote:
>
> This fixes
> dEQP-VK.rasterization.primitive_size.points.point_size_*
>
> This also fixes some black squares with the Sascha SSAO demo.
>
> v2: - do not set for multiple channels
> - call vi_alpha_is_on_msb() for pre-GFX10
> - remove unused 'swap'
>
> Signed-off-by: Samuel Pitoiset
> ---
> src/amd/vulkan/radv_image.c | 17 +++--
> 1 file changed, 11 insertions(+), 6 deletions(-)
>
> diff --git a/src/amd/vulkan/radv_image.c b/src/amd/vulkan/radv_image.c
> index 0941cbb..d46946269e6 100644
> --- a/src/amd/vulkan/radv_image.c
> +++ b/src/amd/vulkan/radv_image.c
> @@ -617,6 +617,15 @@ static unsigned gfx9_border_color_swizzle(const enum
> vk_swizzle swizzle[4])
> return bc_swizzle;
> }
>
> +static bool vi_alpha_is_on_msb(struct radv_device *device, VkFormat format)
> +{
> + const struct vk_format_description *desc =
> vk_format_description(format);
> +
> + if (device->physical_device->rad_info.chip_class >= GFX10 &&
> desc->nr_channels == 1)
> + return desc->swizzle[3] == VK_SWIZZLE_X;
In vulkan we never have an alpha-only format, so this will always be false.
r-b anyway.
> +
> + return radv_translate_colorswap(format, false) <= 1;
> +}
> /**
> * Build the sampler view descriptor for a texture (GFX10).
> */
> @@ -691,11 +700,9 @@ gfx10_make_texture_descriptor(struct radv_device *device,
> state[7] = 0;
>
> if (radv_dcc_enabled(image, first_level)) {
> - unsigned swap = radv_translate_colorswap(vk_format, FALSE);
> -
> state[6] |=
> S_00A018_MAX_UNCOMPRESSED_BLOCK_SIZE(V_028C78_MAX_BLOCK_SIZE_256B) |
>
> S_00A018_MAX_COMPRESSED_BLOCK_SIZE(V_028C78_MAX_BLOCK_SIZE_128B) |
> - S_00A018_ALPHA_IS_ON_MSB(swap <= 1);
> +
> S_00A018_ALPHA_IS_ON_MSB(vi_alpha_is_on_msb(device, vk_format));
> }
>
> /* Initialize the sampler view for FMASK. */
> @@ -849,9 +856,7 @@ si_make_texture_descriptor(struct radv_device *device,
> state[5] |= S_008F24_LAST_ARRAY(last_layer);
> }
> if (image->dcc_offset) {
> - unsigned swap = radv_translate_colorswap(vk_format, FALSE);
> -
> - state[6] = S_008F28_ALPHA_IS_ON_MSB(swap <= 1);
> + state[6] =
> S_008F28_ALPHA_IS_ON_MSB(vi_alpha_is_on_msb(device, vk_format));
> } else {
> /* The last dword is unused by hw. The shader uses it to clear
> * bits in the first dword of sampler state.
> --
> 2.22.0
>
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[Mesa-dev] [Bug 111200] Xorg Graphical Corruption when using anything Vulkan on Navi10
https://bugs.freedesktop.org/show_bug.cgi?id=111200 --- Comment #2 from Matt --- Thanks Bas - that's fixed the corruption on my current snapshot Further to the newness of the navi support - should we as users be logging bugs for general instability or should we just be patient as the support for the chipset is still evolving? -- You are receiving this mail because: You are the QA Contact for the bug. You are the assignee for the bug.___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [Bug 111200] Xorg Graphical Corruption when using anything Vulkan on Navi10
https://bugs.freedesktop.org/show_bug.cgi?id=111200 Samuel Pitoiset changed: What|Removed |Added Resolution|--- |FIXED Status|NEEDINFO|RESOLVED --- Comment #3 from Samuel Pitoiset --- Please report. Thanks for confirming that this one is fixed, closing. -- You are receiving this mail because: You are the QA Contact for the bug. You are the assignee for the bug.___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH] panfrost/ci: Update kernel to 5.2
Signed-off-by: Tomeu Vizoso
---
src/gallium/drivers/panfrost/ci/debian-install.sh | 4 ++--
src/gallium/drivers/panfrost/ci/gitlab-ci.yml | 2 +-
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/src/gallium/drivers/panfrost/ci/debian-install.sh
b/src/gallium/drivers/panfrost/ci/debian-install.sh
index beff1027fd92..c42c4387729a 100644
--- a/src/gallium/drivers/panfrost/ci/debian-install.sh
+++ b/src/gallium/drivers/panfrost/ci/debian-install.sh
@@ -103,12 +103,12 @@ rm -rf /VK-GL-CTS-opengl-es-cts-3.2.5.0
### Cross-build kernel
-KERNEL_URL="https://kernel.googlesource.com/pub/scm/linux/kernel/git/torvalds/linux/+archive/refs/tags/v5.2-rc2.tar.gz";
+KERNEL_URL="https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/snapshot/linux-5.2.tar.gz";
export ARCH=${KERNEL_ARCH}
export CROSS_COMPILE="${GCC_ARCH}-"
mkdir -p /kernel
-wget -qO- ${KERNEL_URL} | tar -xz -C /kernel
+wget -qO- ${KERNEL_URL} | tar -xz --strip-components=1 -C /kernel
cd /kernel
./scripts/kconfig/merge_config.sh ${DEFCONFIG}
${PANFROST_CI_DIR}/${KERNEL_ARCH}.config
make -j12 ${KERNEL_IMAGE_NAME} dtbs
diff --git a/src/gallium/drivers/panfrost/ci/gitlab-ci.yml
b/src/gallium/drivers/panfrost/ci/gitlab-ci.yml
index 3c015678a755..a135c5dd57c2 100644
--- a/src/gallium/drivers/panfrost/ci/gitlab-ci.yml
+++ b/src/gallium/drivers/panfrost/ci/gitlab-ci.yml
@@ -16,7 +16,7 @@
variables:
UPSTREAM_REPO: mesa/mesa
DEBIAN_VERSION: testing-slim
- IMAGE_TAG: "2019-06-26-3"
+ IMAGE_TAG: "2019-07-25-1"
include:
- project: 'wayland/ci-templates'
--
2.20.1
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Re: [Mesa-dev] [PATCH] panfrost/ci: Update kernel to 5.2
A-b
On Thu, Jul 25, 2019 at 01:26:07PM +0200, Tomeu Vizoso wrote:
> Signed-off-by: Tomeu Vizoso
> ---
> src/gallium/drivers/panfrost/ci/debian-install.sh | 4 ++--
> src/gallium/drivers/panfrost/ci/gitlab-ci.yml | 2 +-
> 2 files changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/src/gallium/drivers/panfrost/ci/debian-install.sh
> b/src/gallium/drivers/panfrost/ci/debian-install.sh
> index beff1027fd92..c42c4387729a 100644
> --- a/src/gallium/drivers/panfrost/ci/debian-install.sh
> +++ b/src/gallium/drivers/panfrost/ci/debian-install.sh
> @@ -103,12 +103,12 @@ rm -rf /VK-GL-CTS-opengl-es-cts-3.2.5.0
>
>
> ### Cross-build kernel
> -KERNEL_URL="https://kernel.googlesource.com/pub/scm/linux/kernel/git/torvalds/linux/+archive/refs/tags/v5.2-rc2.tar.gz";
> +KERNEL_URL="https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/snapshot/linux-5.2.tar.gz";
> export ARCH=${KERNEL_ARCH}
> export CROSS_COMPILE="${GCC_ARCH}-"
>
> mkdir -p /kernel
> -wget -qO- ${KERNEL_URL} | tar -xz -C /kernel
> +wget -qO- ${KERNEL_URL} | tar -xz --strip-components=1 -C /kernel
> cd /kernel
> ./scripts/kconfig/merge_config.sh ${DEFCONFIG}
> ${PANFROST_CI_DIR}/${KERNEL_ARCH}.config
> make -j12 ${KERNEL_IMAGE_NAME} dtbs
> diff --git a/src/gallium/drivers/panfrost/ci/gitlab-ci.yml
> b/src/gallium/drivers/panfrost/ci/gitlab-ci.yml
> index 3c015678a755..a135c5dd57c2 100644
> --- a/src/gallium/drivers/panfrost/ci/gitlab-ci.yml
> +++ b/src/gallium/drivers/panfrost/ci/gitlab-ci.yml
> @@ -16,7 +16,7 @@
> variables:
>UPSTREAM_REPO: mesa/mesa
>DEBIAN_VERSION: testing-slim
> - IMAGE_TAG: "2019-06-26-3"
> + IMAGE_TAG: "2019-07-25-1"
>
> include:
>- project: 'wayland/ci-templates'
> --
> 2.20.1
>
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[Mesa-dev] [PATCH] radv/gfx10: use L2 for DMA copy/fill operations
It's coherent and faster. GFX7-GFX9 should also support this but
for now only uses L2 for GFX10 because it's untested on previous gens.
This fixes dEQP-VK.memory.pipeline_barrier.transfer_*
This also fixes some missing geometry in Dawn Of War III because
VBOs weren't updated correctly.
Signed-off-by: Samuel Pitoiset
---
src/amd/vulkan/si_cmd_buffer.c | 16
1 file changed, 16 insertions(+)
diff --git a/src/amd/vulkan/si_cmd_buffer.c b/src/amd/vulkan/si_cmd_buffer.c
index 21a90cb2514..94f759139ee 100644
--- a/src/amd/vulkan/si_cmd_buffer.c
+++ b/src/amd/vulkan/si_cmd_buffer.c
@@ -1501,6 +1501,14 @@ void si_cp_dma_buffer_copy(struct radv_cmd_buffer
*cmd_buffer,
unsigned dma_flags = 0;
unsigned byte_count = MIN2(size,
cp_dma_max_byte_count(cmd_buffer));
+ if (cmd_buffer->device->physical_device->rad_info.chip_class >=
GFX10) {
+ /* DMA operations via L2 are coherent and faster.
+* TODO: GFX7-GFX9 should also support this but it
+* requires tests/benchmarks.
+*/
+ dma_flags |= CP_DMA_USE_L2;
+ }
+
si_cp_dma_prepare(cmd_buffer, byte_count,
size + skipped_size + realign_size,
&dma_flags);
@@ -1545,6 +1553,14 @@ void si_cp_dma_clear_buffer(struct radv_cmd_buffer
*cmd_buffer, uint64_t va,
unsigned byte_count = MIN2(size,
cp_dma_max_byte_count(cmd_buffer));
unsigned dma_flags = CP_DMA_CLEAR;
+ if (cmd_buffer->device->physical_device->rad_info.chip_class >=
GFX10) {
+ /* DMA operations via L2 are coherent and faster.
+* TODO: GFX7-GFX9 should also support this but it
+* requires tests/benchmarks.
+*/
+ dma_flags |= CP_DMA_USE_L2;
+ }
+
si_cp_dma_prepare(cmd_buffer, byte_count, size, &dma_flags);
/* Emit the clear packet. */
--
2.22.0
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Re: [Mesa-dev] [PATCH] radv/gfx10: use L2 for DMA copy/fill operations
r-b
though it sounds like some of our cache flushes might be not ideal.
On Thu, Jul 25, 2019 at 3:35 PM Samuel Pitoiset
wrote:
>
> It's coherent and faster. GFX7-GFX9 should also support this but
> for now only uses L2 for GFX10 because it's untested on previous gens.
>
> This fixes dEQP-VK.memory.pipeline_barrier.transfer_*
>
> This also fixes some missing geometry in Dawn Of War III because
> VBOs weren't updated correctly.
>
> Signed-off-by: Samuel Pitoiset
> ---
> src/amd/vulkan/si_cmd_buffer.c | 16
> 1 file changed, 16 insertions(+)
>
> diff --git a/src/amd/vulkan/si_cmd_buffer.c b/src/amd/vulkan/si_cmd_buffer.c
> index 21a90cb2514..94f759139ee 100644
> --- a/src/amd/vulkan/si_cmd_buffer.c
> +++ b/src/amd/vulkan/si_cmd_buffer.c
> @@ -1501,6 +1501,14 @@ void si_cp_dma_buffer_copy(struct radv_cmd_buffer
> *cmd_buffer,
> unsigned dma_flags = 0;
> unsigned byte_count = MIN2(size,
> cp_dma_max_byte_count(cmd_buffer));
>
> + if (cmd_buffer->device->physical_device->rad_info.chip_class
> >= GFX10) {
> + /* DMA operations via L2 are coherent and faster.
> +* TODO: GFX7-GFX9 should also support this but it
> +* requires tests/benchmarks.
> +*/
> + dma_flags |= CP_DMA_USE_L2;
> + }
> +
> si_cp_dma_prepare(cmd_buffer, byte_count,
> size + skipped_size + realign_size,
> &dma_flags);
> @@ -1545,6 +1553,14 @@ void si_cp_dma_clear_buffer(struct radv_cmd_buffer
> *cmd_buffer, uint64_t va,
> unsigned byte_count = MIN2(size,
> cp_dma_max_byte_count(cmd_buffer));
> unsigned dma_flags = CP_DMA_CLEAR;
>
> + if (cmd_buffer->device->physical_device->rad_info.chip_class
> >= GFX10) {
> + /* DMA operations via L2 are coherent and faster.
> +* TODO: GFX7-GFX9 should also support this but it
> +* requires tests/benchmarks.
> +*/
> + dma_flags |= CP_DMA_USE_L2;
> + }
> +
> si_cp_dma_prepare(cmd_buffer, byte_count, size, &dma_flags);
>
> /* Emit the clear packet. */
> --
> 2.22.0
>
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Re: [Mesa-dev] [PATCH] radv/gfx10: use L2 for DMA copy/fill operations
On 7/25/19 3:39 PM, Bas Nieuwenhuizen wrote:
r-b
though it sounds like some of our cache flushes might be not ideal.
Yes.
On Thu, Jul 25, 2019 at 3:35 PM Samuel Pitoiset
wrote:
It's coherent and faster. GFX7-GFX9 should also support this but
for now only uses L2 for GFX10 because it's untested on previous gens.
This fixes dEQP-VK.memory.pipeline_barrier.transfer_*
This also fixes some missing geometry in Dawn Of War III because
VBOs weren't updated correctly.
Signed-off-by: Samuel Pitoiset
---
src/amd/vulkan/si_cmd_buffer.c | 16
1 file changed, 16 insertions(+)
diff --git a/src/amd/vulkan/si_cmd_buffer.c b/src/amd/vulkan/si_cmd_buffer.c
index 21a90cb2514..94f759139ee 100644
--- a/src/amd/vulkan/si_cmd_buffer.c
+++ b/src/amd/vulkan/si_cmd_buffer.c
@@ -1501,6 +1501,14 @@ void si_cp_dma_buffer_copy(struct radv_cmd_buffer
*cmd_buffer,
unsigned dma_flags = 0;
unsigned byte_count = MIN2(size,
cp_dma_max_byte_count(cmd_buffer));
+ if (cmd_buffer->device->physical_device->rad_info.chip_class >=
GFX10) {
+ /* DMA operations via L2 are coherent and faster.
+* TODO: GFX7-GFX9 should also support this but it
+* requires tests/benchmarks.
+*/
+ dma_flags |= CP_DMA_USE_L2;
+ }
+
si_cp_dma_prepare(cmd_buffer, byte_count,
size + skipped_size + realign_size,
&dma_flags);
@@ -1545,6 +1553,14 @@ void si_cp_dma_clear_buffer(struct radv_cmd_buffer
*cmd_buffer, uint64_t va,
unsigned byte_count = MIN2(size,
cp_dma_max_byte_count(cmd_buffer));
unsigned dma_flags = CP_DMA_CLEAR;
+ if (cmd_buffer->device->physical_device->rad_info.chip_class >=
GFX10) {
+ /* DMA operations via L2 are coherent and faster.
+* TODO: GFX7-GFX9 should also support this but it
+* requires tests/benchmarks.
+*/
+ dma_flags |= CP_DMA_USE_L2;
+ }
+
si_cp_dma_prepare(cmd_buffer, byte_count, size, &dma_flags);
/* Emit the clear packet. */
--
2.22.0
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[Mesa-dev] [PATCH] radv/gfx10: Disable DCC with scanout.
(a) radv does not set the DCC fields required yet. (b) radeonsi just broke their DCC metadata. Fixes: f8b6c5a1a63 "radeonsi: rewrite si_get_opaque_metadata, also for gfx10 support" --- src/amd/vulkan/radv_image.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/amd/vulkan/radv_image.c b/src/amd/vulkan/radv_image.c index 0941cbb..4bcdb70214a 100644 --- a/src/amd/vulkan/radv_image.c +++ b/src/amd/vulkan/radv_image.c @@ -161,6 +161,9 @@ radv_use_dcc_for_image(struct radv_device *device, if (image->shareable) return false; + if (radv_surface_has_scanout(device, create_info)) + return false; + /* TODO: Enable DCC for storage images. */ if ((pCreateInfo->usage & VK_IMAGE_USAGE_STORAGE_BIT) || (pCreateInfo->flags & VK_IMAGE_CREATE_EXTENDED_USAGE_BIT)) -- 2.21.0 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH] radv/gfx10: Disable DCC with scanout.
It's already disabled later in this function? On 7/25/19 4:34 PM, Bas Nieuwenhuizen wrote: (a) radv does not set the DCC fields required yet. (b) radeonsi just broke their DCC metadata. Fixes: f8b6c5a1a63 "radeonsi: rewrite si_get_opaque_metadata, also for gfx10 support" --- src/amd/vulkan/radv_image.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/amd/vulkan/radv_image.c b/src/amd/vulkan/radv_image.c index 0941cbb..4bcdb70214a 100644 --- a/src/amd/vulkan/radv_image.c +++ b/src/amd/vulkan/radv_image.c @@ -161,6 +161,9 @@ radv_use_dcc_for_image(struct radv_device *device, if (image->shareable) return false; + if (radv_surface_has_scanout(device, create_info)) + return false; + /* TODO: Enable DCC for storage images. */ if ((pCreateInfo->usage & VK_IMAGE_USAGE_STORAGE_BIT) || (pCreateInfo->flags & VK_IMAGE_CREATE_EXTENDED_USAGE_BIT)) ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH] radv/gfx10: Disable DCC with scanout.
bleh, you're right So we should not be using DCC ... On Thu, Jul 25, 2019 at 4:37 PM Samuel Pitoiset wrote: > > It's already disabled later in this function? > > On 7/25/19 4:34 PM, Bas Nieuwenhuizen wrote: > > (a) radv does not set the DCC fields required yet. > > (b) radeonsi just broke their DCC metadata. > > > > Fixes: f8b6c5a1a63 "radeonsi: rewrite si_get_opaque_metadata, also for > > gfx10 support" > > --- > > src/amd/vulkan/radv_image.c | 3 +++ > > 1 file changed, 3 insertions(+) > > > > diff --git a/src/amd/vulkan/radv_image.c b/src/amd/vulkan/radv_image.c > > index 0941cbb..4bcdb70214a 100644 > > --- a/src/amd/vulkan/radv_image.c > > +++ b/src/amd/vulkan/radv_image.c > > @@ -161,6 +161,9 @@ radv_use_dcc_for_image(struct radv_device *device, > > if (image->shareable) > > return false; > > > > + if (radv_surface_has_scanout(device, create_info)) > > + return false; > > + > > /* TODO: Enable DCC for storage images. */ > > if ((pCreateInfo->usage & VK_IMAGE_USAGE_STORAGE_BIT) || > > (pCreateInfo->flags & VK_IMAGE_CREATE_EXTENDED_USAGE_BIT)) ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH] radv: Set correct metadata size for GFX9+.
Without correct size, radeonsi assumes the metadata is incorrect, which can and will cause issues. Since the metadata is really incorrect without the size, let us fix that. Fixes: e43cc3e3afc "radv/gfx9: handle GFX9 opaque metadata" --- src/amd/vulkan/radv_image.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/amd/vulkan/radv_image.c b/src/amd/vulkan/radv_image.c index 0941cbb..541ff4086f4 100644 --- a/src/amd/vulkan/radv_image.c +++ b/src/amd/vulkan/radv_image.c @@ -1034,7 +1034,8 @@ radv_query_opaque_metadata(struct radv_device *device, for (i = 0; i <= image->info.levels - 1; i++) md->metadata[10+i] = image->planes[0].surface.u.legacy.level[i].offset >> 8; md->size_metadata = (11 + image->info.levels - 1) * 4; - } + } else + md->size_metadata = 10 * 4; } void -- 2.21.0 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH] radv: Set correct metadata size for GFX9+.
Reviewed-by: Samuel Pitoiset On 7/25/19 4:55 PM, Bas Nieuwenhuizen wrote: Without correct size, radeonsi assumes the metadata is incorrect, which can and will cause issues. Since the metadata is really incorrect without the size, let us fix that. Fixes: e43cc3e3afc "radv/gfx9: handle GFX9 opaque metadata" --- src/amd/vulkan/radv_image.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/amd/vulkan/radv_image.c b/src/amd/vulkan/radv_image.c index 0941cbb..541ff4086f4 100644 --- a/src/amd/vulkan/radv_image.c +++ b/src/amd/vulkan/radv_image.c @@ -1034,7 +1034,8 @@ radv_query_opaque_metadata(struct radv_device *device, for (i = 0; i <= image->info.levels - 1; i++) md->metadata[10+i] = image->planes[0].surface.u.legacy.level[i].offset >> 8; md->size_metadata = (11 + image->info.levels - 1) * 4; - } + } else + md->size_metadata = 10 * 4; } void ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 3/4] nvc0: allow a non-user buffer to be bound at position 0
Previously the code only handled it for positions 1 and up (as would be
for UBO's in GL). It's not a lot of trouble to handle this, and vl or
vdpau want this.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=111213
Signed-off-by: Ilia Mirkin
Cc: mesa-sta...@lists.freedesktop.org
---
.../drivers/nouveau/nvc0/nve4_compute.c | 45 +++
1 file changed, 27 insertions(+), 18 deletions(-)
diff --git a/src/gallium/drivers/nouveau/nvc0/nve4_compute.c
b/src/gallium/drivers/nouveau/nvc0/nve4_compute.c
index c5e4dec20bd..a1c40d1e6b9 100644
--- a/src/gallium/drivers/nouveau/nvc0/nve4_compute.c
+++ b/src/gallium/drivers/nouveau/nvc0/nve4_compute.c
@@ -393,23 +393,24 @@ nve4_compute_validate_constbufs(struct nvc0_context *nvc0)
uint64_t address
= nvc0->screen->uniform_bo->offset + NVC0_CB_AUX_INFO(s);
-assert(i > 0); /* we really only want uniform buffer objects */
-
-BEGIN_NVC0(push, NVE4_CP(UPLOAD_DST_ADDRESS_HIGH), 2);
-PUSH_DATAh(push, address + NVC0_CB_AUX_UBO_INFO(i - 1));
-PUSH_DATA (push, address + NVC0_CB_AUX_UBO_INFO(i - 1));
-BEGIN_NVC0(push, NVE4_CP(UPLOAD_LINE_LENGTH_IN), 2);
-PUSH_DATA (push, 4 * 4);
-PUSH_DATA (push, 0x1);
-BEGIN_1IC0(push, NVE4_CP(UPLOAD_EXEC), 1 + 4);
-PUSH_DATA (push, NVE4_COMPUTE_UPLOAD_EXEC_LINEAR | (0x20 << 1));
-
-PUSH_DATA (push, res->address + nvc0->constbuf[s][i].offset);
-PUSH_DATAh(push, res->address + nvc0->constbuf[s][i].offset);
-PUSH_DATA (push, nvc0->constbuf[5][i].size);
-PUSH_DATA (push, 0);
-BCTX_REFN(nvc0->bufctx_cp, CP_CB(i), res, RD);
+/* constbufs above 0 will are fetched via ubo info in the shader */
+if (i > 0) {
+ BEGIN_NVC0(push, NVE4_CP(UPLOAD_DST_ADDRESS_HIGH), 2);
+ PUSH_DATAh(push, address + NVC0_CB_AUX_UBO_INFO(i - 1));
+ PUSH_DATA (push, address + NVC0_CB_AUX_UBO_INFO(i - 1));
+ BEGIN_NVC0(push, NVE4_CP(UPLOAD_LINE_LENGTH_IN), 2);
+ PUSH_DATA (push, 4 * 4);
+ PUSH_DATA (push, 0x1);
+ BEGIN_1IC0(push, NVE4_CP(UPLOAD_EXEC), 1 + 4);
+ PUSH_DATA (push, NVE4_COMPUTE_UPLOAD_EXEC_LINEAR | (0x20 << 1));
+
+ PUSH_DATA (push, res->address + nvc0->constbuf[s][i].offset);
+ PUSH_DATAh(push, res->address + nvc0->constbuf[s][i].offset);
+ PUSH_DATA (push, nvc0->constbuf[s][i].size);
+ PUSH_DATA (push, 0);
+}
+BCTX_REFN(nvc0->bufctx_cp, CP_CB(i), res, RD);
res->cb_bindings[s] |= 1 << i;
}
}
@@ -554,9 +555,9 @@ nve4_compute_derive_cache_split(struct nvc0_context *nvc0,
uint32_t shared_size)
static void
nve4_compute_setup_buf_cb(struct nvc0_context *nvc0, bool gp100, void *desc)
{
- // only user constant buffers 1-6 can be put in the descriptor, the rest are
+ // only user constant buffers 0-6 can be put in the descriptor, the rest are
// loaded through global memory
- for (int i = 1; i <= 6; i++) {
+ for (int i = 0; i <= 6; i++) {
if (nvc0->constbuf[5][i].user || !nvc0->constbuf[5][i].u.buf)
continue;
@@ -609,6 +610,10 @@ nve4_compute_setup_launch_desc(struct nvc0_context *nvc0,
if (nvc0->constbuf[5][0].user || cp->parm_size) {
nve4_cp_launch_desc_set_cb(desc, 0, screen->uniform_bo,
NVC0_CB_USR_INFO(5), 1 << 16);
+
+ // Later logic will attempt to bind a real buffer at position 0. That
+ // should not happen if we've bound a user buffer.
+ assert(!nvc0->constbuf[5][0].u.buf);
}
nve4_cp_launch_desc_set_cb(desc, 7, screen->uniform_bo,
NVC0_CB_AUX_INFO(5), 1 << 11);
@@ -649,6 +654,10 @@ gp100_compute_setup_launch_desc(struct nvc0_context *nvc0,
if (nvc0->constbuf[5][0].user || cp->parm_size) {
gp100_cp_launch_desc_set_cb(desc, 0, screen->uniform_bo,
NVC0_CB_USR_INFO(5), 1 << 16);
+
+ // Later logic will attempt to bind a real buffer at position 0. That
+ // should not happen if we've bound a user buffer.
+ assert(!nvc0->constbuf[5][0].u.buf);
}
gp100_cp_launch_desc_set_cb(desc, 7, screen->uniform_bo,
NVC0_CB_AUX_INFO(5), 1 << 11);
--
2.21.0
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[Mesa-dev] [PATCH 2/4] nv50, nvc0: update sampler/view bind functions to accept NULL array
Apparently vl (or vdpau) wants to pass that in now. Handle it.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=111213
Signed-off-by: Ilia Mirkin
Cc: mesa-sta...@lists.freedesktop.org
---
src/gallium/drivers/nouveau/nv50/nv50_state.c | 14 --
src/gallium/drivers/nouveau/nvc0/nvc0_state.c | 18 ++
2 files changed, 18 insertions(+), 14 deletions(-)
diff --git a/src/gallium/drivers/nouveau/nv50/nv50_state.c
b/src/gallium/drivers/nouveau/nv50/nv50_state.c
index 8b294be6d86..a4163aa1713 100644
--- a/src/gallium/drivers/nouveau/nv50/nv50_state.c
+++ b/src/gallium/drivers/nouveau/nv50/nv50_state.c
@@ -599,19 +599,20 @@ nv50_sampler_state_delete(struct pipe_context *pipe, void
*hwcso)
static inline void
nv50_stage_sampler_states_bind(struct nv50_context *nv50, int s,
- unsigned nr, void **hwcso)
+ unsigned nr, void **hwcsos)
{
unsigned highest_found = 0;
unsigned i;
assert(nr <= PIPE_MAX_SAMPLERS);
for (i = 0; i < nr; ++i) {
+ struct nv50_tsc_entry *hwcso = hwcsos ? nv50_tsc_entry(hwcsos[i]) : NULL;
struct nv50_tsc_entry *old = nv50->samplers[s][i];
- if (hwcso[i])
+ if (hwcso)
highest_found = i;
- nv50->samplers[s][i] = nv50_tsc_entry(hwcso[i]);
+ nv50->samplers[s][i] = hwcso;
if (old)
nv50_screen_tsc_unlock(nv50->screen, old);
}
@@ -685,12 +686,13 @@ nv50_stage_set_sampler_views(struct nv50_context *nv50,
int s,
assert(nr <= PIPE_MAX_SAMPLERS);
for (i = 0; i < nr; ++i) {
+ struct pipe_sampler_view *view = views ? views[i] : NULL;
struct nv50_tic_entry *old = nv50_tic_entry(nv50->textures[s][i]);
if (old)
nv50_screen_tic_unlock(nv50->screen, old);
- if (views[i] && views[i]->texture) {
- struct pipe_resource *res = views[i]->texture;
+ if (view && view->texture) {
+ struct pipe_resource *res = view->texture;
if (res->target == PIPE_BUFFER &&
(res->flags & PIPE_RESOURCE_FLAG_MAP_COHERENT))
nv50->textures_coherent[s] |= 1 << i;
@@ -700,7 +702,7 @@ nv50_stage_set_sampler_views(struct nv50_context *nv50, int
s,
nv50->textures_coherent[s] &= ~(1 << i);
}
- pipe_sampler_view_reference(&nv50->textures[s][i], views[i]);
+ pipe_sampler_view_reference(&nv50->textures[s][i], view);
}
assert(nv50->num_textures[s] <= PIPE_MAX_SAMPLERS);
diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_state.c
b/src/gallium/drivers/nouveau/nvc0/nvc0_state.c
index a9ee7b784bd..60dcbe3ec39 100644
--- a/src/gallium/drivers/nouveau/nvc0/nvc0_state.c
+++ b/src/gallium/drivers/nouveau/nvc0/nvc0_state.c
@@ -463,22 +463,23 @@ nvc0_sampler_state_delete(struct pipe_context *pipe, void
*hwcso)
static inline void
nvc0_stage_sampler_states_bind(struct nvc0_context *nvc0,
unsigned s,
- unsigned nr, void **hwcso)
+ unsigned nr, void **hwcsos)
{
unsigned highest_found = 0;
unsigned i;
for (i = 0; i < nr; ++i) {
+ struct nv50_tsc_entry *hwcso = hwcsos ? nv50_tsc_entry(hwcsos[i]) : NULL;
struct nv50_tsc_entry *old = nvc0->samplers[s][i];
- if (hwcso[i])
+ if (hwcso)
highest_found = i;
- if (hwcso[i] == old)
+ if (hwcso == old)
continue;
nvc0->samplers_dirty[s] |= 1 << i;
- nvc0->samplers[s][i] = nv50_tsc_entry(hwcso[i]);
+ nvc0->samplers[s][i] = hwcso;
if (old)
nvc0_screen_tsc_unlock(nvc0->screen, old);
}
@@ -523,14 +524,15 @@ nvc0_stage_set_sampler_views(struct nvc0_context *nvc0,
int s,
unsigned i;
for (i = 0; i < nr; ++i) {
+ struct pipe_sampler_view *view = views ? views[i] : NULL;
struct nv50_tic_entry *old = nv50_tic_entry(nvc0->textures[s][i]);
- if (views[i] == nvc0->textures[s][i])
+ if (view == nvc0->textures[s][i])
continue;
nvc0->textures_dirty[s] |= 1 << i;
- if (views[i] && views[i]->texture) {
- struct pipe_resource *res = views[i]->texture;
+ if (view && view->texture) {
+ struct pipe_resource *res = view->texture;
if (res->target == PIPE_BUFFER &&
(res->flags & PIPE_RESOURCE_FLAG_MAP_COHERENT))
nvc0->textures_coherent[s] |= 1 << i;
@@ -548,7 +550,7 @@ nvc0_stage_set_sampler_views(struct nvc0_context *nvc0, int
s,
nvc0_screen_tic_unlock(nvc0->screen, old);
}
- pipe_sampler_view_reference(&nvc0->textures[s][i], views[i]);
+ pipe_sampler_view_reference(&nvc0->textures[s][i], view);
}
for (i = nr; i < nvc0->num_textures[s]; ++i) {
--
2.21.0
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[Mesa-dev] [PATCH 1/4] gallium/vl: fix compute tgsi shaders to not process undefined components
This caused nouveau's function handling logic to think that the MAIN
function was due to receive external parameters, and cascaded some
failures after that. Instead avoid having the undefined components in
the first place.
Fixes: f6ac0b5d71 (gallium/auxiliary/vl: Add compute shader to support video
compositor render)
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=111213
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=111217
Signed-off-by: Ilia Mirkin
---
src/gallium/auxiliary/vl/vl_compositor_cs.c | 102 ++--
1 file changed, 51 insertions(+), 51 deletions(-)
diff --git a/src/gallium/auxiliary/vl/vl_compositor_cs.c
b/src/gallium/auxiliary/vl/vl_compositor_cs.c
index 485b4174b8e..d84df7240da 100644
--- a/src/gallium/auxiliary/vl/vl_compositor_cs.c
+++ b/src/gallium/auxiliary/vl/vl_compositor_cs.c
@@ -61,7 +61,7 @@ const char *compute_shader_video_buffer =
"IMM[0] UINT32 { 8, 8, 1, 0}\n"
"IMM[1] FLT32 { 1.0, 2.0, 0.0, 0.0}\n"
- "UMAD TEMP[0], SV[1], IMM[0], SV[0]\n"
+ "UMAD TEMP[0].xy, SV[1].xyyy, IMM[0].xyyy, SV[0].xyyy\n"
/* Drawn area check */
"USGE TEMP[1].xy, TEMP[0].xyxy, CONST[4].xyxy\n"
@@ -70,20 +70,20 @@ const char *compute_shader_video_buffer =
"AND TEMP[1].x, TEMP[1]., TEMP[1].\n"
"AND TEMP[1].x, TEMP[1]., TEMP[1].\n"
- "UIF TEMP[1]\n"
+ "UIF TEMP[1].\n"
/* Translate */
"UADD TEMP[2].xy, TEMP[0], -CONST[5].xyxy\n"
- "U2F TEMP[2], TEMP[2]\n"
- "DIV TEMP[3], TEMP[2], IMM[1].\n"
+ "U2F TEMP[2].xy, TEMP[2].xyyy\n"
+ "DIV TEMP[3].xy, TEMP[2].xyyy, IMM[1].\n"
/* Scale */
- "DIV TEMP[2], TEMP[2], CONST[3].zwzw\n"
- "DIV TEMP[3], TEMP[3], CONST[3].zwzw\n"
+ "DIV TEMP[2].xy, TEMP[2].xyyy, CONST[3].zwww\n"
+ "DIV TEMP[3].xy, TEMP[3].xyyy, CONST[3].zwww\n"
/* Fetch texels */
- "TEX_LZ TEMP[4].x, TEMP[2], SAMP[0], RECT\n"
- "TEX_LZ TEMP[4].y, TEMP[3], SAMP[1], RECT\n"
- "TEX_LZ TEMP[4].z, TEMP[3], SAMP[2], RECT\n"
+ "TEX_LZ TEMP[4].x, TEMP[2].xyyy, SAMP[0], RECT\n"
+ "TEX_LZ TEMP[4].y, TEMP[3].xyyy, SAMP[1], RECT\n"
+ "TEX_LZ TEMP[4].z, TEMP[3].xyyy, SAMP[2], RECT\n"
"MOV TEMP[4].w, IMM[1].\n"
@@ -93,12 +93,12 @@ const char *compute_shader_video_buffer =
"DP4 TEMP[7].z, CONST[2], TEMP[4]\n"
"MOV TEMP[5].w, TEMP[4].\n"
- "SLE TEMP[6].w, TEMP[5], CONST[3].\n"
- "SGT TEMP[5].w, TEMP[5], CONST[3].\n"
+ "SLE TEMP[6].w, TEMP[5]., CONST[3].\n"
+ "SGT TEMP[5].w, TEMP[5]., CONST[3].\n"
- "MAX TEMP[7].w, TEMP[5], TEMP[6]\n"
+ "MAX TEMP[7].w, TEMP[5]., TEMP[6].\n"
- "STORE IMAGE[0], TEMP[0], TEMP[7], 2D\n"
+ "STORE IMAGE[0], TEMP[0].xyyy, TEMP[7], 2D\n"
"ENDIF\n"
"END\n";
@@ -124,7 +124,7 @@ const char *compute_shader_weave =
"IMM[2] UINT32 { 1, 2, 4, 0}\n"
"IMM[3] FLT32 { 0.25, 0.5, 0.125, 0.125}\n"
- "UMAD TEMP[0], SV[1], IMM[0], SV[0]\n"
+ "UMAD TEMP[0].xy, SV[1].xyyy, IMM[0].xyyy, SV[0].xyyy\n"
/* Drawn area check */
"USGE TEMP[1].xy, TEMP[0].xyxy, CONST[4].xyxy\n"
@@ -133,22 +133,22 @@ const char *compute_shader_weave =
"AND TEMP[1].x, TEMP[1]., TEMP[1].\n"
"AND TEMP[1].x, TEMP[1]., TEMP[1].\n"
- "UIF TEMP[1]\n"
- "MOV TEMP[2], TEMP[0]\n"
+ "UIF TEMP[1].\n"
+ "MOV TEMP[2].xy, TEMP[0].xyyy\n"
/* Translate */
- "UADD TEMP[2].xy, TEMP[2], -CONST[5].xyxy\n"
+ "UADD TEMP[2].xy, TEMP[2].xyyy, -CONST[5].xyxy\n"
/* Top Y */
- "U2F TEMP[2], TEMP[2]\n"
+ "U2F TEMP[2].xy, TEMP[2].xyyy\n"
"DIV TEMP[2].y, TEMP[2]., IMM[1].\n"
/* Down Y */
- "MOV TEMP[12], TEMP[2]\n"
+ "MOV TEMP[12].xy, TEMP[2].xyyy\n"
/* Top UV */
- "MOV TEMP[3], TEMP[2]\n"
+ "MOV TEMP[3].xy, TEMP[2].xyyy\n"
"DIV TEMP[3].xy, TEMP[3], IMM[1].\n"
/* Down UV */
- "MOV TEMP[13], TEMP[3]\n"
+ "MOV TEMP[13].xy, TEMP[3].xyyy\n"
/* Texture offset */
"ADD TEMP[2].x, TEMP[2]., IMM[3].\n"
@@ -162,10 +162,10 @@ const char *compute_shader_weave =
"ADD TEMP[13].y, TEMP[13]., IMM[3].\n"
/* Scale */
- "DIV TEMP[2].xy, TEMP[2], CONST[3].zwzw\n"
- "DIV TEMP[12].xy, TEMP[12], CONST[3].zwzw\n"
- "DIV TEMP[3].xy, TEMP[3], CONST[3].zwzw\n"
- "DIV TEMP[13].xy, TEMP[13], CONST[3].zwzw\n"
+ "DIV TEMP[2].xy, TEMP[2].xyyy, CONST[3].zwzw\n"
+ "DIV TEMP[12].xy, TEMP[12].xyyy, CONST[3].zwzw\n"
+ "DIV TEMP[3].xy, TEMP[3].xyyy, CONST[3].zwzw\n"
+ "DIV TEMP[13].xy, TEMP[13].xyyy, CONST[3].zwzw\n"
/* Weave offset */
"ADD TEMP[2].y, TEMP[2].,
[Mesa-dev] [PATCH 4/4] nouveau: flip DEBUG -> !NDEBUG
The meson conversion chose to change the meaning of DEBUG to "used for
debugging" to be "used for expensive things for debugging", primarily
for nir_validate. Flip things over so that we get nice things with
optimizations enabled.
While we're at it, also kill off nouveau_statebuf.h which is unused (and
has a mention of DEBUG which is how I found it).
Signed-off-by: Ilia Mirkin
---
src/gallium/drivers/nouveau/Makefile.sources | 1 -
.../drivers/nouveau/codegen/nv50_ir_driver.h | 2 +-
.../drivers/nouveau/codegen/nv50_ir_inlines.h | 2 +-
.../drivers/nouveau/codegen/nv50_ir_util.h| 8 ++---
src/gallium/drivers/nouveau/meson.build | 1 -
src/gallium/drivers/nouveau/nouveau_screen.h | 2 +-
.../drivers/nouveau/nouveau_statebuf.h| 32 ---
.../drivers/nouveau/nv50/nv50_program.c | 2 +-
.../drivers/nouveau/nvc0/nvc0_program.c | 8 ++---
.../drivers/nouveau/nvc0/nve4_compute.c | 6 ++--
10 files changed, 15 insertions(+), 49 deletions(-)
delete mode 100644 src/gallium/drivers/nouveau/nouveau_statebuf.h
diff --git a/src/gallium/drivers/nouveau/Makefile.sources
b/src/gallium/drivers/nouveau/Makefile.sources
index c6a1aff7110..6c360992a53 100644
--- a/src/gallium/drivers/nouveau/Makefile.sources
+++ b/src/gallium/drivers/nouveau/Makefile.sources
@@ -12,7 +12,6 @@ C_SOURCES := \
nouveau_mm.h \
nouveau_screen.c \
nouveau_screen.h \
- nouveau_statebuf.h \
nouveau_video.c \
nouveau_video.h \
nouveau_vp3_video_bsp.c \
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_driver.h
b/src/gallium/drivers/nouveau/codegen/nv50_ir_driver.h
index 95b3d633ee6..322bdd02557 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_driver.h
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_driver.h
@@ -54,7 +54,7 @@ struct nv50_ir_varying
ubyte si; /* TGSI semantic index */
};
-#ifdef DEBUG
+#ifndef NDEBUG
# define NV50_IR_DEBUG_BASIC (1 << 0)
# define NV50_IR_DEBUG_VERBOSE (2 << 0)
# define NV50_IR_DEBUG_REG_ALLOC (1 << 2)
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_inlines.h
b/src/gallium/drivers/nouveau/codegen/nv50_ir_inlines.h
index 4cb53ab42ed..b4ca5ed8215 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_inlines.h
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_inlines.h
@@ -222,7 +222,7 @@ Instruction *Value::getUniqueInsn() const
return (*it)->getInsn();
// should be unreachable and trigger assertion at the end
}
-#ifdef DEBUG
+#ifndef NDEBUG
if (reg.data.id < 0) {
int n = 0;
for (DefCIterator it = defs.begin(); n < 2 && it != defs.end(); ++it)
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_util.h
b/src/gallium/drivers/nouveau/codegen/nv50_ir_util.h
index affe04a2dd9..307c23d5e03 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_util.h
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_util.h
@@ -36,14 +36,14 @@
#include "util/u_inlines.h"
#include "util/u_memory.h"
-#define ERROR(args...) debug_printf("ERROR: " args)
-#define WARN(args...) debug_printf("WARNING: " args)
-#define INFO(args...) debug_printf(args)
+#define ERROR(args...) _debug_printf("ERROR: " args)
+#define WARN(args...) _debug_printf("WARNING: " args)
+#define INFO(args...) _debug_printf(args)
#define INFO_DBG(m, f, args...) \
do { \
if (m & NV50_IR_DEBUG_##f) \
- debug_printf(args); \
+ _debug_printf(args); \
} while(0)
#define FATAL(args...) \
diff --git a/src/gallium/drivers/nouveau/meson.build
b/src/gallium/drivers/nouveau/meson.build
index 64138212b5b..b3e79bf7089 100644
--- a/src/gallium/drivers/nouveau/meson.build
+++ b/src/gallium/drivers/nouveau/meson.build
@@ -32,7 +32,6 @@ files_libnouveau = files(
'nouveau_mm.h',
'nouveau_screen.c',
'nouveau_screen.h',
- 'nouveau_statebuf.h',
'nouveau_video.c',
'nouveau_video.h',
'nouveau_vp3_video_bsp.c',
diff --git a/src/gallium/drivers/nouveau/nouveau_screen.h
b/src/gallium/drivers/nouveau/nouveau_screen.h
index 1302c608bec..450c7c466be 100644
--- a/src/gallium/drivers/nouveau/nouveau_screen.h
+++ b/src/gallium/drivers/nouveau/nouveau_screen.h
@@ -6,7 +6,7 @@
#include "util/u_atomic.h"
#include "util/u_memory.h"
-#ifdef DEBUG
+#ifndef NDEBUG
# define NOUVEAU_ENABLE_DRIVER_STATISTICS
#endif
diff --git a/src/gallium/drivers/nouveau/nouveau_statebuf.h
b/src/gallium/drivers/nouveau/nouveau_statebuf.h
deleted file mode 100644
index da5d7972d9c..000
--- a/src/gallium/drivers/nouveau/nouveau_statebuf.h
+++ /dev/null
@@ -1,32 +0,0 @@
-#ifndef __NOUVEAU_STATEBUF_H__
-#define __NOUVEAU_STATEBUF_H__
-
-/* state buffers: lightweight state objects interface */
-/* relocations are not supported, but Gallium CSOs don't require them */
-
-struct nouveau_statebuf_builder
-{
- uint32_t* p;
-#ifdef DEBUG
- uint32_t* pend;
-#endif
-};
-
-#ifd
[Mesa-dev] [PATCH] nv50/ir: handle insn not being there for definition of CVT arg
This can happen if it's e.g. a uniform or a function argument.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=111217
Signed-off-by: Ilia Mirkin
Cc: mesa-sta...@lists.freedesktop.org
---
src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp
b/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp
index 0b3220903b9..bfdb923379b 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp
@@ -2080,14 +2080,15 @@ void
AlgebraicOpt::handleCVT_CVT(Instruction *cvt)
{
Instruction *insn = cvt->getSrc(0)->getInsn();
- RoundMode rnd = insn->rnd;
- if (insn->saturate ||
+ if (!insn ||
+ insn->saturate ||
insn->subOp ||
insn->dType != insn->sType ||
insn->dType != cvt->sType)
return;
+ RoundMode rnd = insn->rnd;
switch (insn->op) {
case OP_CEIL:
rnd = ROUND_PI;
--
2.21.0
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH] nv50/ir: don't consider the main compute function as taking arguments
With OpenCL, kernels can take arguments and return values (?). However in practice, there is no more TGSI compute implementation, and even if there were, it would probably have named functions and no explicit main. This improves RA considerably for compute shaders, since temps are not kept around as return values. Signed-off-by: Ilia Mirkin --- src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp index 9d0ab336c75..2dd13e70d0e 100644 --- a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp +++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp @@ -4298,7 +4298,7 @@ Converter::BindArgumentsPass::visit(Function *f) } } - if (func == prog->main && prog->getType() != Program::TYPE_COMPUTE) + if (func == prog->main /* && prog->getType() != Program::TYPE_COMPUTE */) return true; updatePrototype(&BasicBlock::get(f->cfg.getRoot())->liveSet, &Function::buildLiveSets, &Function::ins); -- 2.21.0 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
